BL808 | DigiCamel IC Datasheet

Online Datasheet

Read BL808 online.

BL808 BOUFFALOALB | Alldatasheet

Document overview

Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
PDF pages: 93

Technical content

Datasheet sections

1 Overview
2 FunctionalDescription
2.1 CPU
2.2 Cache
2.3 Memory
2.4 DMA
2.5 MemoryMap
2.6 Interrupt
2.7 Boot
2.8 Power
2.9 Clock
2.10 Peripheral
2.10.1 GPIO
2.10.2 UART
2.10.3 SPI
2.10.4 I2C
2.10.5 I2S
2.10.6 EMAC
2.10.7 TIMER
2.10.8 PWM
2.10.9 IR(IR-remote)
2.10.10 PDM
2.11 Videoencoding
2.11.1 Introduction
2.11.2 Features

Version: 1.1 Copyright @ 2022 www.bouffalolab.com

Features

Wireless(Tier-1RF Performance) – 2.4GHz RF transceiver – Wi-Fi802.11b/g/n – Bluetooth®5.x Dual-mode (BT+BLE) – Zigbee/ IEEE 802.15.4 – Wi-Fi/Bluetooth/ZigbeeCoexistence – Integratedbalun, PA/LNA – SupportExternal PA/LNA
Microcontroller – Multi-CoreRISC-V CPUs (Max Freq 480MHz) – RTCtimer up to one year – Generalpurpose timers – DMAchannels – JTAGdevelopment support – XIPQSPI flash support
AudioCodec – ADC*2(Mic*2 or Mic*1+Line-in) – DAC*1(Speaker) – SampleRate 8~192KHz, 24bit
Video/Image/Display – MJPEG, H264 (Baseline/Main) – Maximumresolution:2M(1920x1080) – Videoencoding format: * MJPEGand H264 (Baseline/Main) * 1920x1080@ 30fps + 640x480 @30fps * Upto 8-ROI(region-of-interest) – CameraSensor interface: DVPand MIPI-CSI – Displayinterface: SPI、DBI、DPI(RGB)、MIPI-DSI
AINN general HW Accelerator – NPU BLAI-100 (Bouffalo Lab AI engine) For Video/Audiodetection/recognition, etc.
Memory – Embedded32/64MB DRAM – Supportmax 128MB SPI-Nor Flash – Supportmax 256MB SPI-NAND Flash
Security – Secureboot ; Secure debug – XIPQSPI On-The-Fly AES Decryption (OTFAD) – Supportsensitive SW isolation (TrustZone) – AES-CBC/CCM/GCM/XTSmodes – TRNG(TrueRandom Number Generator) – PKA(Public Key Accelerator) for RSA/ECC
Peripherals – USB2.0 HS OTG – EthernetRMII Interface – SD-cardinterface – FourUARTinterface – TwoSPI interface – FourI2C interface – EightPWM channels – I2Sinterface – PDMinterface BL808Datasheet 2/93 @2022BouffaloLab

– General-PurposeADC – General-PurposeDAC – Generalanalog comparators (ACOMP) – PIR(Passive Infra-Red) detection – IRremote HW accelerator – Support12-Channel Touch – Flexible36 or 40 GPIOs

PowerModes (Ultra-low Power modes) – Off(~1uA); Hibernate – PowerDown Sleep (flexible)
Clock – SupportXTAL24/26/32/38.4/40 MHz – SupportXTAL32/32.768 KHz – InternalRC 32KHz/32MHz oscillator – InternalSystem PLLs
PackageType – 88pin QFN BL808Datasheet 3/93 @2022BouffaloLab

BL808Datasheet 5/93 @2022BouffaloLab

BL808Datasheet 6/93 @2022BouffaloLab

BL808Datasheet 7/93 @2022BouffaloLab

BL808Datasheet 8/93 @2022BouffaloLab

8.1 Reference Conditions for Drying Mounted or Unmounted SMD Packages (User Bake: Floor life be-

BL808Datasheet 9/93 @2022BouffaloLab

BL808 is a highly integrated AIoT chipset with Wi-Fi/BT/BLE/Zigbee, Multi-Core CPUs, Audio Codec , Video Codec andAI HW accelerator for high-performance& low-power application. BL808mainly includes two subsystems, wirelessand multimedia. ThewirelesssubsystemincludesaRISC-V32-bithigh-performanceCPU,integratedWi-Fi/BT/Zigbeewirelesssub- system, which can realize a variety of wireless connections and data transmission, and provide a variety of connec- tionand transmission experiences. The multimedia subsystem includes a RISC-V 64-bit ultra-high-performance CPU and integrates video processing modulessuchasDVP/CSI/H264/NPU,whichcanbewidelyusedinvariousAIfieldssuchasvideosurveillance/smart speakers. Thecomponents of the multimedia subsystemare as follows:

NPUHW NN co-processor (BLAI-100) generallyused for AI applications
Camerainterface
AudioCodec
VideoCodec
Sensor
Displayinterfaces PowerManagement Unit provides low-power modes. Moreover,variety ofsecurity features are supported. Peripheral interfaces include USB2.0, Ethernet, SD/MMC, SPI, UART, I2C, I2S, PWM, GPDAC, GPADC, ACOMP, PIR,Touch,IR remote, Display and GPIOs. FlexibleGPIO configurations are supported. BL808 has total 36 or40 GPIOs. BL808Datasheet 10/93 @2022BouffaloLab

USB 2.0 UART SPI I2C Touch IR Remote PWM ACOMP GPADC GPDAC I2S LCD (MIPI,RGB) RISC-V CPUs (FP,VDSP,Cache) AI NPU (BLAI - 100) RF zigbee Wi-Fi PIR GPIO MIC Speaker BT/BLE Clock PSRAM Flash SD Card USB Host/ Device Sensors Sensor (MIPI,DVP) Ethernet (RMII) 10/100M PHY Video Codec OSD MJPEG 2D DMA Camera I/F Audio Codec Display I/F RAM IPC ROM PSRAM I/F Flash I/F SDH master ScalerDMA eFuse Crypto Engine Fig.1.1: Block Diagram BL808Datasheet 11/93 @2022BouffaloLab

BL808main functions described as follows: (RISC-V) EMAC SDH USB Sec Eng DMA0 DMA1 ROM SF_Ctrl OCRAM (64K) WRAM (160K) Wi-Fi+BLE+ BT+Zigbee UART (3) SPI I2C (2) I2S IR Timer PWM IPC TZC Efuse Audio PDS HBN (RISC-V) CSI DVP Codec OSD MJPEG (Enc+Dec) UART SPI Timer IPCI2C (2) Scaler Display (DSI+DPI+DBI) NPU Mul-Media Wireless PLL (320M/400M...) PMU (POR/BOR...) OSC (32K/32M) L2SRAM VRAM GLB pSRAM Fig.2.1: System Architecture BL808Datasheet 12/93 @2022BouffaloLab

2.1 CPU

BL808contains multiple RISC-V processors inside. M0isa32-bitRISC-VCPUwitha5-stagepipelinestructure,supportsRISC-V32/16-bitmixedinstructionset,contains 64external interrupt sources, and 4bits can be used to configureinterrupt priority. D0isa64-bitRISC-VCPUwitha5-stagepipelinestructure,supportstheRISC-VRV64IMAFCVinstructionarchitec- ture,contains 67 external interrupt sources,and 3 bits can be usedto configure the interrupt priority.

2.2 Cache

The cache of BL808 improves the performance of CPU accessing external memory. M0 contains 32K instruction cacheand 16K data cache; D0contains 32K instruction cache and 32Kdata cache.

2.3 Memory

BL808memoryincludes: on-chipzero-delaySRAMmemory,read-onlymemory,write-oncememory,Embeddedflash (optional),embedded pSRAM (optional).

2.4 DMA

The DMA controller has 20 dedicated channels (8 channels each for DMA0 and DMA2, and 4 channels for DMA1) to manage data transfers between peripherals and memory to improve CPU/bus efficiency. DMA has four transfer types,memory-to-memory,memory-to-peripheral, peripheral-to-memory,and peripheral-to-peripheral modes. The DMA also supports the LLI (Linked List Item) feature, which consists of a series of linked lists that predefine multiple transfers, and then the hardware automatically completes all transfers based on the size and address of eachLLI. Peripherals supported by DMAinclude UART,I2C, SPI, ADC, IR, GPIO,Audio, I2S, PDM, DBI, DSI.

2.5 Memory Map

Table2.1: Memory Map Module Size Base Address(M0) Base Address(D0) Module Size Cache Non-cache Cache Non-cache OCRAM(MCU) 64KB 0x62020000 0x22020000 - 0x22020000 WRAM(MCU) 160KB 0x62030000 0x22030000 - 0x22030000 DRAM(MM) 512KB - 0x3EF80000 0x3EF80000 - VRAM(MM) 32KB - 0x3F000000 0x3F000000 - OCRAM and WRAM can be accessed either through AHB bus or through AXI. When the CPU accesses OCRAM BL808Datasheet 13/93 @2022BouffaloLab

using the address of 0x62020000, it will go through the internal cache and transfer AXI to AHB to achieve access to OCRAM.WhentheCPUusesthe0x22020000addresstoaccessOCRAM,itdoesnotgothroughtheinternalcache anddirectly accesses OCRAM through theAHB bus. Table2.2: Memory Map Module Target BaseAddress Size Description pSRAM pSRAM 0x54000000 64MB pSRAMmemory address space, actual sizedepends on chip model FLASH FlashA 0x58000000 64MB Applicationaddress space, the actual sizedepends on the chip model MMPERI TIMER1 0x30009000 4KB TIMER1control register SPI1 0x30008000 4KB SPI1control register MM_GLB 0x30007000 4KB Multimediaside global register DMA2D 0x30006000 4KB DMA2Dcontrol register I2C3 0x30004000 4KB I2C3control register I2C2 0x30003000 4KB I2C2control register UART3 0x30002000 4KB UART3control register DMA2 0x30001000 4KB DMA2control register MCUPERI DMA1 0x20071000 4KB DMA1control register EMAC 0x20070000 4KB EMACcontrol register AUDIO 0x20055000 4KB Audiocontrol register USB 0x20072000 4KB USBcontrol register HBN 0x2000F000 4KB Hibernateregister PDS 0x2000E000 4KB Power-Downsleep register DMA0 0x2000C000 4KB DMA0control register I2S 0x2000AB00 256B I2Scontrol register ISO11898 UART2 0x2000AA00 256B ISO11898bus control register 0x2000AA00 256B UART2control register I2C1 0x2000A900 256B I2C1control register IR 0x2000A600 256B IRcontrol register TIMER0 0x2000A500 256B TIMER0control register PWM 0x2000A400 256B PWMcontrol register I2C0 0x2000A300 256B I2C0control register SPI0 0x2000A200 256B SPI0control register UART1 0x2000A100 256B UART1control register UART0 0x2000A000 256B UART0control register eFuse 0x20056000 4KB eFusememory control register TZ 0x20005000 4KB SecurityZone partition SEC_ENG 0x20004000 4KB Securityengine control register GPIP 0x20002000 1KB Generalpurpose DAC/ADC/ACOMP interface control register GLB 0x20000000 4KB Globalcontrol register BL808Datasheet 14/93 @2022BouffaloLab

Table2.2: Memory Map Module Target BaseAddress Size Description ROM ROM 0x90000000 128KB Bootromaddress space Table2.3: MRAM/VRAM address space MRAM/VRAM Configure(reg_h2pf_sram_rel，reg_vram_sram_sel，reg_ispl_sram_rel，reg_blai_sram_rel) MRAM/VRAM 0，0，0， 0，0，0， 1，0，0， 3，0，0， 0，0，1， 0，1，0， 2，0，0， 3，1，1， MRAM 0x3EF80000 - 0x3EF8FFFF - - - - - - - 64K 0x3EF90000 - 0x3EF9FFFF - - - - - - - 64K 0x3EFA0000 - 0x3EFAFFFF - - - - - - - 64K 0x3EFB0000 - 0x3EFBFFFF 0x3EFC0000 - 0x3EFCFFFF - - - 64K - - 64K 64K 0x3EFD0000 - 0x3EFDFFFF - 64K - 64K - - 64K 64K 0x3EFE0000 - 0x3EFEFFFF - 64K 64K 64K 64K 64K 64K 64K 0x3EFF0000 - 0x3EFFFFFF 64K 64K 64K 64K 64K 64K 64K 64K VRAM 0x3F000000 - 0x3F007FFF 32K 32K 32K 32K 32K 32K 32K 32K

2.6 Interrupt

BL808supportsinternalRTCclockwake-upandexternalinterruptwake-uptorealizelow-powersleepwake-upfunction. TheCPUinterruptcontrollersupportsatotalof131maskableinterrupttriggersourcesincludingUARTinterrupt,I2C interrupt,SPI interrupt, timer interrupt, DMAinterrupt, etc. AllI/Opinscanbeconfiguredasexternalinterruptinputmode,theexternalinterruptsupportsninetriggertypes: synchronous high/low level trigger, synchronous rising/falling edge trigger, asynchronous high/low level trigger, asynchronous ris- ingedge /Falling edge trigger andsynchronous double edge trigger. BL808Datasheet 15/93 @2022BouffaloLab

2.7 Boot

BL808supports multiple boot options: UART,USB, and Flash. Table2.4: Boot mode Boot pin Level Description GPIO39

1 Bootfrom UART(GPIO20/21)/USB,this mode ismainly used for Flash download ordownload image to RAM

0 Launchapplication image from Flash

2.8 Power

PMU (power management unit) manages the power of the entire chip and is divided into running, idle, sleep, hiber- nationandpoweroffmodes. Thesoftwarecanbeconfiguredtoentersleepmodeandwake-upviaRTCtimerorEINTto achievelow-power sleep and accurate wake-upmanagement. Powerdown sleep modes are flexiblefor applications to configure as thelowest power consumption.

2.9 Clock

Clock control unit generates clocks to the core MCU and the peripheral SOC devices. The root clock source can be XTAL,PLL or RC oscillator. Dynamic power-saved byproper configurations such as sel, div,en, etc. BL808Datasheet 16/93 @2022BouffaloLab

xtal32k_soc_out rc32k_clk f32k_sel f32k_clk PMU RC32M xclk root_clk_sel[0] dig_32k_outDIV CG wifipll_480/192/120/96/80/48/32 MHz sel CPUPLL cpupll_133/66.66/40/26.66MHz (default) (cpupll_480/240/192/120/96/48/32 MHz) sel sel UHSPLL uhs pll_clk_out (2100/2000/1900/1800...MHz) sel xtal_soc_clk MIPIPLL mipipll_clk_out (~1500MHz) sel AUPLL (aupll_div3/div4/div10/div15) ( 442.368 or 440.2944MHz) audio_pll_clk (24.576/5.6448MHz)DIV eth_ref (50MHz)DIV disp_pll(27/54/74.25MHz)DIV (Choose according to scenarios) xtal_soc_clk_clkpll RF_WIFI xtal_lo_clk xtal_clk CG aupll_div1 top_aupll_div1 CG emi_aupll_div1 CG mm_aupll_div1 CG aupll_div2 top aupll_div2 CG mm_aupll_div2 CG wifipll_320MHz top_wifipll_320m CG CG emi_wifipll_320m mm_wifipll_320m CG wifipll_240MHz top_wifipll_240m CG mm_wifipll_240m CG cpupll_400MHz top_cpupll_400m CG emi_cpupll_400m CG cpupll_200MHz emi_cpupll_200m CG cpupll_160MHz top_cpupll_160m CG cpupll_100MHz top_cpupll_100m CG cpupll_80MHz top_cpupll_80m CG wifipll_160MHz mm_wifipll_160m mm_xclk reg_xclk_clk_sel rc32m_clk reg_top_muxpll_160m_sel muxpll_160m reg_top_muxpll_80m_sel muxpll_80m aupll_div2p5 aupll_div5 aupll_div6 wifipll_80MHz Fig.2.2: System ClockArchitecture BL808Datasheet 17/93 @2022BouffaloLab

(M0) pbclk (80MHz) DIVaupll_div1 pll_sel CG hclk root_clk_sel[1] CG WiFi CG CG wphy80 wiﬁpll_80MHz CG plf pbclk CG mac_core CG mac_wt DIV DIV CG lp f32k_clk BT/BLE CG CG CG plf CG lp wiﬁpll_160MHz emi_aupll_div1 reg_psramB_clk_sel CG psramB_clk DIV cpupll_400m reg_cpu_clk_sel DIV mm_cpu_clk (400MHz) reg_cpu_root_clk_sel CG MM CG DIV CG mm_bclk2x (200MHz) mm_bclk1x (160MHz) DIV DIV cnn_clk BLAI reg_dp_clk_sel DIV dp_clk Display CGDIV emi_clk_sel[1:0] CG emi_clkDIV xclk DIV phy_32m reg_mm_muxpll_320m_sel wiﬁpll_480MHz clk_soc_480m emi_cpupll_200m emi_clk_sel[2] reg_mm_muxpll_240m_sel mm_aupll_div2 mm_wiﬁpll_240m cpupll_160m mm_wiﬁpll_160m reg_mm_muxpll_160m_sel reg_bclk1x_sel[1] reg_bclk1x_sel[0] mm_muxpll_320m mm_muxpll_240m mm_muxpll_160m reg_h264_clk_sel DIV h264_core_clk H264 mm_muxpll_320m reg_cnn_clk_sel disp_pll_clk EMI mm_xclk wiﬁpll_320MHz wiﬁpll_240MHz mm_aupll_div1 mm_wiﬁpll_320m emi_wiﬁpll_320m emi_cpupll_400m pbclk cpupll_400m mm_muxpll_160m mm_muxpll_240m Fig.2.3: Moudle ClockArchitecture BL808Datasheet 18/93 @2022BouffaloLab

DIV CG ir clk (~2MHz) DIV CG gpadc clk CG gpdac clkDIV sel dig_clk_src_sel f32k_clk 1 pir_en CG i2s_ref_clk (AP) sdio master clk sel DIV ethernet clk sel DIV wifipll_32MHz 0 CG clk_adcDIV CG clk_dacDIV DIV CG i2c clk_0 I2c_clk_1(M0) DIV CG spi clk (M0) pbclk 0 sel sel cpupll _100 MHz wifipll_120 MHz xtal_soc_clk wifipll_120 MHz DIV CG flash clk sf_clk_sel muxpll _80m_clk wifipll_96MHz bclk eth_ref_clk (PAD ) xclk cpupll _100 m_clk wifipll_96m_clk DIV uart clk _0 uart_clk _1 (M0) uart_clk _2 xclk muxpll _160 m_clk mcu _bclk 0 sel CG xclk xclk CG clk_pdmDIV audio _pll_clk audio _pll_clk audio _pll_clk audio _pll_clk xclk xclk audio _pll_clk audio _pll_clk cam _ref_clk cpupll _100 m_clk wifipll_96m_clk xclk cam_ref_clk_ src_sel DIV muxpll _160 m_clk chip_clk_out_0_sel chip _clk _out[0] chip_clk_out_1_sel clk_dac clk_adc i2s_ref_clk cam _ref_clk chip _clk _out[1] chip_clk_out_2_sel wifipll_32m_clk xtal _clk i2s_ref_clk Cam _ref_clk chip _clk _out[2] chip_clk_out_3_sel wifipll_48m_clk x i2s_ref_clk Cam _ref_clk chip _clk _out[3] mm_i2c clk mm_spi clk mm_uart clk mm_bclk 1x 0 uart_clk_sel mm_bclk 1x mm_muxpll _160 m_clk mm_xclk reg_ i2c_ clk_sel mm_xclk mm_xclk mm_muxpll _160 m_clk DIV DIV DIV CG CG CG clk_dac clk_adc i2s_ref_clk cam _ref_clk sf_clk_sel2 spi clk sel_ _reg_ reg_ Fig.2.4: Peripheral ClockArchitecture BL808Datasheet 19/93 @2022BouffaloLab

2.10 Peripheral

PeripheralsincludeUSB2.0,Ethernet,SD/MMC,SPI,UART,I2C,I2S,PWM,GPDAC/GPADC/,ACOMP,PIR,Touch, IRremote, Display and GPIO.

2.10.1 GPIO

BL808Ccan have up to 40GPIOs, BL808D can have up to36 GPIOs, with the following features:

Each GPIO can be used as general purpose input and output function, pull-up/pull-down/float can be configured bysoftware
EachGPIOsupportsinterruptfunction,theinterruptsupportssynchronoushigh/lowleveltrigger,synchronousrising/falling edge trigger, asynchronous high/low level trigger, asynchronous rising/falling edge trigger and synchronous dou- bleedge trigger
EachGPIO can be set tohigh impedance state for low powermode

2.10.2 UART

Thechip has four built-in UARTs(UART0/1/2/3)with the following features:

SupportsCTS and RTSflow controlin hardware
SupportLIN master/slave function
Configurabledata bits, stop bits andparity bits
Supportsautomatic baud rate detection forcommon/fixed characters
Theworking clock can be selectedas BCLK, XCLK or 160MHz, themaximum baud rate supports 10Mbps
TXand RX have independent FIFO,FIFO depth is 32 bytes, supportDMA function

2.10.3 SPI

The chip has two built-in SPIs, which can be configured as master mode or slave mode. The SPI module clock is XCLKor 160MHz, and has thefollowing characteristics:

Inmaster mode, clock frequency upto 80 MHz
Inslave mode, the maximum allowedmaster clock frequency is 80 MHz
Thebit width of each framecan be configured as 8bit/16bit/24bit/32bit
AdaptiveFIFO depth change characteristics, suitablefor high-performance scene applications – Whenthe bit width is 32bits, the depth of the FIFOis 8 – Whenthe bit width is 24bits, the depth of the FIFOis 8 BL808Datasheet 20/93 @2022BouffaloLab

– Whenthe bit width is 16bits, the depth of the FIFOis 16 – Whenthe bit width is 8bits, the depth of the FIFOis 32

SupportDMA transfer mode

2.10.4 I2C

Thechip has four built-in I2Cinterfaces with the following features:

Supportmulti-master mode and arbitration function
Theworking clock can be selectedas BCLK or XCLK
With device address register, register address register, register address length can be set to 1 byte / 2 bytes / 3 bytes/ 4 bytes
I2Chas independent transceiver FIFO, FIFOdepth is 2 words
SupportDMA function

2.10.5 I2S

Thechip has a built-in I2Sinterface with the following features:

Supportmaster mode and slave mode
SupportLeft-justified/Right-justified/DSPandotherdataformats,thedatawidthcanbeconfiguredas8/16/24/32 bits
Theworking clock can be selectedas BCLK or XCLK
Supportsboth four-channel and six-channel modesin addition to mono/dual-channel mode
Supportsplayback of mono audio dubbingto binaural mode
Supportdynamic mute switching function
I2Shas independent transceiver FIFO, FIFOdepth is 16 words
SupportDMA function

2.10.6 EMAC

TheEMACmoduleisa10/100MbpsEthernetMediaAccessController(EthernetMAC)compatiblewithIEEE802.3, hasthe following characteristics:

Compatiblewith the MAC layer definedby IEEE 802.3
PHYsupporting MII/RMII interface defined byIEEE 802.3
Interactswith PHY through MDIO interface BL808Datasheet 21/93 @2022BouffaloLab

Supports10 Mbps and 100 MbpsEthernet
Supportshalf-duplex and full-duplex
Supportsautomatic flow control and controlframe generation in the full-duplex mode
Supportscollision detection and retransmission inthe half-duplex mode
Supportsthe generation and verification ofCRC
Generatesand removes data frame preamble
Supportsautomatic extension of short dataframes when sending
Detectstoo long/short data frames (lengthlimit)
Transmitslong data frames (> standardEthernet frame length)
Automaticallydiscards data packets with over-limitretransmission times or too small framegap
Broadcastpacket filtering
InternalRAM for storing up to128 BDs
Splitsand configures a data packetto multiple consecutive Bds when sending
Variousevent flags sent orreceived
Generatesa corresponding interrupt when anevent occurs TheEMAC timing diagram is shownbelow: Tvld TXD[1:0] TXEN RXD[1:0] RX_DV RXERR Tsu Th Tcyc Fig.2.5: EMAC TimingDiagram Table2.5: Timingconditionsfor using RX Clock Set the corresponding bit of register eth_cfg0:cfg_inv_eth_rx_clk = 1,cfg_inv_eth_tx_clk = 0,cfg_sel_eth_ref_clk_o = 0 Timing parameters(1.8V, Load = 20PF) Min. T yp Max. Unit Note Tcyc ClockCycle - 20 - ns ClockFrom ETH PHY Tvld OutputValidDelay 10.37 - 22 ns TXD/TX_EN Tsu InputSetup Time 6 - - ns RXD/RX_DV/RXERR BL808Datasheet 22/93 @2022BouffaloLab

Table2.5: Timingconditionsfor using RX Clock Set the corresponding bit of register eth_cfg0:cfg_inv_eth_rx_clk = 1,cfg_inv_eth_tx_clk = 0,cfg_sel_eth_ref_clk_o = 0 Timing parameters(1.8V, Load = 20PF) Min. T yp Max. Unit Note Th InputHold Time 0 - - ns RXD/RX_DV/RXERR Table2.6: Timingconditionswithout using RX Clock Set the corresponding bit of register eth_cfg0:cfg_inv_eth_rx_clk = 0,cfg_inv_eth_tx_clk = 0,cfg_sel_eth_ref_clk_o = 0 Timing parameters(1.8V, Load = 20PF) Min. T yp Max. Unit Note Tcyc ClockCycle - 20 - ns ClockFrom ETH PHY Tvld OutputValidDelay 10.374 - 22 ns TXD/TX_EN Tsu InputSetup Time 5 - - ns RXD/RX_DV/RXERR Th InputHold Time 3 - - ns RXD/RX_DV/RXERR

2.10.7 TIMER

Thechip has two built-in 32-bitgeneral-purpose timers and a watchdog timerwith the following features:

TheclocksourceofthegeneraltimercanbeselectedfromFCLK/32K/XTAL,andtheclocksourceofthewatchdog timercan be selected from FCLK/32K/XTAL
8-bitdivider for each counter
Each group of general-purpose timers includes three compare registers, supports compare interrupts, and sup- portsFreeRun mode and PreLoad modein counting mode
16-bitwatchdog timer,supports twowatchdog overflow methods: interruptor reset

2.10.8 PWM

Thechiphasbuilt-in2groupsofPWMsignals,eachgroupcontains4channelsofPWMsignaloutput,eachchannel canbe set to 2 channelsof complementary PWM, with the followingcharacteristics:

Threeclock sources BCLK/XCLK/32K
Frequencydivider register and period registerare 16-bit wide
Each channel PWM supports adjustable output polarity, dual threshold setting, increasing the flexibility of pulse output
Eachchannel PWM has independent deadtime setting BL808Datasheet 23/93 @2022BouffaloLab

Each PWM has an independent connection switch to choose whether to connect with the internal counter, and canset the default output levelwhen not connected
Softwarebrake and external brake signalcan put the PWM output levelinto a preset state
Upto 11trigger sourcesthat can be used to triggerADC conversions

2.10.9 IR(IR-remote)

Thechip has a built-in infraredremote control with the following features:

Supportboth sending and receiving modes
Supportsupto128-bitdatabitstobesentinnon-freemode,andcancontinuouslysenddataofanylengthinfree mode
SupportsreceivingdatawithfixedprotocolsNEC,RC-5,andreceivingdatainanyformatwithpulsewidthcounting
The clock source is XCLK, and the maximum operating frequency is 32MHz. It has powerful infrared waveform editing capabilities, and can send waveforms that conform to various protocols. The transmit power is adjustable in15 levels
ReceiveFIFO depth is 128 bytes,transmit FIFO depth is 16 bytes
Transmitsupports DMA mode

2.10.10 PDM

Thechip has a built-in PDMaudio processing module with the followingfeatures:

Integrated3-channel digital filter,cansupport 3-channel digital microphone input – Samplingrate: 8k~48k – SNR> 110dB – Datavalid bit width 20 bit – Digitalgain: -95.5 ~+32.5dB, 0.5dB step
Independentlyadjustable three-channel high-pass filter
MultiplexedGPIO input (1 clock output,2 data input)
TransmitFIFO width 32bit, depth 48
SupportDMA transfer mode BL808Datasheet 24/93 @2022BouffaloLab

2.11 Video encoding

2.11.1 Introduction

VENC adopts the H264 video coding standard, which is mainly compressed by means of prediction and motion compensation, and uses loop filtering to improve the image quality, taking into account the requirements of code streamtransmission and image quality.

2.11.2 Features

1920x1080p@ 30fps + 640x480 @30fps, BP/MP
Input: Semi-Planar YCbCr 4:2:0
Output: NALU(Network Abstract LayerUint) in byte stream format
CBR/VBRmode
Upto 8 ROIs
Upto 16 OSD coding areas
Supportsoftware mode and linkage mode
Dynamicallyconfigurable max/min quantization parameters
Dynamicallyconfigurable I/P frame target bits
Dynamicallyconfigurable I-frame distance

2.12 And sensor and display interface

2.12.1 And sensor

MIPI-CSI 1. Support1-/2-lane mode 2. Supporthardware decoding (RAW8/10/12/14,RGB565/888, YUV4228-/10-bit) or software decoding
DVP 1. SupportRAW12-bit data 2. SupportYUV/RGB 8-bit format 3. Supportimage compression mode BL808Datasheet 25/93 @2022BouffaloLab

2.12.2 And monitor

MIPI-DSI 1. Support1-/2-/4-lane mode 2. SupportRGB565/666/888 and YUV422 8-bit format 3. SupportSync Event Mode or SyncPulse Mode 4. SupportEscape Mode, and can beused with DMA function
MIPI-DBI 1. SupportType-B(8-bit), Type-COption 1 (3-wire) and Type-COption 3 (4-wire) modes 2. SupportRGB565/666/888 format 3. Built-inYUV2RGB conversion module 4. SupportDMA function
MIPI-DPI 1. Supportdata 16-bit mode 2. SupportRGB565 format
QSPI 1. CMD/ADDR/DATAcan choose 1-/4-wiremode arbitrarily,so QSPI111/114/144/444modecan be supported 2. SupportRGB565/666/888 format 3. Built-inYUV2RGB conversion module 4. SupportDMA function BL808Datasheet 26/93 @2022BouffaloLab

BL808C88-pin package includes 26 powerpins, 22 analog pins, and 40flexible GPIO pins. 27 28 29 30 31 32 33 2223 24 25 26 34 86 87 88 79 78 77 76 75 74 73 85 84 83 82 81 80 72 QFN88C VDD33_RF VDD33_RF VDDCORE SW_DCDC18 VDD33_DCDC18 DOVDD18_OUT VDD33_CIS(USB) USB_DP USB_DN VDDIO1 PAD_GPIO_0 PAD_GPIO_1 PAD_GPIO_2 PAD_GPIO_3 PAD_GPIO_4 PAD_GPIO_5 ANT MICBIAS VREF VSS_CODEC AVDD15_RF AVDD18_RF RSTB_RTC VDDIO2(AON) XTAL32K_OUT (PAD_GPIO_41) XTAL32K_IN (PAD_GPIO_40) PAD_GPIO_11 PAD_GPIO_12 VDDCORE XTAL_OUT XTAL_IN AVDD33_CODEC AVDD25_CODEC VDDIO3 MIC_1P MIC_1N MIC2P(PADC_AIP1) PAD_GPIO_21 PAD_GPIO_20 PAD_GPIO_19 PAD_GPIO_18 PAD_GPIO_17 PAD_GPIO_16 LINEOUT_1P MIC2N(PADC_AIN1) VSS_DCDC PAD_GPIO_24 PAD_GPIO_25 PAD_GPIO_26 VDD33_DCDC11 SW_DCDC11 DCDC11_VOUT PAD_GPIO_39 PAD_GPIO_36 PAD_GPIO_35 PAD_GPIO_34 VDD18_FLASH VDDIO4 PAD_GPIO_28 PAD_GPIO_27 PAD_GPIO_38 PAD_GPIO_37 VDD15_CIS VSS_IDO28CIS VDD28_CIS PAD_GPIO_6 PAD_GPIO_7 PAD_GPIO_8 35 36 37 38 39 40 41 42 43 44 PU_CHIP AVDD33_RTC PAD_GPIO_13 PAD_GPIO_14 PAD_GPIO_15 PAD_GPIO_22 PAD_GPIO_23 AVDD12 AVDD12 CSI_DN<1> CSI_DP<1> CSI_CLK_DN CSI_CLK_DP CSI_DN<0> CSI_DP<0> 71 70 69 68 67 PAD_GPIO_29 PAD_GPIO_30 PAD_GPIO_31 PAD_GPIO_32 PAD_GPIO_33 Fig.3.1: BL808C Pinlayout BL808Datasheet 27/93 @2022BouffaloLab

BL808D88-pin package includes 27 powerpins, 25 analog pins, and 36flexible GPIO pins. 27 28 29 30 31 32 33 2223 24 25 26 34 86 87 88 79 78 77 76 75 74 73 85 84 83 82 81 80 72 QFN88D VDD33_RF VDD33_RF VDDCORE SW_DCDC18 VDD33_DCDC18 DOVDD18_OUT VDD33_CIS(USB) VDDIO1 PAD_GPIO_0 PAD_GPIO_1 PAD_GPIO_2 PAD_GPIO_3 PAD_GPIO_4 PAD_GPIO_5 ANT MICBIAS VREF VSS_CODEC AVDD15_RF AVDD18_RF AVDD33_AON XTAL32K_OUT (PAD_GPIO_41) XTAL32K_IN (PAD_GPIO_40) PAD_GPIO_11 PAD_GPIO_12 VDDCORE XTAL_OUT XTAL_IN AVDD33_CODEC AVDD25_CODEC VDDIO3 MIC_1P MIC_1N PAD_GPIO_21 PAD_GPIO_20 PAD_GPIO_19 PAD_GPIO_18 PAD_GPIO_17 PAD_GPIO_16 LINEOUT_1P VSS_DCDC DSI_DN<0> DSI_DP<0> DSI_DN<1> VDD33_DCDC11 SW_DCDC11 DCDC11_VOUT PAD_GPIO_39 PAD_GPIO_36 PAD_GPIO_35 PAD_GPIO_34 VDD18_FLASH VDDIO4 DSI_CLK_DN DSI_DP<1> PAD_GPIO_38 PAD_GPIO_37 VDD15_CIS VSS_IDO28CIS VDD28_CIS PAD_GPIO_6 PAD_GPIO_7 PAD_GPIO_8 35 36 37 38 39 40 41 42 43 44 PU_CHIP PAD_GPIO_13 PAD_GPIO_14 PAD_GPIO_15 PAD_GPIO_22 PAD_GPIO_23 AVDD12 AVDD12 CSI_DN<1> CSI_DP<1> CSI_CLK_DN CSI_CLK_DP CSI_DN<0> CSI_DP<0> 71 70 69 68 67 DSI_CLK_DP DSI_DN<2> DSI_DP<2> DSI_DN<3> DSI_DP<3> PAD_GPIO_44 PAD_GPIO_45 PAD_GPIO_9 PAD_GPIO_10 PAD_GPIO_42 PAD_GPIO_43 Fig.3.2: BL808D Pinlayout Table3.1: Pin Description BL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function DescriptionBL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function Description 1 1 - Power SW_DCDC18 - - SW_DCDC18 DCDCswitchoutput,connectedtopowerinductor 2 2 - Power VDD33_DCDC18 - - VDD33_DCDC18 DCDCpower input, 3.3V 3 3 - Power DOVDD18_OUT - - DOVDD18_OUT DCDC mode, feedback voltage input, 1.8V LDO mode,power output, 1.8V 4 4 - Power VDD15_CIS - - VDD15_CIS Integrated LDO output to power the image sensor digitalpower DVDD 5 5 - Power VSS_IDO28CIS - - VSS_IDO28CIS ConnecttotheimagesensoranaloggroundAGND 6 6 - Power VDD28_CIS - - VDD28_CIS Integrated LDO output to power the image sensor analogpower supply AVDD 7 7 - Power VDD33_CIS(USB) - - VDD33_CIS(USB) IntegratedLDO VDD28_CIS input, 3.3V 8 - VDDIO_1 DI/DO USB_DP - - USB_DP USB2.0differentialdata cable+ 9 - VDDIO_1 DI/DO USB_DN - - USB_DN USB2.0differentialdata cable BL808Datasheet 28/93 @2022BouffaloLab

Table3.1: Pin Description BL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function DescriptionBL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function Description - 8 VDDIO_1 DI/DO PAD_GPIO_44 0 - - - 1 - SPI_SS SPI_SS 2 - - - 3 - I2S_BCLK I2S_BCLK 4 - - 5 - I2C0_SCL I2C0_SCL 6 - I2C1_SCL I2C1_SCL uart_sig_8_sel=0 UART0_RTS UART0_RTS uart_sig_8_sel=1 UART0_CTS UART0_CTS uart_sig_8_sel=2 UART0_TXD UART0_TXD uart_sig_8_sel=3 UART0_RXD UART0_RXD uart_sig_8_sel=4 UART1_RTS UART1_RTS uart_sig_8_sel=5 UART1_CTS UART1_CTS uart_sig_8_sel=6 UART1_TXD UART1_TXD uart_sig_8_sel=7 UART1_RXD UART1_RXD uart_sig_8_sel=8 UART2_RTS UART2_RTS uart_sig_8_sel=9 UART2_CTS UART2_CTS uart_sig_8_sel=10 UART2_TXD UART2_TXD uart_sig_8_sel=11 UART2_RXD UART2_RXD 8 - - - 9 - - - 10 - - - 11 - SWGPIO44 SWGPIO44 reg_pwm1_io_sel=0 PWM0_CH0P PWM0_CH0P reg_pwm1_io_sel=1 PWM0_CH2P PWM0_CH2P reg_pwm2_io_sel=0 PWM1_CH0P PWM1_CH0P reg_pwm2_io_sel=1 PWM0_BREAK_EXT PWM0_BREAK_EXT 18 - MM_SPI_SS MM_SPI_SS 19 - MM_I2C0_SCL MM_I2C0_SCL 20 - MM_I2C1_SCL MM_I2C1_SCL 21 - MM_UART_TXD MM_UART_TXD 22 - - - 23 - DBI_CSn DBI_CSn 24 - - - 26 - M0_JTAG_TCLK M0_JTAG_TCLK 27 - D0_JTAG_TCK D0_JTAG_TCK BL808Datasheet 29/93 @2022BouffaloLab

Table3.1: Pin Description BL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function DescriptionBL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function Description - 9 VDDIO_1 DI/DO PAD_GPIO_45 0 - - - 1 - SPI_MOSI1 SPI_MOSI 2 - - - 3 - I2S_FS I2S_FS 4 - - 5 - I2C0_SDA I2C0_SDA 6 - I2C1_SDA I2C1_SDA uart_sig_9_sel=0 UART0_RTS UART0_RTS uart_sig_9_sel=1 UART0_CTS UART0_CTS uart_sig_9_sel=2 UART0_TXD UART0_TXD uart_sig_9_sel=3 UART0_RXD UART0_RXD uart_sig_9_sel=4 UART1_RTS UART1_RTS uart_sig_9_sel=5 UART1_CTS UART1_CTS uart_sig_9_sel=6 UART1_TXD UART1_TXD uart_sig_9_sel=7 UART1_RXD UART1_RXD uart_sig_9_sel=8 UART2_RTS UART2_RTS uart_sig_9_sel=9 UART2_CTS UART2_CTS uart_sig_9_sel=10 UART2_TXD UART2_TXD uart_sig_9_sel=11 UART2_RXD UART2_RXD 8 - - - 9 - - - 10 - - - 11 - SWGPIO45 SWGPIO45 reg_pwm1_io_sel=0 PWM0_CH1P PWM0_CH1P reg_pwm1_io_sel=1 PWM0_CH2N PWM0_CH2N reg_pwm2_io_sel=0 PWM1_CH1P PWM1_CH1P reg_pwm2_io_sel=1 PWM0_CH0P PWM0_CH0P 18 - MM_SPI_MOSI MM_SPI_MOSI 19 - MM_I2C0_SDA MM_I2C0_SDA 20 - MM_I2C1_SDA MM_I2C1_SDA 21 - MM_UART_RXD MM_UART_RXD 22 - - - 23 - DBI_DCn DBI_DCn 24 - - - 26 - M0_JTAG_TDI M0_JTAG_TDI 27 - D0_JTAG_TDI D0_JTAG_TDI 10 10 - Power VDDIO1 - - VDDIO1 GPIO0~8,GPIO44~45 power supply,3.3V/1.8V BL808Datasheet 30/93 @2022BouffaloLab

Table3.1: Pin Description BL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function DescriptionBL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function Description 11 11 VDDIO_1 DI/DO PAD_GPIO_0 0 - SDH_CLK SDH_CLK 1 - SPI_SS SPI_SS 2 - - - 3 - I2S_BCLK I2S_BCLK 4 - PDM_0_IN PDM_0_IN 5 - I2C0_SCL I2C0_SCL 6 - I2C1_SCL I2C1_SCL uart_sig_0_sel=0 UART0_RTS UART0_RTS uart_sig_0_sel=1 UART0_CTS UART0_CTS uart_sig_0_sel=2 UART0_TXD UART0_TXD uart_sig_0_sel=3 UART0_RXD UART0_RXD uart_sig_0_sel=4 UART1_RTS UART1_RTS uart_sig_0_sel=5 UART1_CTS UART1_CTS uart_sig_0_sel=6 UART1_TXD UART1_TXD uart_sig_0_sel=7 UART1_RXD UART1_RXD uart_sig_0_sel=8 UART2_RTS UART2_RTS uart_sig_0_sel=9 UART2_CTS UART2_CTS uart_sig_0_sel=10 UART2_TXD UART2_TXD uart_sig_0_sel=11 UART2_RXD UART2_RXD 8 - - - 9 - - - 10 - USB20_RREF_EXT USB20_RREF_EXT 11 - SWGPIO0 SWGPIO0 reg_pwm1_io_sel=0 PWM0_CH0P PWM0_CH0P reg_pwm1_io_sel=1 PWM0_CH0P PWM0_CH0P reg_pwm2_io_sel=0 PWM1_CH0P PWM1_CH0P reg_pwm2_io_sel=1 PWM0_BREAK_EXT PWM0_BREAK_EXT 18 - MM_SPI_SS MM_SPI_SS 19 - MM_I2C0_SCL MM_I2C0_SCL 20 - MM_I2C1_SCL MM_I2C1_SCL 21 - MM_UART_TXD MM_UART_TXD 22 - - - 23 - DBI_CSn DBI_CSn 24 - - - 26 - M0_JTAG_TCLK M0_JTAG_TCLK 27 - D0_JTAG_TCK D0_JTAG_TCK BL808Datasheet 31/93 @2022BouffaloLab

Table3.1: Pin Description BL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function DescriptionBL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function Description 12 12 VDDIO_1 DI/DO PAD_GPIO_1 0 - SDH_CMD SDH_CMD 1 - SPI_MOSI SPI_MOSI 2 - - - 3 - I2S_FS I2S_FS 4 - PDM_1_IN PDM_1_IN 5 - I2C0_SDA I2C0_SDA 6 - I2C1_SDA I2C1_SDA uart_sig_1_sel=0 UART0_RTS UART0_RTS uart_sig_1_sel=1 UART0_CTS UART0_CTS uart_sig_1_sel=2 UART0_TXD UART0_TXD uart_sig_1_sel=3 UART0_RXD UART0_RXD uart_sig_1_sel=4 UART1_RTS UART1_RTS uart_sig_1_sel=5 UART1_CTS UART1_CTS uart_sig_1_sel=6 UART1_TXD UART1_TXD uart_sig_1_sel=7 UART1_RXD UART1_RXD uart_sig_1_sel=8 UART2_RTS UART2_RTS uart_sig_1_sel=9 UART2_CTS UART2_CTS uart_sig_1_sel=10 UART2_TXD UART2_TXD uart_sig_1_sel=11 UART2_RXD UART2_RXD 8 - - - 9 - - - 10 - - - 11 - SWGPIO1 SWGPIO1 reg_pwm1_io_sel=0 PWM0_CH1P PWM0_CH1P reg_pwm1_io_sel=1 PWM0_CH0N PWM0_CH0N reg_pwm2_io_sel=0 PWM1_CH1P PWM1_CH1P reg_pwm2_io_sel=1 PWM0_CH0P PWM0_CH0P 18 - MM_SPI_MOSI MM_SPI_MOSI 19 - MM_I2C0_SDA MM_I2C0_SDA 20 - MM_I2C1_SDA MM_I2C1_SDA 21 - MM_UART_RXD MM_UART_RXD 22 - - - 23 - DBI_DCn DBI_DCn 24 - - - 26 - M0_JTAG_TDI M0_JTAG_TDI 27 - D0_JTAG_TDI D0_JTAG_TDI BL808Datasheet 32/93 @2022BouffaloLab

Table3.1: Pin Description BL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function DescriptionBL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function Description 13 13 VDDIO_1 DI/DO PAD_GPIO_2 0 - SDH_DAT0 SDH_DAT0 1 - SPI_MISO SPI_MISO 2 - - - 3 - I2S_DI/I2S_RCLK_O I2S_DI/I2S_RCLK_O 4 - PDM_CLK_O PDM_CLK_O 5 - I2C0_SCL I2C0_SCL 6 - I2C1_SCL I2C1_SCL uart_sig_2_sel=0 UART0_RTS UART0_RTS uart_sig_2_sel=1 UART0_CTS UART0_CTS uart_sig_2_sel=2 UART0_TXD UART0_TXD uart_sig_2_sel=3 UART0_RXD UART0_RXD uart_sig_2_sel=4 UART1_RTS UART1_RTS uart_sig_2_sel=5 UART1_CTS UART1_CTS uart_sig_2_sel=6 UART1_TXD UART1_TXD uart_sig_2_sel=7 UART1_RXD UART1_RXD uart_sig_2_sel=8 UART2_RTS UART2_RTS uart_sig_2_sel=9 UART2_CTS UART2_CTS uart_sig_2_sel=10 UART2_TXD UART2_TXD uart_sig_2_sel=11 UART2_RXD UART2_RXD 8 - - - 9 - - - 10 - - - 11 - SWGPIO2 SWGPIO2 reg_pwm1_io_sel=0 PWM0_CH2P PWM0_CH2P reg_pwm1_io_sel=1 PWM0_CH1P PWM0_CH1P reg_pwm2_io_sel=0 PWM1_CH2P PWM1_CH2P reg_pwm2_io_sel=1 PWM0_CH1P PWM0_CH1P 18 - MM_SPI_MISO MM_SPI_MISO 19 - MM_I2C0_SCL MM_I2C0_SCL 20 - MM_I2C1_SCL MM_I2C1_SCL 21 - MM_UART_RTS MM_UART_RTS 22 - - - 23 - DBI_SCL DBI_SCL 24 - - - 26 - M0_JTAG_TMS M0_JTAG_TMS 27 - D0_JTAG_TMS D0_JTAG_TMS BL808Datasheet 33/93 @2022BouffaloLab

Table3.1: Pin Description BL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function DescriptionBL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function Description 14 14 VDDIO_1 DI/DO PAD_GPIO_3 0 - SDH_DAT1 SDH_DAT1 1 - SPI_SCLK SPI_SCLK 2 - - - 3 - I2S_DO/I2S_RCLK_O I2S_DO/I2S_RCLK_O 4 - PDM_0_IN PDM_0_IN 5 - I2C0_SDA I2C0_SDA 6 - I2C1_SDA I2C1_SDA uart_sig_3_sel=0 UART0_RTS UART0_RTS uart_sig_3_sel=1 UART0_CTS UART0_CTS uart_sig_3_sel=2 UART0_TXD UART0_TXD uart_sig_3_sel=3 UART0_RXD UART0_RXD uart_sig_3_sel=4 UART1_RTS UART1_RTS uart_sig_3_sel=5 UART1_CTS UART1_CTS uart_sig_3_sel=6 UART1_TXD UART1_TXD uart_sig_3_sel=7 UART1_RXD UART1_RXD uart_sig_3_sel=8 UART2_RTS UART2_RTS uart_sig_3_sel=9 UART2_CTS UART2_CTS uart_sig_3_sel=10 UART2_TXD UART2_TXD uart_sig_3_sel=11 UART2_RXD UART2_RXD 8 - - - 9 - - - 10 - - - 11 - SWGPIO3 SWGPIO3 reg_pwm1_io_sel=0 PWM0_CH3P PWM0_CH3P reg_pwm1_io_sel=1 PWM0_CH1N PWM0_CH1N reg_pwm2_io_sel=0 PWM1_CH3P PWM1_CH3P reg_pwm2_io_sel=1 PWM0_CH2P PWM0_CH2P 18 - MM_SPI_SCLK MM_SPI_SCLK 19 - MM_I2C0_SDA MM_I2C0_SDA 20 - MM_I2C1_SDA MM_I2C1_SDA 21 - MM_UART_CTS MM_UART_CTS 22 - - - 23 - DBI_SDA DBI_SDA 24 - - - 26 - M0_JTAG_TDO M0_JTAG_TDO 27 - D0_JTAG_TDO D0_JTAG_TDO BL808Datasheet 34/93 @2022BouffaloLab

Table3.1: Pin Description BL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function DescriptionBL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function Description 15 15 VDDIO_1 DI/DO PAD_GPIO_4 0 - SDH_DAT2 SDH_DAT2 1 - SPI_SS SPI_SS 2 - - - 3 - I2S_BCLK I2S_BCLK 4 - PDM_1_IN PDM_1_IN 5 - I2C0_SCL I2C0_SCL 6 - I2C1_SCL I2C1_SCL uart_sig_4_sel=0 UART0_RTS UART0_RTS uart_sig_4_sel=1 UART0_CTS UART0_CTS uart_sig_4_sel=2 UART0_TXD UART0_TXD uart_sig_4_sel=3 UART0_RXD UART0_RXD uart_sig_4_sel=4 UART1_RTS UART1_RTS uart_sig_4_sel=5 UART1_CTS UART1_CTS uart_sig_4_sel=6 UART1_TXD UART1_TXD uart_sig_4_sel=7 UART1_RXD UART1_RXD uart_sig_4_sel=8 UART2_RTS UART2_RTS uart_sig_4_sel=9 UART2_CTS UART2_CTS uart_sig_4_sel=10 UART2_TXD UART2_TXD uart_sig_4_sel=11 UART2_RXD UART2_RXD 8 - - - 9 - - - 10 - ADC_CH2 ADC_CH2 11 - SWGPIO4 SWGPIO4 reg_pwm1_io_sel=0 PWM0_CH0P PWM0_CH0P reg_pwm1_io_sel=1 PWM0_CH2P PWM0_CH2P reg_pwm2_io_sel=0 PWM1_CH0P PWM1_CH0P reg_pwm2_io_sel=1 PWM0_BREAK_EXT PWM0_BREAK_EXT 18 - MM_SPI_SS MM_SPI_SS 19 - MM_I2C0_SCL MM_I2C0_SCL 20 - MM_I2C1_SCL MM_I2C1_SCL 21 - MM_UART_TXD MM_UART_TXD 22 - - - 23 - DBI_CSn DBI_CSn 24 - - - 26 - M0_JTAG_TCLK M0_JTAG_TCLK 27 - D0_JTAG_TCK D0_JTAG_TCK BL808Datasheet 35/93 @2022BouffaloLab

Table3.1: Pin Description BL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function DescriptionBL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function Description 16 16 VDDIO_1 DI/DO PAD_GPIO_5 0 - SDH_DAT3 SDH_DAT3 1 - SPI_MOSI SPI_MOSI 2 - - - 3 - I2S_FS I2S_FS 4 - PDM_CLK_O PDM_CLK_O 5 - I2C0_SDA I2C0_SDA 6 - I2C1_SDA I2C1_SDA uart_sig_5_sel=0 UART0_RTS UART0_RTS uart_sig_5_sel=1 UART0_CTS UART0_CTS uart_sig_5_sel=2 UART0_TXD UART0_TXD uart_sig_5_sel=3 UART0_RXD UART0_RXD uart_sig_5_sel=4 UART1_RTS UART1_RTS uart_sig_5_sel=5 UART1_CTS UART1_CTS uart_sig_5_sel=6 UART1_TXD UART1_TXD uart_sig_5_sel=7 UART1_RXD UART1_RXD uart_sig_5_sel=8 UART2_RTS UART2_RTS uart_sig_5_sel=9 UART2_CTS UART2_CTS uart_sig_5_sel=10 UART2_TXD UART2_TXD uart_sig_5_sel=11 UART2_RXD UART2_RXD 8 - - - 9 - - - 10 - ADC_CH1 ADC_CH1 11 - SWGPIO5 SWGPIO5 reg_pwm1_io_sel=0 PWM0_CH1P PWM0_CH1P reg_pwm1_io_sel=1 PWM0_CH2N PWM0_CH2N reg_pwm2_io_sel=0 PWM1_CH1P PWM1_CH1P reg_pwm2_io_sel=1 PWM0_CH0P PWM0_CH0P 18 - MM_SPI_MOSI MM_SPI_MOSI 19 - MM_I2C0_SDA MM_I2C0_SDA 20 - MM_I2C1_SDA MM_I2C1_SDA 21 - MM_UART_RXD MM_UART_RXD 22 - - - 23 - DBI_DCn DBI_DCn 24 - - - 26 - M0_JTAG_TDI M0_JTAG_TDI 27 - D0_JTAG_TDI D0_JTAG_TDI BL808Datasheet 36/93 @2022BouffaloLab

Table3.1: Pin Description BL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function DescriptionBL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function Description 17 17 VDDIO_1 DI/DO PAD_GPIO_6 0 - - - 1 - SPI_MISO SPI_MISO 2 - - - 3 - I2S_DI/I2S_RCLK_O I2S_DI/I2S_RCLK_O 4 - - - 5 - I2C0_SCL I2C0_SCL 6 - I2C1_SCL I2C1_SCL uart_sig_6_sel=0 UART0_RTS UART0_RTS uart_sig_6_sel=1 UART0_CTS UART0_CTS uart_sig_6_sel=2 UART0_TXD UART0_TXD uart_sig_6_sel=3 UART0_RXD UART0_RXD uart_sig_6_sel=4 UART1_RTS UART1_RTS uart_sig_6_sel=5 UART1_CTS UART1_CTS uart_sig_6_sel=6 UART1_TXD UART1_TXD uart_sig_6_sel=7 UART1_RXD UART1_RXD uart_sig_6_sel=8 UART2_RTS UART2_RTS uart_sig_6_sel=9 UART2_CTS UART2_CTS uart_sig_6_sel=10 UART2_TXD UART2_TXD uart_sig_6_sel=11 UART2_RXD UART2_RXD 8 - - - 9 - - - 10 - ADC_CH4 ADC_CH4 11 - SWGPIO6 SWGPIO6 reg_pwm1_io_sel=0 PWM0_CH2P PWM0_CH2P reg_pwm1_io_sel=1 PWM0_CH3P PWM0_CH3P reg_pwm2_io_sel=0 PWM1_CH2P PWM1_CH2P reg_pwm2_io_sel=1 PWM0_CH1P PWM0_CH1P 18 - MM_SPI_MISO MM_SPI_MISO 19 - MM_I2C0_SCL MM_I2C0_SCL 20 - MM_I2C1_SCL MM_I2C1_SCL 21 - MM_UART_RTS MM_UART_RTS 22 - - - 23 - DBI_SCL DBI_SCL 24 - - - 26 - M0_JTAG_TMS M0_JTAG_TMS 27 - D0_JTAG_TMS D0_JTAG_TMS BL808Datasheet 37/93 @2022BouffaloLab

Table3.1: Pin Description BL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function DescriptionBL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function Description 18 18 VDDIO_1 DI/DO PAD_GPIO_7 0 - - - 1 - SPI_SCLK SPI_SCLK 2 - - - 3 - I2S_DO/I2S_RCLK_O I2S_DO/I2S_RCLK_O 4 - - - 5 - I2C0_SDA I2C0_SDA 6 - I2C1_SDA I2C1_SDA uart_sig_7_sel=0 UART0_RTS UART0_RTS uart_sig_7_sel=1 UART0_CTS UART0_CTS uart_sig_7_sel=2 UART0_TXD UART0_TXD uart_sig_7_sel=3 UART0_RXD UART0_RXD uart_sig_7_sel=4 UART1_RTS UART1_RTS uart_sig_7_sel=5 UART1_CTS UART1_CTS uart_sig_7_sel=6 UART1_TXD UART1_TXD uart_sig_7_sel=7 UART1_RXD UART1_RXD uart_sig_7_sel=8 UART2_RTS UART2_RTS uart_sig_7_sel=9 UART2_CTS UART2_CTS uart_sig_7_sel=10 UART2_TXD UART2_TXD uart_sig_7_sel=11 UART2_RXD UART2_RXD 8 - - - 9 - - - 10 - - - 11 - SWGPIO7 SWGPIO7 reg_pwm1_io_sel=0 PWM0_CH3P PWM0_CH3P reg_pwm1_io_sel=1 PWM0_CH3N PWM0_CH3N reg_pwm2_io_sel=0 PWM1_CH3P PWM1_CH3P reg_pwm2_io_sel=1 PWM0_CH2P PWM0_CH2P 18 - MM_SPI_SCLK MM_SPI_SCLK 19 - MM_I2C0_SDA MM_I2C0_SDA 20 - MM_I2C1_SDA MM_I2C1_SDA 21 - MM_UART_CTS MM_UART_CTS 22 - - - 23 - DBI_SDA DBI_SDA 24 - - - 26 - M0_JTAG_TDO M0_JTAG_TDO 27 - D0_JTAG_TDO D0_JTAG_TDO BL808Datasheet 38/93 @2022BouffaloLab

Table3.1: Pin Description BL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function DescriptionBL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function Description 19 19 VDDIO_1 DI/DO PAD_GPIO_8 0 - - - 1 - SPI_SS SPI_SS 2 - - - 3 - I2S_BCLK I2S_BCLK 4 - - - 5 - I2C0_SCL I2C0_SCL 6 - I2C1_SCL I2C1_SCL uart_sig_8_sel=0 UART0_RTS UART0_RTS uart_sig_8_sel=1 UART0_CTS UART0_CTS uart_sig_8_sel=2 UART0_TXD UART0_TXD uart_sig_8_sel=3 UART0_RXD UART0_RXD uart_sig_8_sel=4 UART1_RTS UART1_RTS uart_sig_8_sel=5 UART1_CTS UART1_CTS uart_sig_8_sel=6 UART1_TXD UART1_TXD uart_sig_8_sel=7 UART1_RXD UART1_RXD uart_sig_8_sel=8 UART2_RTS UART2_RTS uart_sig_8_sel=9 UART2_CTS UART2_CTS uart_sig_8_sel=10 UART2_TXD UART2_TXD uart_sig_8_sel=11 UART2_RXD UART2_RXD 8 - - - 9 - - - 10 - - - 11 - SWGPIO8 SWGPIO8 reg_pwm1_io_sel=0 PWM0_CH0P PWM0_CH0P reg_pwm1_io_sel=1 PWM0_CH0P PWM0_CH0P reg_pwm2_io_sel=0 PWM1_CH0P PWM1_CH0P reg_pwm2_io_sel=1 PWM0_BREAK_EXT PWM0_BREAK_EXT 18 - MM_SPI_SS MM_SPI_SS 19 - MM_I2C0_SCL MM_I2C0_SCL 20 - MM_I2C1_SCL MM_I2C1_SCL 21 - MM_UART_TXD MM_UART_TXD 22 - - - 23 - DBI_CSn DBI_CSn 24 - - - 26 - M0_JTAG_TCLK M0_JTAG_TCLK 27 - D0_JTAG_TCK D0_JTAG_TCK 20 20 - Power VDDCORE - - VDDCORE Corepower,1.1V 21 21 - Power VDD33_RF - - VDD33_RF RFtransmitter power supply,3.3V 22 22 - Power VDD33_RF - - VDD33_RF RFtransmitter power supply,3.3V 23 23 AVDD15 Analog ANT - - ANT RFsignal pin 24 24 - Power AVDD15_RF - - AVDD15_RF Integrated LDO output, RF circuit power supply, 1.5V,connectedto decoupling capacitors 25 25 - Power AVDD18_RF - - AVDD18_RF IntegratedLDOinput,1.8V(connectedtothethird pinVDD18_OUT)/3.3V 26 - - Power RSTB_RTC - - RSTB_RTC Real-timeclock circuit reset, active low 28 26 AVDD33 Analog PU_CHIP - - PU_CHIP Chipenable, active high 27 - - Power AVDD33_RTC - - AVDD33_RTC Real-timeclock circuit power supply,3.3V 29 27 - Power VDDIO2(AON) - - VDDIO2(AON) GPIO11~15, GPIO40~41 and AON circuit power input,3.3V BL808Datasheet 39/93 @2022BouffaloLab

Table3.1: Pin Description BL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function DescriptionBL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function Description - 28 AVDD33 DI/DO PAD_GPIO_9 0 - - - 1 - SPI_MOSI SPI_MOSI 2 - - - 3 - I2S_FS I2S_FS 4 - - - 5 - I2C0_SDA I2C0_SDA 6 - I2C1_SDA I2C1_SDA uart_sig_9_sel=0 UART0_RTS UART0_RTS uart_sig_9_sel=1 UART0_CTS UART0_CTS uart_sig_9_sel=2 UART0_TXD UART0_TXD uart_sig_9_sel=3 UART0_RXD UART0_RXD uart_sig_9_sel=4 UART1_RTS UART1_RTS uart_sig_9_sel=5 UART1_CTS UART1_CTS uart_sig_9_sel=6 UART1_TXD UART1_TXD uart_sig_9_sel=7 UART1_RXD UART1_RXD uart_sig_9_sel=8 UART2_RTS UART2_RTS uart_sig_9_sel=9 UART2_CTS UART2_CTS uart_sig_9_sel=10 UART2_TXD UART2_TXD uart_sig_9_sel=11 UART2_RXD UART2_RXD 8 - - - 9 - - - 10 - - - 11 - SWGPIO9 SWGPIO9 reg_pwm1_io_sel=0 PWM0_CH1P PWM0_CH1P reg_pwm1_io_sel=1 PWM0_CH0N PWM0_CH0N reg_pwm2_io_sel=0 PWM1_CH1P PWM1_CH1P reg_pwm2_io_sel=1 PWM0_CH0P PWM0_CH0P 18 - MM_SPI_MOSI MM_SPI_MOSI 19 - MM_I2C0_SDA MM_I2C0_SDA 20 - MM_I2C1_SDA MM_I2C1_SDA 21 - MM_UART_RXD MM_UART_RXD 22 - - - 23 - DBI_DCn DBI_DCn 24 - - - 26 - M0_JTAG_TDI M0_JTAG_TDI 27 - D0_JTAG_TDI D0_JTAG_TDI BL808Datasheet 40/93 @2022BouffaloLab

Table3.1: Pin Description BL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function DescriptionBL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function Description - 29 AVDD33 DI/DO PAD_GPIO_10 0 - - - 1 - SPI_MISO SPI_MISO 2 - - - 3 - I2S_DI/I2S_RCLK_O I2S_DI/I2S_RCLK_O 4 - PDM_CLK_O PDM_CLK_O 5 - I2C0_SCL I2C0_SCL 6 - I2C1_SCL I2C1_SCL uart_sig_10_sel=0 UART0_RTS UART0_RTS uart_sig_10_sel=1 UART0_CTS UART0_CTS uart_sig_10_sel=2 UART0_TXD UART0_TXD uart_sig_10_sel=3 UART0_RXD UART0_RXD uart_sig_10_sel=4 UART1_RTS UART1_RTS uart_sig_10_sel=5 UART1_CTS UART1_CTS uart_sig_10_sel=6 UART1_TXD UART1_TXD uart_sig_10_sel=7 UART1_RXD UART1_RXD uart_sig_10_sel=8 UART2_RTS UART2_RTS uart_sig_10_sel=9 UART2_CTS UART2_CTS uart_sig_10_sel=10 UART2_TXD UART2_TXD uart_sig_10_sel=11 UART2_RXD UART2_RXD 8 - - - 9 - - - 10 - - - 11 - SWGPIO10 SWGPIO10 reg_pwm1_io_sel=0 PWM0_CH2P PWM0_CH2P reg_pwm1_io_sel=1 PWM0_CH1P PWM0_CH1P reg_pwm2_io_sel=0 PWM1_CH2P PWM1_CH2P reg_pwm2_io_sel=1 PWM0_CH1P PWM0_CH1P 18 - MM_SPI_MISO MM_SPI_MISO 19 - MM_I2C0_SCL MM_I2C0_SCL 20 - MM_I2C1_SCL MM_I2C1_SCL 21 - MM_UART_RTS MM_UART_RTS 22 - - - 23 - DBI_SCL DBI_SCL 24 - - - 26 - M0_JTAG_TMS M0_JTAG_TMS 27 - D0_JTAG_TMS D0_JTAG_TMS BL808Datasheet 41/93 @2022BouffaloLab

Table3.1: Pin Description BL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function DescriptionBL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function Description 30 30 AVDD33 Clock XTAL32K_OUT - XTAL32K_OUT XTAL32K_OUT Connectto RTCpassive crystal/active clock VDDIO_2 DI/DO PAD_GPIO_41 0 - - - 1 - SPI_MOSI SPI_MOSI 2 - - - 3 - I2S_FS I2S_FS 4 - - - 5 - I2C0_SDA I2C0_SDA 6 - I2C1_SDA I2C1_SDA uart_sig_5_sel=0 UART0_RTS UART0_RTS uart_sig_5_sel=1 UART0_CTS UART0_CTS uart_sig_5_sel=2 UART0_TXD UART0_TXD uart_sig_5_sel=3 UART0_RXD UART0_RXD uart_sig_5_sel=4 UART1_RTS UART1_RTS uart_sig_5_sel=5 UART1_CTS UART1_CTS uart_sig_5_sel=6 UART1_TXD UART1_TXD uart_sig_5_sel=7 UART1_RXD UART1_RXD uart_sig_5_sel=8 UART2_RTS UART2_RTS uart_sig_5_sel=9 UART2_CTS UART2_CTS uart_sig_5_sel=10 UART2_TXD UART2_TXD uart_sig_5_sel=11 UART2_RXD UART2_RXD 8 - - - 9 - - - 10 - - - 11 - SWGPIO41 SWGPIO41 reg_pwm1_io_sel=0 PWM0_CH1P PWM0_CH1P reg_pwm1_io_sel=1 PWM0_CH0N PWM0_CH0N reg_pwm2_io_sel=0 PWM1_CH1P PWM1_CH1P reg_pwm2_io_sel=1 PWM0_CH0P PWM0_CH0P 18 - MM_SPI_MOSI MM_SPI_MOSI 19 - MM_I2C0_SDA MM_I2C0_SDA 20 - MM_I2C1_SDA MM_I2C1_SDA 21 - MM_UART_RXD MM_UART_RXD 22 - - - 23 - DBI_DCn DBI_DCn 24 - - - 26 - M0_JTAG_TDI M0_JTAG_TDI 27 - D0_JTAG_TDI D0_JTAG_TDI BL808Datasheet 42/93 @2022BouffaloLab

Table3.1: Pin Description BL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function DescriptionBL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function Description 31 31 AVDD33 Clock XTAL32K_IN - XTAL32K_IN XTAL32K_IN Connectto RTCpassive crystal VDDIO_2 DI/DO PAD_GPIO_40 0 - - - 1 - SPI_SS SPI_SS 2 - - - 3 - I2S_BCLK I2S_BCLK 4 - - - 5 - I2C0_SCL I2C0_SCL 6 - I2C1_SCL I2C1_SCL uart_sig_4_sel=0 UART0_RTS UART0_RTS uart_sig_4_sel=1 UART0_CTS UART0_CTS uart_sig_4_sel=2 UART0_TXD UART0_TXD uart_sig_4_sel=3 UART0_RXD UART0_RXD uart_sig_4_sel=4 UART1_RTS UART1_RTS uart_sig_4_sel=5 UART1_CTS UART1_CTS uart_sig_4_sel=6 UART1_TXD UART1_TXD uart_sig_4_sel=7 UART1_RXD UART1_RXD uart_sig_4_sel=8 UART2_RTS UART2_RTS uart_sig_4_sel=9 UART2_CTS UART2_CTS uart_sig_4_sel=10 UART2_TXD UART2_TXD uart_sig_4_sel=11 UART2_RXD UART2_RXD 8 - - - 9 - - - 10 - ADC_CH5 ADC_CH5 11 - SWGPIO40 SWGPIO40 reg_pwm1_io_sel=0 PWM0_CH0P PWM0_CH0P reg_pwm1_io_sel=1 PWM0_CH0P PWM0_CH0P reg_pwm2_io_sel=0 PWM1_CH0P PWM1_CH0P reg_pwm2_io_sel=1 PWM0_BREAK_EXT PWM0_BREAK_EXT 18 - MM_SPI_SS MM_SPI_SS 19 - MM_I2C0_SCL MM_I2C0_SCL 20 - MM_I2C1_SCL MM_I2C1_SCL 21 - MM_UART_TXD MM_UART_TXD 22 - DBI_RDn DBI_RDn 23 - DBI_CSn DBI_CSn 24 - - - 26 - M0_JTAG_TCLK M0_JTAG_TCLK 27 - D0_JTAG_TCK D0_JTAG_TCK BL808Datasheet 43/93 @2022BouffaloLab

Table3.1: Pin Description BL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function DescriptionBL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function Description 32 32 VDDIO_2 DI/DO PAD_GPIO_11 0 - - - 1 - SPI_SCLK SPI_SCLK 2 - - - 3 - I2S_DO/I2S_RCLK_O I2S_DO/I2S_RCLK_O 4 - - - 5 - I2C0_SDA I2C0_SDA 6 - I2C1_SDA I2C1_SDA uart_sig_11_sel=0 UART0_RTS UART0_RTS uart_sig_11_sel=1 UART0_CTS UART0_CTS uart_sig_11_sel=2 UART0_TXD UART0_TXD uart_sig_11_sel=3 UART0_RXD UART0_RXD uart_sig_11_sel=4 UART1_RTS UART1_RTS uart_sig_11_sel=5 UART1_CTS UART1_CTS uart_sig_11_sel=6 UART1_TXD UART1_TXD uart_sig_11_sel=7 UART1_RXD UART1_RXD uart_sig_11_sel=8 UART2_RTS UART2_RTS uart_sig_11_sel=9 UART2_CTS UART2_CTS uart_sig_11_sel=10 UART2_TXD UART2_TXD uart_sig_11_sel=11 UART2_RXD UART2_RXD 8 - - - 9 - - - 10 - ADC_CH3 ADC_CH3 11 - SWGPIO11 SWGPIO11 reg_pwm1_io_sel=0 PWM0_CH3P PWM0_CH3P reg_pwm1_io_sel=1 PWM0_CH1N PWM0_CH1N reg_pwm2_io_sel=0 PWM1_CH3P PWM1_CH3P reg_pwm2_io_sel=1 PWM0_CH2P PWM0_CH2P 18 - MM_SPI_SCLK MM_SPI_SCLK 19 - MM_I2C0_SDA MM_I2C0_SDA 20 - MM_I2C1_SDA MM_I2C1_SDA 21 - MM_UART_CTS MM_UART_CTS 22 - DBI_CSn DBI_CSn 23 - DBI_SDA DBI_SDA 24 - - - 26 - M0_JTAG_TDO M0_JTAG_TDO 27 - D0_JTAG_TDO D0_JTAG_TDO BL808Datasheet 44/93 @2022BouffaloLab

Table3.1: Pin Description BL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function DescriptionBL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function Description 33 33 VDDIO_2 DI/DO PAD_GPIO_12 0 - - - 1 - SPI_SS SPI_SS 2 - - - 3 - I2S_BCLK I2S_BCLK 4 - - - 5 - I2C0_SCL I2C0_SCL 6 - I2C1_SCL I2C1_SCL uart_sig_0_sel=0 UART0_RTS UART0_RTS uart_sig_0_sel=1 UART0_CTS UART0_CTS uart_sig_0_sel=2 UART0_TXD UART0_TXD uart_sig_0_sel=3 UART0_RXD UART0_RXD uart_sig_0_sel=4 UART1_RTS UART1_RTS uart_sig_0_sel=5 UART1_CTS UART1_CTS uart_sig_0_sel=6 UART1_TXD UART1_TXD uart_sig_0_sel=7 UART1_RXD UART1_RXD uart_sig_0_sel=8 UART2_RTS UART2_RTS uart_sig_0_sel=9 UART2_CTS UART2_CTS uart_sig_0_sel=10 UART2_TXD UART2_TXD uart_sig_0_sel=11 UART2_RXD UART2_RXD 8 - - - 9 - - - 10 - ADC_CH6 ADC_CH6 11 - SWGPIO12 SWGPIO12 reg_pwm1_io_sel=0 PWM0_CH0P PWM0_CH0P reg_pwm1_io_sel=1 PWM0_CH2P PWM0_CH2P reg_pwm2_io_sel=0 PWM1_CH0P PWM1_CH0P reg_pwm2_io_sel=1 PWM0_BREAK_EXT PWM0_BREAK_EXT 18 - MM_SPI_SS MM_SPI_SS 19 - MM_I2C0_SCL MM_I2C0_SCL 20 - MM_I2C1_SCL MM_I2C1_SCL 21 - MM_UART_TXD MM_UART_TXD 22 - DBI_DCn DBI_DCn 23 - DBI_CSn DBI_CSn 24 - DPI_VS DPI_VS 26 - M0_JTAG_TCLK M0_JTAG_TCLK 27 - D0_JTAG_TCK D0_JTAG_TCK BL808Datasheet 45/93 @2022BouffaloLab

Table3.1: Pin Description BL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function DescriptionBL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function Description 34 34 VDDIO_2 DI/DO PAD_GPIO_13 0 - - - 1 - SPI_MOSI SPI_MOSI 2 - - - 3 - I2S_FS I2S_FS 4 - - - 5 - I2C0_SDA I2C0_SDA 6 - I2C1_SDA I2C1_SDA uart_sig_1_sel=0 UART0_RTS UART0_RTS uart_sig_1_sel=1 UART0_CTS UART0_CTS uart_sig_1_sel=2 UART0_TXD UART0_TXD uart_sig_1_sel=3 UART0_RXD UART0_RXD uart_sig_1_sel=4 UART1_RTS UART1_RTS uart_sig_1_sel=5 UART1_CTS UART1_CTS uart_sig_1_sel=6 UART1_TXD UART1_TXD uart_sig_1_sel=7 UART1_RXD UART1_RXD uart_sig_1_sel=8 UART2_RTS UART2_RTS uart_sig_1_sel=9 UART2_CTS UART2_CTS uart_sig_1_sel=10 UART2_TXD UART2_TXD uart_sig_1_sel=11 UART2_RXD UART2_RXD 8 - - - 9 - - - 10 - ADC_CH7 ADC_CH7 11 - SWGPIO13 SWGPIO13 reg_pwm1_io_sel=0 PWM0_CH1P PWM0_CH1P reg_pwm1_io_sel=1 PWM0_CH2N PWM0_CH2N reg_pwm2_io_sel=0 PWM1_CH1P PWM1_CH1P reg_pwm2_io_sel=1 PWM0_CH0P PWM0_CH0P 18 - MM_SPI_MOSI MM_SPI_MOSI 19 - MM_I2C0_SDA MM_I2C0_SDA 20 - MM_I2C1_SDA MM_I2C1_SDA 21 - MM_UART_RXD MM_UART_RXD 22 - DBI_WRn DBI_WRn 23 - DBI_DCn DBI_DCn 24 - DPI_HS DPI_HS 26 - M0_JTAG_TDI M0_JTAG_TDI 27 - D0_JTAG_TDI D0_JTAG_TDI BL808Datasheet 46/93 @2022BouffaloLab

Table3.1: Pin Description BL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function DescriptionBL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function Description 35 35 VDDIO_2 DI/DO PAD_GPIO_14 0 - - - 1 - SPI_MISO SPI_MISO 2 - - - 3 - I2S_DI/I2S_RCLK_O I2S_DI/I2S_RCLK_O 4 - - - 5 - I2C0_SCL I2C0_SCL 6 - I2C1_SCL I2C1_SCL uart_sig_2_sel=0 UART0_RTS UART0_RTS uart_sig_2_sel=1 UART0_CTS UART0_CTS uart_sig_2_sel=2 UART0_TXD UART0_TXD uart_sig_2_sel=3 UART0_RXD UART0_RXD uart_sig_2_sel=4 UART1_RTS UART1_RTS uart_sig_2_sel=5 UART1_CTS UART1_CTS uart_sig_2_sel=6 UART1_TXD UART1_TXD uart_sig_2_sel=7 UART1_RXD UART1_RXD uart_sig_2_sel=8 UART2_RTS UART2_RTS uart_sig_2_sel=9 UART2_CTS UART2_CTS uart_sig_2_sel=10 UART2_TXD UART2_TXD uart_sig_2_sel=11 UART2_RXD UART2_RXD 8 - - - 9 - - - 10 - - - 11 - SWGPIO14 SWGPIO14 reg_pwm1_io_sel=0 PWM0_CH2P PWM0_CH2P reg_pwm1_io_sel=1 PWM0_CH3P PWM0_CH3P reg_pwm2_io_sel=0 PWM1_CH2P PWM1_CH2P reg_pwm2_io_sel=1 PWM0_CH1P PWM0_CH1P 18 - MM_SPI_MISO MM_SPI_MISO 19 - MM_I2C0_SCL MM_I2C0_SCL 20 - MM_I2C1_SCL MM_I2C1_SCL 21 - MM_UART_RTS MM_UART_RTS 22 - - - 23 - DBI_SCL DBI_SCL 24 - - - 26 - M0_JTAG_TMS M0_JTAG_TMS 27 - D0_JTAG_TMS D0_JTAG_TMS BL808Datasheet 47/93 @2022BouffaloLab

Table3.1: Pin Description BL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function DescriptionBL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function Description 36 36 VDDIO_2 DI/DO PAD_GPIO_15 0 - - - 1 - SPI_SCLK SPI_SCLK 2 - - - 3 - I2S_DO/I2S_RCLK_O I2S_DO/I2S_RCLK_O 4 - - - 5 - I2C0_SDA I2C0_SDA 6 - I2C1_SDA I2C1_SDA uart_sig_3_sel=0 UART0_RTS UART0_RTS uart_sig_3_sel=1 UART0_CTS UART0_CTS uart_sig_3_sel=2 UART0_TXD UART0_TXD uart_sig_3_sel=3 UART0_RXD UART0_RXD uart_sig_3_sel=4 UART1_RTS UART1_RTS uart_sig_3_sel=5 UART1_CTS UART1_CTS uart_sig_3_sel=6 UART1_TXD UART1_TXD uart_sig_3_sel=7 UART1_RXD UART1_RXD uart_sig_3_sel=8 UART2_RTS UART2_RTS uart_sig_3_sel=9 UART2_CTS UART2_CTS uart_sig_3_sel=10 UART2_TXD UART2_TXD uart_sig_3_sel=11 UART2_RXD UART2_RXD 8 - - - 9 - - - 10 - - - 11 - SWGPIO15 SWGPIO15 reg_pwm1_io_sel=0 PWM0_CH3P PWM0_CH3P reg_pwm1_io_sel=1 PWM0_CH3N PWM0_CH3N reg_pwm2_io_sel=0 PWM1_CH3P PWM1_CH3P reg_pwm2_io_sel=1 PWM0_CH2P PWM0_CH2P 18 - MM_SPI_SCLK MM_SPI_SCLK 19 - MM_I2C0_SDA MM_I2C0_SDA 20 - MM_I2C1_SDA MM_I2C1_SDA 21 - MM_UART_CTS MM_UART_CTS 22 - - - 23 - DBI_SDA DBI_SDA 24 - - - 26 - M0_JTAG_TDO M0_JTAG_TDO 27 - D0_JTAG_TDO D0_JTAG_TDO 37 37 - Power VDDCORE - - VDDCORE CorePower,1.1V 38 38 AVDD33 Clock XTAL_OUT - - XTAL_OUT Connecthigh frequency passive crystal 39 39 AVDD33 Clock XTAL_IN - - XTAL_IN Connect high frequency passive crystal/active clock 40 40 - Power AVDD33_CODEC - - AVDD33_CODEC IntegratedLDO input, 3.3V 41 41 - Power AVDD25_CODEC - - AVDD25_CODEC Integrated LDO output, audio codec circuit power supply,2.5V,connectedto decoupling capacitors 42 42 - Power VSS_CODEC - - VSS_CODEC Audiocodec circuit ground pin 43 43 - Power VREF - - VREF Audio codec circuit reference voltage, connected todecoupling capacitors 44 44 - Power MICBIAS - - MICBIAS MicrophoneBias/Power 45 45 AVDD33/25 Analog MIC_1P - - MIC_1P Microphone1 differentialinput+ 46 46 AVDD33/25 Analog MIC_1N - - MIC_1N Microphone1 differentialinput- 47 - AVDD33/25 Analog MIC2P(PADC_AIP1) - - MIC2P(PADC_AIP1) Microphone2 differentialinput+ 48 - AVDD33/25 Analog MIC2N(PADC_AIN1) - - MIC2N(PADC_AIN1) Microphone2 differentialinput- 49 47 AVDD33/25 Analog LINEOUT_1P - - LINEOUT_1P Line1 single-ended output BL808Datasheet 48/93 @2022BouffaloLab

Table3.1: Pin Description BL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function DescriptionBL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function Description - 48 VDDIO_3 DI/DO PAD_GPIO_42 0 - - - 1 - SPI_MISO SPI_MISO 2 - - - 3 - I2S_DI/I2S_RCLK_O I2S_DI/I2S_RCLK_O 4 - - - 5 - I2C0_SCL I2C0_SCL 6 - I2C1_SCL I2C1_SCL uart_sig_6_sel=0 UART0_RTS UART0_RTS uart_sig_6_sel=1 UART0_CTS UART0_CTS uart_sig_6_sel=2 UART0_TXD UART0_TXD uart_sig_6_sel=3 UART0_RXD UART0_RXD uart_sig_6_sel=4 UART1_RTS UART1_RTS uart_sig_6_sel=5 UART1_CTS UART1_CTS uart_sig_6_sel=6 UART1_TXD UART1_TXD uart_sig_6_sel=7 UART1_RXD UART1_RXD uart_sig_6_sel=8 UART2_RTS UART2_RTS uart_sig_6_sel=9 UART2_CTS UART2_CTS uart_sig_6_sel=10 UART2_TXD UART2_TXD uart_sig_6_sel=11 UART2_RXD UART2_RXD 8 - - - 9 - - - 10 - - - 11 - SWGPIO42 SWGPIO42 reg_pwm1_io_sel=0 PWM0_CH2P PWM0_CH2P reg_pwm1_io_sel=1 PWM0_CH1P PWM0_CH1P reg_pwm2_io_sel=0 PWM1_CH2P PWM1_CH2P reg_pwm2_io_sel=1 PWM0_CH1P PWM0_CH1P 18 - MM_SPI_MISO MM_SPI_MISO 19 - MM_I2C0_SCL MM_I2C0_SCL 20 - MM_I2C1_SCL MM_I2C1_SCL 21 - MM_UART_RTS MM_UART_RTS 22 - - - 23 - DBI_SCL DBI_SCL 24 - - - 26 - M0_JTAG_TMS M0_JTAG_TMS 27 - D0_JTAG_TMS D0_JTAG_TMS BL808Datasheet 49/93 @2022BouffaloLab

Table3.1: Pin Description BL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function DescriptionBL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function Description - 49 VDDIO_3 DI/DO PAD_GPIO_43 0 - - - 1 - SPI_SCLK SPI_SCLK 2 - - - 3 - I2S_DO/I2S_RCLK_O I2S_DO/I2S_RCLK_O 4 - - - 5 - I2C0_SDA I2C0_SDA 6 - I2C1_SDA I2C1_SDA uart_sig_7_sel=0 UART0_RTS UART0_RTS uart_sig_7_sel=1 UART0_CTS UART0_CTS uart_sig_7_sel=2 UART0_TXD UART0_TXD uart_sig_7_sel=3 UART0_RXD UART0_RXD uart_sig_7_sel=4 UART1_RTS UART1_RTS uart_sig_7_sel=5 UART1_CTS UART1_CTS uart_sig_7_sel=6 UART1_TXD UART1_TXD uart_sig_7_sel=7 UART1_RXD UART1_RXD uart_sig_7_sel=8 UART2_RTS UART2_RTS uart_sig_7_sel=9 UART2_CTS UART2_CTS uart_sig_7_sel=10 UART2_TXD UART2_TXD uart_sig_7_sel=11 UART2_RXD UART2_RXD 8 - - - 9 - - - 10 - - - 11 - SWGPIO43 SWGPIO43 reg_pwm1_io_sel=0 PWM0_CH3P PWM0_CH3P reg_pwm1_io_sel=1 PWM0_CH1N PWM0_CH1N reg_pwm2_io_sel=0 PWM1_CH3P PWM1_CH3P reg_pwm2_io_sel=1 PWM0_CH2P PWM0_CH2P 18 - MM_SPI_SCLK MM_SPI_SCLK 19 - MM_I2C0_SDA MM_I2C0_SDA 20 - MM_I2C1_SDA MM_I2C1_SDA 21 - MM_UART_CTS MM_UART_CTS 22 - - - 23 - DBI_SDA DBI_SDA 24 - - - 26 - M0_JTAG_TDO M0_JTAG_TDO 27 - D0_JTAG_TDO D0_JTAG_TDO BL808Datasheet 50/93 @2022BouffaloLab

Table3.1: Pin Description BL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function DescriptionBL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function Description 50 50 VDDIO_3 DI/DO PAD_GPIO_16 0 - - - 1 - SPI_SS SPI_SS 2 - - - 3 - I2S_BCLK I2S_BCLK 4 - PDM_1_IN PDM_1_IN 5 - I2C0_SCL I2C0_SCL 6 - I2C1_SCL I2C1_SCL uart_sig_4_sel=0 UART0_RTS UART0_RTS uart_sig_4_sel=1 UART0_CTS UART0_CTS uart_sig_4_sel=2 UART0_TXD UART0_TXD uart_sig_4_sel=3 UART0_RXD UART0_RXD uart_sig_4_sel=4 UART1_RTS UART1_RTS uart_sig_4_sel=5 UART1_CTS UART1_CTS uart_sig_4_sel=6 UART1_TXD UART1_TXD uart_sig_4_sel=7 UART1_RXD UART1_RXD uart_sig_4_sel=8 UART2_RTS UART2_RTS uart_sig_4_sel=9 UART2_CTS UART2_CTS uart_sig_4_sel=10 UART2_TXD UART2_TXD uart_sig_4_sel=11 UART2_RXD UART2_RXD 8 - - - 9 - CAM_HSYNC CAM_HSYNC 10 - ADC_CH8 ADC_CH8 11 - SWGPIO16 SWGPIO16 reg_pwm1_io_sel=0 PWM0_CH0P PWM0_CH0P reg_pwm1_io_sel=1 PWM0_CH0P PWM0_CH0P reg_pwm2_io_sel=0 PWM1_CH0P PWM1_CH0P reg_pwm2_io_sel=1 PWM0_BREAK_EXT PWM0_BREAK_EXT 18 - MM_SPI_SS MM_SPI_SS 19 - MM_I2C0_SCL MM_I2C0_SCL 20 - MM_I2C1_SCL MM_I2C1_SCL 21 - MM_UART_TXD MM_UART_TXD 22 - DBI_DB_0 DBI_DB_0 23 - DBI_CSn DBI_CSn 24 - DPI_PCLK DPI_PCLK 26 - M0_JTAG_TCLK M0_JTAG_TCLK 27 - D0_JTAG_TCK D0_JTAG_TCK BL808Datasheet 51/93 @2022BouffaloLab

Table3.1: Pin Description BL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function DescriptionBL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function Description 51 51 VDDIO_3 DI/DO PAD_GPIO_17 0 - - - 1 - SPI_MOSI SPI_MOSI 2 - - - 3 - I2S_FS I2S_FS 4 - PDM_CLK_O PDM_CLK_O 5 - I2C0_SDA I2C0_SDA 6 - I2C1_SDA I2C1_SDA uart_sig_5_sel=0 UART0_RTS UART0_RTS uart_sig_5_sel=1 UART0_CTS UART0_CTS uart_sig_5_sel=2 UART0_TXD UART0_TXD uart_sig_5_sel=3 UART0_RXD UART0_RXD uart_sig_5_sel=4 UART1_RTS UART1_RTS uart_sig_5_sel=5 UART1_CTS UART1_CTS uart_sig_5_sel=6 UART1_TXD UART1_TXD uart_sig_5_sel=7 UART1_RXD UART1_RXD uart_sig_5_sel=8 UART2_RTS UART2_RTS uart_sig_5_sel=9 UART2_CTS UART2_CTS uart_sig_5_sel=10 UART2_TXD UART2_TXD uart_sig_5_sel=11 UART2_RXD UART2_RXD 8 - - - 9 - CAM_VSYNC CAM_VSYNC 10 - ADC_CH0 ADC_CH0 11 - SWGPIO17 SWGPIO17 reg_pwm1_io_sel=0 PWM0_CH1P PWM0_CH1P reg_pwm1_io_sel=1 PWM0_CH0N PWM0_CH0N reg_pwm2_io_sel=0 PWM1_CH1P PWM1_CH1P reg_pwm2_io_sel=1 PWM0_CH0P PWM0_CH0P 18 - MM_SPI_MOSI MM_SPI_MOSI 19 - MM_I2C0_SDA MM_I2C0_SDA 20 - MM_I2C1_SDA MM_I2C1_SDA 21 - MM_UART_RXD MM_UART_RXD 22 - DBI_DB_1 DBI_DB_1 23 - DBI_DCn DBI_DCn 24 - DPI_DATA[0] DPI_DATA[0] 26 - M0_JTAG_TDI M0_JTAG_TDI 27 - D0_JTAG_TDI D0_JTAG_TDI BL808Datasheet 52/93 @2022BouffaloLab

Table3.1: Pin Description BL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function DescriptionBL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function Description 52 52 VDDIO_3 DI/DO PAD_GPIO_18 0 - - - 1 - SPI_MISO SPI_MISO 2 - - - 3 - I2S_DI/I2S_RCLK_O I2S_DI/I2S_RCLK_O 4 - PDM_0_IN PDM_0_IN 5 - I2C0_SCL I2C0_SCL 6 - I2C1_SCL I2C1_SCL uart_sig_6_sel=0 UART0_RTS UART0_RTS uart_sig_6_sel=1 UART0_CTS UART0_CTS uart_sig_6_sel=2 UART0_TXD UART0_TXD uart_sig_6_sel=3 UART0_RXD UART0_RXD uart_sig_6_sel=4 UART1_RTS UART1_RTS uart_sig_6_sel=5 UART1_CTS UART1_CTS uart_sig_6_sel=6 UART1_TXD UART1_TXD uart_sig_6_sel=7 UART1_RXD UART1_RXD uart_sig_6_sel=8 UART2_RTS UART2_RTS uart_sig_6_sel=9 UART2_CTS UART2_CTS uart_sig_6_sel=10 UART2_TXD UART2_TXD uart_sig_6_sel=11 UART2_RXD UART2_RXD 8 - - - 9 - PIX_DAT8 PIX_DAT8 10 - ADC_CH9 ADC_CH9 11 - SWGPIO18 SWGPIO18 reg_pwm1_io_sel=0 PWM0_CH2P PWM0_CH2P reg_pwm1_io_sel=1 PWM0_CH1P PWM0_CH1P reg_pwm2_io_sel=0 PWM1_CH2P PWM1_CH2P reg_pwm2_io_sel=1 PWM0_CH1P PWM0_CH1P 18 - MM_SPI_MISO MM_SPI_MISO 19 - MM_I2C0_SCL MM_I2C0_SCL 20 - MM_I2C1_SCL MM_I2C1_SCL 21 - MM_UART_RTS MM_UART_RTS 22 - DBI_DB_2 DBI_DB_2 23 - DBI_SCL DBI_SCL 24 - DPI_DATA[1] DPI_DATA[1] 26 - M0_JTAG_TMS M0_JTAG_TMS 27 - D0_JTAG_TMS D0_JTAG_TMS BL808Datasheet 53/93 @2022BouffaloLab

Table3.1: Pin Description BL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function DescriptionBL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function Description 53 53 VDDIO_3 DI/DO PAD_GPIO_19 0 - - - 1 - SPI_SCLK SPI_SCLK 2 - - - 3 - I2S_DO/I2S_RCLK_O I2S_DO/I2S_RCLK_O 4 - PDM_1_IN PDM_1_IN 5 - I2C0_SDA I2C0_SDA 6 - I2C1_SDA I2C1_SDA uart_sig_7_sel=0 UART0_RTS UART0_RTS uart_sig_7_sel=1 UART0_CTS UART0_CTS uart_sig_7_sel=2 UART0_TXD UART0_TXD uart_sig_7_sel=3 UART0_RXD UART0_RXD uart_sig_7_sel=4 UART1_RTS UART1_RTS uart_sig_7_sel=5 UART1_CTS UART1_CTS uart_sig_7_sel=6 UART1_TXD UART1_TXD uart_sig_7_sel=7 UART1_RXD UART1_RXD uart_sig_7_sel=8 UART2_RTS UART2_RTS uart_sig_7_sel=9 UART2_CTS UART2_CTS uart_sig_7_sel=10 UART2_TXD UART2_TXD uart_sig_7_sel=11 UART2_RXD UART2_RXD 8 - - - 9 - PIX_DAT9 PIX_DAT9 10 - ADC_CH10 ADC_CH10 11 - SWGPIO19 SWGPIO19 reg_pwm1_io_sel=0 PWM0_CH3P PWM0_CH3P reg_pwm1_io_sel=1 PWM0_CH1N PWM0_CH1N reg_pwm2_io_sel=0 PWM1_CH3P PWM1_CH3P reg_pwm2_io_sel=1 PWM0_CH2P PWM0_CH2P 18 - MM_SPI_SCLK MM_SPI_SCLK 19 - MM_I2C0_SDA MM_I2C0_SDA 20 - MM_I2C1_SDA MM_I2C1_SDA 21 - MM_UART_CTS MM_UART_CTS 22 - DBI_DB_3 DBI_DB_3 23 - DBI_SDA DBI_SDA 24 - DPI_DATA[2] DPI_DATA[2] 26 - M0_JTAG_TDO M0_JTAG_TDO 27 - D0_JTAG_TDO D0_JTAG_TDO BL808Datasheet 54/93 @2022BouffaloLab

Table3.1: Pin Description BL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function DescriptionBL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function Description 54 54 VDDIO_3 DI/DO PAD_GPIO_20 0 - - - 1 - SPI_SS SPI_SS 2 - - - 3 - I2S_BCLK I2S_BCLK 4 - PDM_CLK_O PDM_CLK_O 5 - I2C0_SCL I2C0_SCL 6 - I2C1_SCL I2C1_SCL uart_sig_8_sel=0 UART0_RTS UART0_RTS uart_sig_8_sel=1 UART0_CTS UART0_CTS uart_sig_8_sel=2 UART0_TXD UART0_TXD uart_sig_8_sel=3 UART0_RXD UART0_RXD uart_sig_8_sel=4 UART1_RTS UART1_RTS uart_sig_8_sel=5 UART1_CTS UART1_CTS uart_sig_8_sel=6 UART1_TXD UART1_TXD uart_sig_8_sel=7 UART1_RXD UART1_RXD uart_sig_8_sel=8 UART2_RTS UART2_RTS uart_sig_8_sel=9 UART2_CTS UART2_CTS uart_sig_8_sel=10 UART2_TXD UART2_TXD uart_sig_8_sel=11 UART2_RXD UART2_RXD 8 - - - 9 - PIX_DAT10 PIX_DAT10 10 - - - 11 - SWGPIO20 SWGPIO20 reg_pwm1_io_sel=0 PWM0_CH0P PWM0_CH0P reg_pwm1_io_sel=1 PWM0_CH2P PWM0_CH2P reg_pwm2_io_sel=0 PWM1_CH0P PWM1_CH0P reg_pwm2_io_sel=1 PWM0_BREAK_EXT PWM0_BREAK_EXT 18 - MM_SPI_SS MM_SPI_SS 19 - MM_I2C0_SCL MM_I2C0_SCL 20 - MM_I2C1_SCL MM_I2C1_SCL 21 - MM_UART_TXD MM_UART_TXD 22 - DBI_DB_4 DBI_DB_4 23 - DBI_CSn DBI_CSn 24 - DPI_DATA[3] DPI_DATA[3] 26 - M0_JTAG_TCLK M0_JTAG_TCLK 27 - D0_JTAG_TCK D0_JTAG_TCK BL808Datasheet 55/93 @2022BouffaloLab

Table3.1: Pin Description BL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function DescriptionBL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function Description 55 55 VDDIO_3 DI/DO PAD_GPIO_21 0 - - - 1 - SPI_MOSI SPI_MOSI 2 - - - 3 - I2S_FS I2S_FS 4 - PDM_0_IN PDM_0_IN 5 - I2C0_SDA I2C0_SDA 6 - I2C1_SDA I2C1_SDA uart_sig_9_sel=0 UART0_RTS UART0_RTS uart_sig_9_sel=1 UART0_CTS UART0_CTS uart_sig_9_sel=2 UART0_TXD UART0_TXD uart_sig_9_sel=3 UART0_RXD UART0_RXD uart_sig_9_sel=4 UART1_RTS UART1_RTS uart_sig_9_sel=5 UART1_CTS UART1_CTS uart_sig_9_sel=6 UART1_TXD UART1_TXD uart_sig_9_sel=7 UART1_RXD UART1_RXD uart_sig_9_sel=8 UART2_RTS UART2_RTS uart_sig_9_sel=9 UART2_CTS UART2_CTS uart_sig_9_sel=10 UART2_TXD UART2_TXD uart_sig_9_sel=11 UART2_RXD UART2_RXD 8 - - - 9 - PIX_DAT11 PIX_DAT11 10 - - - 11 - SWGPIO21 SWGPIO21 reg_pwm1_io_sel=0 PWM0_CH1P PWM0_CH1P reg_pwm1_io_sel=1 PWM0_CH2N PWM0_CH2N reg_pwm2_io_sel=0 PWM1_CH1P PWM1_CH1P reg_pwm2_io_sel=1 PWM0_CH0P PWM0_CH0P 18 - MM_SPI_MOSI MM_SPI_MOSI 19 - MM_I2C0_SDA MM_I2C0_SDA 20 - MM_I2C1_SDA MM_I2C1_SDA 21 - MM_UART_RXD MM_UART_RXD 22 - DBI_DB_5 DBI_DB_5 23 - DBI_DCn DBI_DCn 24 - DPI_DATA[4] DPI_DATA[4] 26 - M0_JTAG_TDI M0_JTAG_TDI 27 - D0_JTAG_TDI D0_JTAG_TDI BL808Datasheet 56/93 @2022BouffaloLab

Table3.1: Pin Description BL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function DescriptionBL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function Description 56 56 VDDIO_3 DI/DO PAD_GPIO_22 0 - - - 1 - SPI_MISO SPI_MISO 2 - - - 3 - I2S_DI/I2S_RCLK_O I2S_DI/I2S_RCLK_O 4 - - - 5 - I2C0_SCL I2C0_SCL 6 - I2C1_SCL I2C1_SCL uart_sig_10_sel=0 UART0_RTS UART0_RTS uart_sig_10_sel=1 UART0_CTS UART0_CTS uart_sig_10_sel=2 UART0_TXD UART0_TXD uart_sig_10_sel=3 UART0_RXD UART0_RXD uart_sig_10_sel=4 UART1_RTS UART1_RTS uart_sig_10_sel=5 UART1_CTS UART1_CTS uart_sig_10_sel=6 UART1_TXD UART1_TXD uart_sig_10_sel=7 UART1_RXD UART1_RXD uart_sig_10_sel=8 UART2_RTS UART2_RTS uart_sig_10_sel=9 UART2_CTS UART2_CTS uart_sig_10_sel=10 UART2_TXD UART2_TXD uart_sig_10_sel=11 UART2_RXD UART2_RXD 8 - - - 9 - CAM_HSYNC CAM_HSYNC 10 - - - 11 - SWGPIO22 SWGPIO22 reg_pwm1_io_sel=0 PWM0_CH2P PWM0_CH2P reg_pwm1_io_sel=1 PWM0_CH3P PWM0_CH3P reg_pwm2_io_sel=0 PWM1_CH2P PWM1_CH2P reg_pwm2_io_sel=1 PWM0_CH1P PWM0_CH1P 18 - MM_SPI_MISO MM_SPI_MISO 19 - MM_I2C0_SCL MM_I2C0_SCL 20 - MM_I2C1_SCL MM_I2C1_SCL 21 - MM_UART_RTS MM_UART_RTS 22 - DBI_DB_6 DBI_DB_6 23 - DBI_SCL DBI_SCL 24 - DPI_DATA[5] DPI_DATA[5] 26 - M0_JTAG_TMS M0_JTAG_TMS 27 - D0_JTAG_TMS D0_JTAG_TMS BL808Datasheet 57/93 @2022BouffaloLab

Table3.1: Pin Description BL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function DescriptionBL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function Description 57 57 VDDIO_3 DI/DO PAD_GPIO_23 0 - - - 1 - SPI_SCLK SPI_SCLK 2 - - - 3 - I2S_DO/I2S_RCLK_O I2S_DO/I2S_RCLK_O 4 - - - 5 - I2C0_SDA I2C0_SDA 6 - I2C1_SDA I2C1_SDA uart_sig_11_sel=0 UART0_RTS UART0_RTS uart_sig_11_sel=1 UART0_CTS UART0_CTS uart_sig_11_sel=2 UART0_TXD UART0_TXD uart_sig_11_sel=3 UART0_RXD UART0_RXD uart_sig_11_sel=4 UART1_RTS UART1_RTS uart_sig_11_sel=5 UART1_CTS UART1_CTS uart_sig_11_sel=6 UART1_TXD UART1_TXD uart_sig_11_sel=7 UART1_RXD UART1_RXD uart_sig_11_sel=8 UART2_RTS UART2_RTS uart_sig_11_sel=9 UART2_CTS UART2_CTS uart_sig_11_sel=10 UART2_TXD UART2_TXD uart_sig_11_sel=11 UART2_RXD UART2_RXD 8 - - - 9 - CAM_VSYNC CAM_VSYNC 10 - - - 11 - SWGPIO23 SWGPIO23 reg_pwm1_io_sel=0 PWM0_CH3P PWM0_CH3P reg_pwm1_io_sel=1 PWM0_CH3N PWM0_CH3N reg_pwm2_io_sel=0 PWM1_CH3P PWM1_CH3P reg_pwm2_io_sel=1 PWM0_CH2P PWM0_CH2P 18 - MM_SPI_SCLK MM_SPI_SCLK 19 - MM_I2C0_SDA MM_I2C0_SDA 20 - MM_I2C1_SDA MM_I2C1_SDA 21 - MM_UART_CTS MM_UART_CTS 22 - DBI_DB_7 DBI_DB_7 23 - DBI_SDA DBI_SDA 24 - DPI_DATA[6] DPI_DATA[6] 26 - M0_JTAG_TDO M0_JTAG_TDO 27 - D0_JTAG_TDO D0_JTAG_TDO 58 58 - Power VDDIO3 - - VDDIO3 GPIO16~23andintegratedLDOpowerinput,1.8V (connectedto the third pin VDD18_OUT)/3.3V 59 59 - Power AVDD12 - - AVDD12 Integrated LDO output, on-chip pSRAM power supply,1.2V,connectedto decoupling capacitors 60 60 - Power AVDD12 - - AVDD12 Integrated LDO output, on-chip pSRAM power supply,1.2V,connectedto decoupling capacitors 61 61 AVDD12_INT (1.2V) Analog CSI_DN<1> - - CSI_DN<1> MIPICSI data LANE1 differentialinput- 62 62 AVDD12_INT (1.2V) Analog CSI_DP<1> - - CSI_DP<1> MIPICSI data LANE1 differentialinput+ 63 63 AVDD12_INT (1.2V) Analog CSI_CLK_DN - - CSI_CLK_DN MIPICSI clock LANE differentialinput- 64 64 AVDD12_INT (1.2V) Analog CSI_CLK_DP - - CSI_CLK_DP MIPICSI clock LANE differentialinput+ 65 65 AVDD12_INT (1.2V) Analog CSI_DN<0> - - CSI_DN<0> MIPICSI data LANE0 differentialinput- 66 66 AVDD12_INT (1.2V) Analog CSI_DP<0> - - CSI_DP<0> MIPICSI data LANE0 differentialinput+ - 67 AVDD12_INT (1.2V) Analog DSI_DN<0> - - DSI_DN<0> MIPIDSI data LANE0 differentialoutput- BL808Datasheet 58/93 @2022BouffaloLab

Table3.1: Pin Description BL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function DescriptionBL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function Description - 68 AVDD12_INT (1.2V) Analog DSI_DP<0> - - DSI_DP<0> MIPIDSI data LANE0 differentialoutput+ - 69 AVDD12_INT (1.2V) Analog DSI_DN<1> - - DSI_DN<1> MIPIDSI data LANE1 differentialoutput- - 70 AVDD12_INT (1.2V) Analog DSI_DP<1> - - DSI_DP<1> MIPIDSI data LANE1 differentialoutput+ - 71 AVDD12_INT (1.2V) Analog DSI_CLK_DN - - DSI_CLK_DN MIPIDSI clock LANE differentialoutput- - 72 AVDD12_INT (1.2V) Analog DSI_CLK_DP - - DSI_CLK_DP MIPIDSI clock LANE differentialoutput+ - 73 AVDD12_INT (1.2V) Analog DSI_DN<2> - - DSI_DN<2> MIPIDSI data LANE2 differentialoutput- - 74 AVDD12_INT (1.2V) Analog DSI_DP<2> - - DSI_DP<2> MIPIDSI data LANE2 differentialoutput+ - 75 AVDD12_INT (1.2V) Analog DSI_DN<3> - - DSI_DN<3> MIPIDSI data LANE3 differentialoutput- - 76 AVDD12_INT (1.2V) Analog DSI_DP<3> - - DSI_DP<3> MIPIDSI data LANE2 differentialoutput+ 67 - VDDIO_4 DI/DO PAD_GPIO_24 0 - - - 1 - SPI_SS SPI_SS 2 - - - 3 - I2S_BCLK I2S_BCLK 4 - - - 5 - I2C0_SCL I2C0_SCL 6 - I2C1_SCL I2C1_SCL uart_sig_0_sel=0 UART0_RTS UART0_RTS uart_sig_0_sel=1 UART0_CTS UART0_CTS uart_sig_0_sel=2 UART0_TXD UART0_TXD uart_sig_0_sel=3 UART0_RXD UART0_RXD uart_sig_0_sel=4 UART1_RTS UART1_RTS uart_sig_0_sel=5 UART1_CTS UART1_CTS uart_sig_0_sel=6 UART1_TXD UART1_TXD uart_sig_0_sel=7 UART1_RXD UART1_RXD uart_sig_0_sel=8 UART2_RTS UART2_RTS uart_sig_0_sel=9 UART2_CTS UART2_CTS uart_sig_0_sel=10 UART2_TXD UART2_TXD uart_sig_0_sel=11 UART2_RXD UART2_RXD 8 - RMII_REF_CLK RMII_REF_CLK 9 - DVP_CLK DVP_CLK 10 - - - 11 - SWGPIO24 SWGPIO24 reg_pwm1_io_sel=0 PWM0_CH0P PWM0_CH0P reg_pwm1_io_sel=1 PWM0_CH0P PWM0_CH0P reg_pwm2_io_sel=0 PWM1_CH0P PWM1_CH0P reg_pwm2_io_sel=1 PWM0_BREAK_EXT PWM0_BREAK_EXT 18 - MM_SPI_SS MM_SPI_SS 19 - MM_I2C0_SCL MM_I2C0_SCL 20 - MM_I2C1_SCL MM_I2C1_SCL 21 - MM_UART_TXD MM_UART_TXD 22 - - - 23 - DBI_CSn DBI_CSn 24 - DPI_DATA[7] DPI_DATA[7] 26 - M0_JTAG_TCLK M0_JTAG_TCLK 27 - D0_JTAG_TCK D0_JTAG_TCK BL808Datasheet 59/93 @2022BouffaloLab

Table3.1: Pin Description BL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function DescriptionBL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function Description 68 - VDDIO_4 DI/DO PAD_GPIO_25 0 - - - 1 - SPI_MOSI SPI_MOSI 2 - - - 3 - I2S_FS I2S_FS 4 - PDM_1_IN PDM_1_IN 5 - I2C0_SDA I2C0_SDA 6 - I2C1_SDA I2C1_SDA uart_sig_1_sel=0 UART0_RTS UART0_RTS uart_sig_1_sel=1 UART0_CTS UART0_CTS uart_sig_1_sel=2 UART0_TXD UART0_TXD uart_sig_1_sel=3 UART0_RXD UART0_RXD uart_sig_1_sel=4 UART1_RTS UART1_RTS uart_sig_1_sel=5 UART1_CTS UART1_CTS uart_sig_1_sel=6 UART1_TXD UART1_TXD uart_sig_1_sel=7 UART1_RXD UART1_RXD uart_sig_1_sel=8 UART2_RTS UART2_RTS uart_sig_1_sel=9 UART2_CTS UART2_CTS uart_sig_1_sel=10 UART2_TXD UART2_TXD uart_sig_1_sel=11 UART2_RXD UART2_RXD 8 - RMII_TXD[0] RMII_TXD[0] 9 - PIX_DAT0 PIX_DAT0 10 - - - 11 - SWGPIO25 SWGPIO25 reg_pwm1_io_sel=0 PWM0_CH1P PWM0_CH1P reg_pwm1_io_sel=1 PWM0_CH0N PWM0_CH0N reg_pwm2_io_sel=0 PWM1_CH1P PWM1_CH1P reg_pwm2_io_sel=1 PWM0_CH0P PWM0_CH0P 18 - MM_SPI_MOSI MM_SPI_MOSI 19 - MM_I2C0_SDA MM_I2C0_SDA 20 - MM_I2C1_SDA MM_I2C1_SDA 21 - MM_UART_RXD MM_UART_RXD 22 - - - 23 - DBI_DCn DBI_DCn 24 - DPI_DATA[8] DPI_DATA[8] 26 - M0_JTAG_TDI M0_JTAG_TDI 27 - D0_JTAG_TDI D0_JTAG_TDI BL808Datasheet 60/93 @2022BouffaloLab

Table3.1: Pin Description BL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function DescriptionBL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function Description 69 - VDDIO_4 DI/DO PAD_GPIO_26 0 - - - 1 - SPI_MISO SPI_MISO 2 - - - 3 - I2S_DI/I2S_RCLK_O I2S_DI/I2S_RCLK_O 4 - PDM_CLK_O PDM_CLK_O 5 - I2C0_SCL I2C0_SCL 6 - I2C1_SCL I2C1_SCL uart_sig_2_sel=0 UART0_RTS UART0_RTS uart_sig_2_sel=1 UART0_CTS UART0_CTS uart_sig_2_sel=2 UART0_TXD UART0_TXD uart_sig_2_sel=3 UART0_RXD UART0_RXD uart_sig_2_sel=4 UART1_RTS UART1_RTS uart_sig_2_sel=5 UART1_CTS UART1_CTS uart_sig_2_sel=6 UART1_TXD UART1_TXD uart_sig_2_sel=7 UART1_RXD UART1_RXD uart_sig_2_sel=8 UART2_RTS UART2_RTS uart_sig_2_sel=9 UART2_CTS UART2_CTS uart_sig_2_sel=10 UART2_TXD UART2_TXD uart_sig_2_sel=11 UART2_RXD UART2_RXD 8 - RMII_TXD[1] RMII_TXD[1] 9 - PIX_DAT1 PIX_DAT1 10 - - - 11 - SWGPIO26 SWGPIO26 reg_pwm1_io_sel=0 PWM0_CH2P PWM0_CH2P reg_pwm1_io_sel=1 PWM0_CH1P PWM0_CH1P reg_pwm2_io_sel=0 PWM1_CH2P PWM1_CH2P reg_pwm2_io_sel=1 PWM0_CH1P PWM0_CH1P 18 - MM_SPI_MISO MM_SPI_MISO 19 - MM_I2C0_SCL MM_I2C0_SCL 20 - MM_I2C1_SCL MM_I2C1_SCL 21 - MM_UART_RTS MM_UART_RTS 22 - - - 23 - DBI_SCL DBI_SCL 24 - DPI_DATA[9] DPI_DATA[9] 26 - M0_JTAG_TMS M0_JTAG_TMS 27 - D0_JTAG_TMS D0_JTAG_TMS BL808Datasheet 61/93 @2022BouffaloLab

Table3.1: Pin Description BL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function DescriptionBL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function Description 70 - VDDIO_4 DI/DO PAD_GPIO_27 0 - - - 1 - SPI_SCLK SPI_SCLK 2 - - - 3 - I2S_DO/I2S_RCLK_O I2S_DO/I2S_RCLK_O 4 - PDM_0_IN PDM_0_IN 5 - I2C0_SDA I2C0_SDA 6 - I2C1_SDA I2C1_SDA uart_sig_3_sel=0 UART0_RTS UART0_RTS uart_sig_3_sel=1 UART0_CTS UART0_CTS uart_sig_3_sel=2 UART0_TXD UART0_TXD uart_sig_3_sel=3 UART0_RXD UART0_RXD uart_sig_3_sel=4 UART1_RTS UART1_RTS uart_sig_3_sel=5 UART1_CTS UART1_CTS uart_sig_3_sel=6 UART1_TXD UART1_TXD uart_sig_3_sel=7 UART1_RXD UART1_RXD uart_sig_3_sel=8 UART2_RTS UART2_RTS uart_sig_3_sel=9 UART2_CTS UART2_CTS uart_sig_3_sel=10 UART2_TXD UART2_TXD uart_sig_3_sel=11 UART2_RXD UART2_RXD 8 - RMII_RXD[0] RMII_RXD[0] 9 - PIX_DAT2 PIX_DAT2 10 - - - 11 - SWGPIO27 SWGPIO27 reg_pwm1_io_sel=0 PWM0_CH3P PWM0_CH3P reg_pwm1_io_sel=1 PWM0_CH1N PWM0_CH1N reg_pwm2_io_sel=0 PWM1_CH3P PWM1_CH3P reg_pwm2_io_sel=1 PWM0_CH2P PWM0_CH2P 18 - MM_SPI_SCLK MM_SPI_SCLK 19 - MM_I2C0_SDA MM_I2C0_SDA 20 - MM_I2C1_SDA MM_I2C1_SDA 21 - MM_UART_CTS MM_UART_CTS 22 - - - 23 - DBI_SDA DBI_SDA 24 - DPI_DATA[10] DPI_DATA[10] 26 - M0_JTAG_TDO M0_JTAG_TDO 27 - D0_JTAG_TDO D0_JTAG_TDO BL808Datasheet 62/93 @2022BouffaloLab

Table3.1: Pin Description BL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function DescriptionBL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function Description 71 - VDDIO_4 DI/DO PAD_GPIO_28 0 - - - 1 - SPI_SS SPI_SS 2 - - - 3 - I2S_BCLK I2S_BCLK 4 - - - 5 - I2C0_SCL I2C0_SCL 6 - I2C1_SCL I2C1_SCL uart_sig_4_sel=0 UART0_RTS UART0_RTS uart_sig_4_sel=1 UART0_CTS UART0_CTS uart_sig_4_sel=2 UART0_TXD UART0_TXD uart_sig_4_sel=3 UART0_RXD UART0_RXD uart_sig_4_sel=4 UART1_RTS UART1_RTS uart_sig_4_sel=5 UART1_CTS UART1_CTS uart_sig_4_sel=6 UART1_TXD UART1_TXD uart_sig_4_sel=7 UART1_RXD UART1_RXD uart_sig_4_sel=8 UART2_RTS UART2_RTS uart_sig_4_sel=9 UART2_CTS UART2_CTS uart_sig_4_sel=10 UART2_TXD UART2_TXD uart_sig_4_sel=11 UART2_RXD UART2_RXD 8 - RMII_RXD[1] RMII_RXD[1] 9 - PIX_DAT3 PIX_DAT3 10 - - - 11 - SWGPIO28 SWGPIO28 reg_pwm1_io_sel=0 PWM0_CH0P PWM0_CH0P reg_pwm1_io_sel=1 PWM0_CH2P PWM0_CH2P reg_pwm2_io_sel=0 PWM1_CH0P PWM1_CH0P reg_pwm2_io_sel=1 PWM0_BREAK_EXT PWM0_BREAK_EXT 18 - MM_SPI_SS MM_SPI_SS 19 - MM_I2C0_SCL MM_I2C0_SCL 20 - MM_I2C1_SCL MM_I2C1_SCL 21 - MM_UART_TXD MM_UART_TXD 22 - - - 23 - DBI_CSn DBI_CSn 24 - DPI_DATA[11] DPI_DATA[11] 26 - M0_JTAG_TCLK M0_JTAG_TCLK 27 - D0_JTAG_TCK D0_JTAG_TCK BL808Datasheet 63/93 @2022BouffaloLab

Table3.1: Pin Description BL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function DescriptionBL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function Description 72 - VDDIO_4 DI/DO PAD_GPIO_29 0 - - - 1 - SPI_MOSI SPI_MOSI 2 - - - 3 - I2S_FS I2S_FS 4 - - - 5 - I2C0_SDA I2C0_SDA 6 - I2C1_SDA I2C1_SDA uart_sig_5_sel=0 UART0_RTS UART0_RTS uart_sig_5_sel=1 UART0_CTS UART0_CTS uart_sig_5_sel=2 UART0_TXD UART0_TXD uart_sig_5_sel=3 UART0_RXD UART0_RXD uart_sig_5_sel=4 UART1_RTS UART1_RTS uart_sig_5_sel=5 UART1_CTS UART1_CTS uart_sig_5_sel=6 UART1_TXD UART1_TXD uart_sig_5_sel=7 UART1_RXD UART1_RXD uart_sig_5_sel=8 UART2_RTS UART2_RTS uart_sig_5_sel=9 UART2_CTS UART2_CTS uart_sig_5_sel=10 UART2_TXD UART2_TXD uart_sig_5_sel=11 UART2_RXD UART2_RXD 8 - RMII_RXERR RMII_RXERR 9 - PIX_DAT4 PIX_DAT4 10 - - - 11 - SWGPIO29 SWGPIO29 reg_pwm1_io_sel=0 PWM0_CH1P PWM0_CH1P reg_pwm1_io_sel=1 PWM0_CH2N PWM0_CH2N reg_pwm2_io_sel=0 PWM1_CH1P PWM1_CH1P reg_pwm2_io_sel=1 PWM0_CH0P PWM0_CH0P 18 - MM_SPI_MOSI MM_SPI_MOSI 19 - MM_I2C0_SDA MM_I2C0_SDA 20 - MM_I2C1_SDA MM_I2C1_SDA 21 - MM_UART_RXD MM_UART_RXD 22 - - - 23 - DBI_DCn DBI_DCn 24 - DPI_DATA[12] DPI_DATA[12] 26 - M0_JTAG_TDI M0_JTAG_TDI 27 - D0_JTAG_TDI D0_JTAG_TDI BL808Datasheet 64/93 @2022BouffaloLab

Table3.1: Pin Description BL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function DescriptionBL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function Description 73 - VDDIO_4 DI/DO PAD_GPIO_30 0 - - - 1 - SPI_MISO SPI_MISO 2 - - - 3 - I2S_DI/I2S_RCLK_O I2S_DI/I2S_RCLK_O 4 - - - 5 - I2C0_SCL I2C0_SCL 6 - I2C1_SCL I2C1_SCL uart_sig_6_sel=0 UART0_RTS UART0_RTS uart_sig_6_sel=1 UART0_CTS UART0_CTS uart_sig_6_sel=2 UART0_TXD UART0_TXD uart_sig_6_sel=3 UART0_RXD UART0_RXD uart_sig_6_sel=4 UART1_RTS UART1_RTS uart_sig_6_sel=5 UART1_CTS UART1_CTS uart_sig_6_sel=6 UART1_TXD UART1_TXD uart_sig_6_sel=7 UART1_RXD UART1_RXD uart_sig_6_sel=8 UART2_RTS UART2_RTS uart_sig_6_sel=9 UART2_CTS UART2_CTS uart_sig_6_sel=10 UART2_TXD UART2_TXD uart_sig_6_sel=11 UART2_RXD UART2_RXD 8 - RMII_TX_EN RMII_TX_EN 9 - PIX_DAT5 PIX_DAT5 10 - - - 11 - SWGPIO30 SWGPIO30 reg_pwm1_io_sel=0 PWM0_CH2P PWM0_CH2P reg_pwm1_io_sel=1 PWM0_CH3P PWM0_CH3P reg_pwm2_io_sel=0 PWM1_CH2P PWM1_CH2P reg_pwm2_io_sel=1 PWM0_CH1P PWM0_CH1P 18 - MM_SPI_MISO MM_SPI_MISO 19 - MM_I2C0_SCL MM_I2C0_SCL 20 - MM_I2C1_SCL MM_I2C1_SCL 21 - MM_UART_RTS MM_UART_RTS 22 - - - 23 - DBI_SCL DBI_SCL 24 - DPI_DATA[13] DPI_DATA[13] 26 - M0_JTAG_TMS M0_JTAG_TMS 27 - D0_JTAG_TMS D0_JTAG_TMS BL808Datasheet 65/93 @2022BouffaloLab

Table3.1: Pin Description BL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function DescriptionBL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function Description 74 - VDDIO_4 DI/DO PAD_GPIO_31 0 - - - 1 - SPI_SCLK SPI_SCLK 2 - - - 3 - I2S_DO/I2S_RCLK_O I2S_DO/I2S_RCLK_O 4 - - - 5 - I2C0_SDA I2C0_SDA 6 - I2C1_SDA I2C1_SDA uart_sig_7_sel=0 UART0_RTS UART0_RTS uart_sig_7_sel=1 UART0_CTS UART0_CTS uart_sig_7_sel=2 UART0_TXD UART0_TXD uart_sig_7_sel=3 UART0_RXD UART0_RXD uart_sig_7_sel=4 UART1_RTS UART1_RTS uart_sig_7_sel=5 UART1_CTS UART1_CTS uart_sig_7_sel=6 UART1_TXD UART1_TXD uart_sig_7_sel=7 UART1_RXD UART1_RXD uart_sig_7_sel=8 UART2_RTS UART2_RTS uart_sig_7_sel=9 UART2_CTS UART2_CTS uart_sig_7_sel=10 UART2_TXD UART2_TXD uart_sig_7_sel=11 UART2_RXD UART2_RXD 8 - RMII_RX_DV RMII_RX_DV 9 - PIX_DAT6 PIX_DAT6 10 - - - 11 - SWGPIO31 SWGPIO31 reg_pwm1_io_sel=0 PWM0_CH3P PWM0_CH3P reg_pwm1_io_sel=1 PWM0_CH3N PWM0_CH3N reg_pwm2_io_sel=0 PWM1_CH3P PWM1_CH3P reg_pwm2_io_sel=1 PWM0_CH2P PWM0_CH2P 18 - MM_SPI_SCLK MM_SPI_SCLK 19 - MM_I2C0_SDA MM_I2C0_SDA 20 - MM_I2C1_SDA MM_I2C1_SDA 21 - MM_UART_CTS MM_UART_CTS 22 - - - 23 - DBI_SDA DBI_SDA 24 - DPI_DATA[14] DPI_DATA[14] 26 - M0_JTAG_TDO M0_JTAG_TDO 27 - D0_JTAG_TDO D0_JTAG_TDO BL808Datasheet 66/93 @2022BouffaloLab

Table3.1: Pin Description BL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function DescriptionBL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function Description 75 - VDDIO_4 DI/DO PAD_GPIO_32 0 - - - 1 - SPI_SS SPI_SS 2 - - - 3 - I2S_BCLK I2S_BCLK 4 - - - 5 - I2C0_SCL I2C0_SCL 6 - I2C1_SCL I2C1_SCL uart_sig_8_sel=0 UART0_RTS UART0_RTS uart_sig_8_sel=1 UART0_CTS UART0_CTS uart_sig_8_sel=2 UART0_TXD UART0_TXD uart_sig_8_sel=3 UART0_RXD UART0_RXD uart_sig_8_sel=4 UART1_RTS UART1_RTS uart_sig_8_sel=5 UART1_CTS UART1_CTS uart_sig_8_sel=6 UART1_TXD UART1_TXD uart_sig_8_sel=7 UART1_RXD UART1_RXD uart_sig_8_sel=8 UART2_RTS UART2_RTS uart_sig_8_sel=9 UART2_CTS UART2_CTS uart_sig_8_sel=10 UART2_TXD UART2_TXD uart_sig_8_sel=11 UART2_RXD UART2_RXD 8 - RMII_MDC RMII_MDC 9 - PIX_DAT7 PIX_DAT7 10 - - - 11 - SWGPIO32 SWGPIO32 reg_pwm1_io_sel=0 PWM0_CH0P PWM0_CH0P reg_pwm1_io_sel=1 PWM0_CH0P PWM0_CH0P reg_pwm2_io_sel=0 PWM1_CH0P PWM1_CH0P reg_pwm2_io_sel=1 PWM0_BREAK_EXT PWM0_BREAK_EXT 18 - MM_SPI_SS MM_SPI_SS 19 - MM_I2C0_SCL MM_I2C0_SCL 20 - MM_I2C1_SCL MM_I2C1_SCL 21 - MM_UART_TXD MM_UART_TXD 22 - - - 23 - DBI_CSn DBI_CSn 24 - DPI_DATA[15] DPI_DATA[15] 26 - M0_JTAG_TCLK M0_JTAG_TCLK 27 - D0_JTAG_TCK D0_JTAG_TCK BL808Datasheet 67/93 @2022BouffaloLab

Table3.1: Pin Description BL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function DescriptionBL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function Description 76 - VDDIO_4 DI/DO PAD_GPIO_33 0 - - - 1 - SPI_MOSI SPI_MOSI 2 - - - 3 - I2S_FS I2S_FS 4 - - - 5 - I2C0_SDA I2C0_SDA 6 - I2C1_SDA I2C1_SDA uart_sig_9_sel=0 UART0_RTS UART0_RTS uart_sig_9_sel=1 UART0_CTS UART0_CTS uart_sig_9_sel=2 UART0_TXD UART0_TXD uart_sig_9_sel=3 UART0_RXD UART0_RXD uart_sig_9_sel=4 UART1_RTS UART1_RTS uart_sig_9_sel=5 UART1_CTS UART1_CTS uart_sig_9_sel=6 UART1_TXD UART1_TXD uart_sig_9_sel=7 UART1_RXD UART1_RXD uart_sig_9_sel=8 UART2_RTS UART2_RTS uart_sig_9_sel=9 UART2_CTS UART2_CTS uart_sig_9_sel=10 UART2_TXD UART2_TXD uart_sig_9_sel=11 UART2_RXD UART2_RXD 8 - RMII_MDIO RMII_MDIO 9 - - - 10 - - - 11 - SWGPIO33 SWGPIO33 reg_pwm1_io_sel=0 PWM0_CH1P PWM0_CH1P reg_pwm1_io_sel=1 PWM0_CH0N PWM0_CH0N reg_pwm2_io_sel=0 PWM1_CH1P PWM1_CH1P reg_pwm2_io_sel=1 PWM0_CH0P PWM0_CH0P 18 - MM_SPI_MOSI MM_SPI_MOSI 19 - MM_I2C0_SDA MM_I2C0_SDA 20 - MM_I2C1_SDA MM_I2C1_SDA 21 - MM_UART_RXD MM_UART_RXD 22 - - - 23 - DBI_DCn DBI_DCn 24 - DPI_DE DPI_DE 26 - M0_JTAG_TDI M0_JTAG_TDI 27 - D0_JTAG_TDI D0_JTAG_TDI 77 77 - Power VDDIO4 - - VDDIO4 VDDIO4 78 78 - Power VDD18_FLASH - - VDD18_FLASH VDD18_FLASH BL808Datasheet 68/93 @2022BouffaloLab

Table3.1: Pin Description BL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function DescriptionBL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function Description 79 79 VDDIO_4 DI/DO PAD_GPIO_34 0 - - - 1 - SPI_MISO SPI_MISO 2 - SF2_CLK SF2_CLK 3 - I2S_DI/I2S_RCLK_O I2S_DI/I2S_RCLK_O 4 - PDM_1_IN PDM_1_IN 5 - I2C0_SCL I2C0_SCL 6 - I2C1_SCL I2C1_SCL uart_sig_10_sel=0 UART0_RTS UART0_RTS uart_sig_10_sel=1 UART0_CTS UART0_CTS uart_sig_10_sel=2 UART0_TXD UART0_TXD uart_sig_10_sel=3 UART0_RXD UART0_RXD uart_sig_10_sel=4 UART1_RTS UART1_RTS uart_sig_10_sel=5 UART1_CTS UART1_CTS uart_sig_10_sel=6 UART1_TXD UART1_TXD uart_sig_10_sel=7 UART1_RXD UART1_RXD uart_sig_10_sel=8 UART2_RTS UART2_RTS uart_sig_10_sel=9 UART2_CTS UART2_CTS uart_sig_10_sel=10 UART2_TXD UART2_TXD uart_sig_10_sel=11 UART2_RXD UART2_RXD 8 - RMII_RXERR RMII_RXERR 9 - - - 10 - ADC_CH11 ADC_CH11 11 - SWGPIO34 SWGPIO34 reg_pwm1_io_sel=0 PWM0_CH2P PWM0_CH2P reg_pwm1_io_sel=1 PWM0_CH1P PWM0_CH1P reg_pwm2_io_sel=0 PWM1_CH2P PWM1_CH2P reg_pwm2_io_sel=1 PWM0_CH1P PWM0_CH1P 18 - MM_SPI_MISO MM_SPI_MISO 19 - MM_I2C0_SCL MM_I2C0_SCL 20 - MM_I2C1_SCL MM_I2C1_SCL 21 - MM_UART_RTS MM_UART_RTS 22 - - - 23 - DBI_SCL DBI_SCL 24 - - - 26 - M0_JTAG_TMS M0_JTAG_TMS 27 - D0_JTAG_TMS D0_JTAG_TMS BL808Datasheet 69/93 @2022BouffaloLab

Table3.1: Pin Description BL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function DescriptionBL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function Description 80 80 VDDIO_4 DI/DO PAD_GPIO_35 0 - - - 1 - SPI_SCLK SPI_SCLK 2 - SF2_CS SF2_CS 3 - I2S_DO/I2S_RCLK_O I2S_DO/I2S_RCLK_O 4 - PDM_CLK_O PDM_CLK_O 5 - I2C0_SDA I2C0_SDA 6 - I2C1_SDA I2C1_SDA uart_sig_11_sel=0 UART0_RTS UART0_RTS uart_sig_11_sel=1 UART0_CTS UART0_CTS uart_sig_11_sel=2 UART0_TXD UART0_TXD uart_sig_11_sel=3 UART0_RXD UART0_RXD uart_sig_11_sel=4 UART1_RTS UART1_RTS uart_sig_11_sel=5 UART1_CTS UART1_CTS uart_sig_11_sel=6 UART1_TXD UART1_TXD uart_sig_11_sel=7 UART1_RXD UART1_RXD uart_sig_11_sel=8 UART2_RTS UART2_RTS uart_sig_11_sel=9 UART2_CTS UART2_CTS uart_sig_11_sel=10 UART2_TXD UART2_TXD uart_sig_11_sel=11 UART2_RXD UART2_RXD 8 - RMII_TX_EN RMII_TX_EN 9 - - - 10 - - - 11 - SWGPIO35 SWGPIO35 reg_pwm1_io_sel=0 PWM0_CH3P PWM0_CH3P reg_pwm1_io_sel=1 PWM0_CH1N PWM0_CH1N reg_pwm2_io_sel=0 PWM1_CH3P PWM1_CH3P reg_pwm2_io_sel=1 PWM0_CH2P PWM0_CH2P 18 - MM_SPI_SCLK MM_SPI_SCLK 19 - MM_I2C0_SDA MM_I2C0_SDA 20 - MM_I2C1_SDA MM_I2C1_SDA 21 - MM_UART_CTS MM_UART_CTS 22 - - - 23 - DBI_SDA DBI_SDA 24 - - - 26 - M0_JTAG_TDO M0_JTAG_TDO 27 - D0_JTAG_TDO D0_JTAG_TDO BL808Datasheet 70/93 @2022BouffaloLab

Table3.1: Pin Description BL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function DescriptionBL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function Description 81 81 VDDIO_4 DI/DO PAD_GPIO_36 0 - - - 1 - SPI_SS SPI_SS 2 - SF2_D0 SF2_D0 3 - I2S_BCLK I2S_BCLK 4 - PDM_0_IN PDM_0_IN 5 - I2C0_SCL I2C0_SCL 6 - I2C1_SCL I2C1_SCL uart_sig_0_sel=0 UART0_RTS UART0_RTS uart_sig_0_sel=1 UART0_CTS UART0_CTS uart_sig_0_sel=2 UART0_TXD UART0_TXD uart_sig_0_sel=3 UART0_RXD UART0_RXD uart_sig_0_sel=4 UART1_RTS UART1_RTS uart_sig_0_sel=5 UART1_CTS UART1_CTS uart_sig_0_sel=6 UART1_TXD UART1_TXD uart_sig_0_sel=7 UART1_RXD UART1_RXD uart_sig_0_sel=8 UART2_RTS UART2_RTS uart_sig_0_sel=9 UART2_CTS UART2_CTS uart_sig_0_sel=10 UART2_TXD UART2_TXD uart_sig_0_sel=11 UART2_RXD UART2_RXD 8 - RMII_RX_DV RMII_RX_DV 9 - - - 10 - - - 11 - SWGPIO36 SWGPIO36 reg_pwm1_io_sel=0 PWM0_CH0P PWM0_CH0P reg_pwm1_io_sel=1 PWM0_CH2P PWM0_CH2P reg_pwm2_io_sel=0 PWM1_CH0P PWM1_CH0P reg_pwm2_io_sel=1 PWM0_BREAK_EXT PWM0_BREAK_EXT 18 - MM_SPI_SS MM_SPI_SS 19 - MM_I2C0_SCL MM_I2C0_SCL 20 - MM_I2C1_SCL MM_I2C1_SCL 21 - MM_UART_TXD MM_UART_TXD 22 - - - 23 - DBI_CSn DBI_CSn 24 - - - 26 - M0_JTAG_TCLK M0_JTAG_TCLK 27 - D0_JTAG_TCK D0_JTAG_TCK BL808Datasheet 71/93 @2022BouffaloLab

Table3.1: Pin Description BL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function DescriptionBL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function Description 82 82 VDDIO_4 DI/DO PAD_GPIO_37 0 - - - 1 - SPI_MOSI SPI_MOSI 2 - SF2_D1 SF2_D1 3 - I2S_FS I2S_FS 4 - PDM_1_IN PDM_1_IN 5 - I2C0_SDA I2C0_SDA 6 - I2C1_SDA I2C1_SDA uart_sig_1_sel=0 UART0_RTS UART0_RTS uart_sig_1_sel=1 UART0_CTS UART0_CTS uart_sig_1_sel=2 UART0_TXD UART0_TXD uart_sig_1_sel=3 UART0_RXD UART0_RXD uart_sig_1_sel=4 UART1_RTS UART1_RTS uart_sig_1_sel=5 UART1_CTS UART1_CTS uart_sig_1_sel=6 UART1_TXD UART1_TXD uart_sig_1_sel=7 UART1_RXD UART1_RXD uart_sig_1_sel=8 UART2_RTS UART2_RTS uart_sig_1_sel=9 UART2_CTS UART2_CTS uart_sig_1_sel=10 UART2_TXD UART2_TXD uart_sig_1_sel=11 UART2_RXD UART2_RXD 8 - RMII_MDC RMII_MDC 9 - - - 10 - - - 11 - SWGPIO37 SWGPIO37 reg_pwm1_io_sel=0 PWM0_CH1P PWM0_CH1P reg_pwm1_io_sel=1 PWM0_CH2N PWM0_CH2N reg_pwm2_io_sel=0 PWM1_CH1P PWM1_CH1P reg_pwm2_io_sel=1 PWM0_CH0P PWM0_CH0P 18 - MM_SPI_MOSI MM_SPI_MOSI 19 - MM_I2C0_SDA MM_I2C0_SDA 20 - MM_I2C1_SDA MM_I2C1_SDA 21 - MM_UART_RXD MM_UART_RXD 22 - - - 23 - DBI_DCn DBI_DCn 24 - - - 26 - M0_JTAG_TDI M0_JTAG_TDI 27 - D0_JTAG_TDI D0_JTAG_TDI BL808Datasheet 72/93 @2022BouffaloLab

Table3.1: Pin Description BL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function DescriptionBL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function Description 83 83 VDDIO_4 DI/DO PAD_GPIO_38 0 - - - 1 - SPI_MISO SPI_MISO 2 - SF2_D2 SF2_D2 3 - I2S_DI/I2S_RCLK_O I2S_DI/I2S_RCLK_O 4 - PDM_CLK_O PDM_CLK_O 5 - I2C0_SCL I2C0_SCL 6 - I2C1_SCL I2C1_SCL uart_sig_2_sel=0 UART0_RTS UART0_RTS uart_sig_2_sel=1 UART0_CTS UART0_CTS uart_sig_2_sel=2 UART0_TXD UART0_TXD uart_sig_2_sel=3 UART0_RXD UART0_RXD uart_sig_2_sel=4 UART1_RTS UART1_RTS uart_sig_2_sel=5 UART1_CTS UART1_CTS uart_sig_2_sel=6 UART1_TXD UART1_TXD uart_sig_2_sel=7 UART1_RXD UART1_RXD uart_sig_2_sel=8 UART2_RTS UART2_RTS uart_sig_2_sel=9 UART2_CTS UART2_CTS uart_sig_2_sel=10 UART2_TXD UART2_TXD uart_sig_2_sel=11 UART2_RXD UART2_RXD 8 - RMII_MDIO RMII_MDIO 9 - - - 10 - - - 11 - SWGPIO38 SWGPIO38 reg_pwm1_io_sel=0 PWM0_CH2P PWM0_CH2P reg_pwm1_io_sel=1 PWM0_CH3P PWM0_CH3P reg_pwm2_io_sel=0 PWM1_CH2P PWM1_CH2P reg_pwm2_io_sel=1 PWM0_CH1P PWM0_CH1P 18 - MM_SPI_MISO MM_SPI_MISO 19 - MM_I2C0_SCL MM_I2C0_SCL 20 - MM_I2C1_SCL MM_I2C1_SCL 21 - MM_UART_RTS MM_UART_RTS 22 - - - 23 - DBI_SCL DBI_SCL 24 - - - 26 - M0_JTAG_TMS M0_JTAG_TMS 27 - D0_JTAG_TMS D0_JTAG_TMS BL808Datasheet 73/93 @2022BouffaloLab

Table3.1: Pin Description BL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function DescriptionBL808C BL808D Voltage Domain T ype Pin Name GPIO Function SelectNumber Peripheral Internal FunctionSelect P AD Main Function Description 84 84 VDDIO_4 DI/DO PAD_GPIO_39 0 - - - 1 - SPI_SCLK SPI_SCLK 2 - SF2_D3 SF2_D3 3 - I2S_DO/I2S_RCLK_O I2S_DO/I2S_RCLK_O 4 - PDM_0_IN PDM_0_IN 5 - I2C0_SDA I2C0_SDA 6 - I2C1_SDA I2C1_SDA uart_sig_3_sel=0 UART0_RTS UART0_RTS uart_sig_3_sel=1 UART0_CTS UART0_CTS uart_sig_3_sel=2 UART0_TXD UART0_TXD uart_sig_3_sel=3 UART0_RXD UART0_RXD uart_sig_3_sel=4 UART1_RTS UART1_RTS uart_sig_3_sel=5 UART1_CTS UART1_CTS uart_sig_3_sel=6 UART1_TXD UART1_TXD uart_sig_3_sel=7 UART1_RXD UART1_RXD uart_sig_3_sel=8 UART2_RTS UART2_RTS uart_sig_3_sel=9 UART2_CTS UART2_CTS uart_sig_3_sel=10 UART2_TXD UART2_TXD uart_sig_3_sel=11 UART2_RXD UART2_RXD 8 - - - 9 - - - 10 - - - 11 - SWGPIO39 SWGPIO39 reg_pwm1_io_sel=0 PWM0_CH3P PWM0_CH3P reg_pwm1_io_sel=1 PWM0_CH3N PWM0_CH3N reg_pwm2_io_sel=0 PWM1_CH3P PWM1_CH3P reg_pwm2_io_sel=1 PWM0_CH2P PWM0_CH2P 18 - MM_SPI_SCLK MM_SPI_SCLK 19 - MM_I2C0_SDA MM_I2C0_SDA 20 - MM_I2C1_SDA MM_I2C1_SDA 21 - MM_UART_CTS MM_UART_CTS 22 - - - 23 - DBI_SDA DBI_SDA 24 - - - 26 - M0_JTAG_TDO M0_JTAG_TDO 27 - D0_JTAG_TDO D0_JTAG_TDO 85 85 - Power DCDC11_VOUT - - DCDC11_VOUT Feedbackvoltage input, 1.1V 86 86 - Power SW_DCDC11 - - SW_DCDC11 DCDCswitchoutput,connectedtopowerinductor 87 87 - Power VDD33_DCDC11 - - VDD33_DCDC11 DCDCpower input, 3.3V 88 88 - Power VSS_DCDC11 - - VSS_DCDC11 DCDCcircuit ground pin 1 Thisfunction defaults to SPI_MOSI, which canbe converted to SPI_MISO through aregister. BL808Datasheet 74/93 @2022BouffaloLab

RFCharacteristics of Receiving and Transmittingmodes. Table4.1: WLAN TX RFcharacteristics Mode Note Performance @3.3V,25°C Mode Note Min. T yp Max. Unit TXpower 11b- 1Mbps 21 dBm 11b- 11Mbps 21 11g- 6Mbps 19 11g- 54Mbps 18 11n- MCS0 19 11n- MCS7 17 Table4.2: WLAN RX RFcharacteristics Mode Note Performance @3.3V,25°C Mode Note Min. T yp Max. Unit RXsensitivity 11b- 1Mbps -98 dBm 11b- 11Mbps -90 11g- 6Mbps -93 11g- 54Mbps -77 11n- MCS0 -93 11n- MCS7 -74 BL808Datasheet 75/93 @2022BouffaloLab

Table4.3: BLE RX RFcharacteristics Mode Note Performance @3.3V,25°C Mode Note Min. T yp Max. Unit RXsensitivity 1Mbps -99 dBm 2Mbps -97 S8(125Kbps) -105 S2(500Kbps) -102 Table4.4: BLE TX RFcharacteristics Mode Note Performance @3.3V,25°C Mode Note Min. T yp Max. Unit TXpower 10 20 dBm Table4.5: BT TX RFcharacteristics Mode Note Performance @3.3V,25℃ Mode Note Min. T yp Max. Unit BRoutput power 10 dBm EDRoutput power 8 dBm Δf1avg BR1Mbps 159 kHz Δf2max 132 Δf2avg/Δf1avg 0.88 EDR2Mbps -3 3 kHzωi -12 6 ωi+ω0 -6 3 RMSDEVM 5 %99%DEVM 9 PeakDEVM 10 EDR3Mbps -3 3 kHzωi -12 6 ωi+ω0 -6 3 RMSDEVM 5 %99%DEVM 9 PeakDEVM 10 BL808Datasheet 76/93 @2022BouffaloLab

Table4.6: BT RX RFCharacteristics Mode Note Performance @3.3V,25℃ Mode Note Min. T yp Max. Unit Sensitivity BR1Mbps DirtyOff -94 dBm Maximumreception level Sensitivity EDR2Mbps -95 Maximumreception level Sensitivity EDR3Mbps -89 Maximumreception level BL808Datasheet 77/93 @2022BouffaloLab

5.1 Electrical characteristics

Table5.1: Analog-to-Digital converter electricalcharacteristics At 25°C, A VDD25_CODEC= 2.5 V, fS = 48kHz, 20-bit audio data (unless otherwise noted) Parameter Conditions Min. T yp Max. Unit AUDIOADC Inputsignal full-scale level Differentialinput，0dB PGA gain 1.8 VrmsSingle-endedinput，0dB PGA gain 0.9 1.4 Inputcommon-mode voltage differential/Single-endedinput 1.23 SNR Signal-to-noiseratio, A-weighted fS=48 kHz, 0 dB PGAgain, 1kHz full-scale sine-waveinput 103 dB DR Dynamicrange, A-weighted fS=48 kHz, 0 dB PGAgain, 1kHz -60dB sine-waveinput 103 THD Totalharmonic distortion fS=48 kHz, 0 dB PGAgain, 1kHz -5dB sine-waveinput -95 PSRR Powersupply rejection ratio 234Hz, 100 mVPP on AVDD, single-endedinput - 234Hz, 100 mVPP on AVDD, differentialinput - Crosstalk ADCchannel separation 0dB PGA gain, 1kHzfull-scale sine-wave input 130 36dBPGA gain, 1kHzfull-scale sine-wave input 100 Freq. Response -5dB20Hz~24kHz sine-wave input 0.25 ADCprogrammable analogue amplifier gain range Analoguegain resolution = 3dB 0 42 ADCprogrammable digital gain range Digitalgain resolution = 0.5dB -95.5 31.5 BL808Datasheet 78/93 @2022BouffaloLab

Table5.1: Analog-to-Digital converter electricalcharacteristics At 25°C, A VDD25_CODEC= 2.5 V, fS = 48kHz, 20-bit audio data (unless otherwise noted) Parameter Conditions Min. T yp Max. Unit Inputresistance Analoguegain 0dB 16 kΩ Analoguegain 6dB~42dB 160 640 Inputcapacitance 10 pF MICROPHONE BIAS Biasvoltage Programmablesettings 1.8 2.5 V Currentsourcing 2.5Vsetting, load = 1 KΩ 2.2 mA Integratednoise BW= 20 Hz to 20 kHz,A-weighted, 1μF capacitorbetween MICBIAS and AGND 1.5 μV rms Table5.2: Digital-to-Analog converter electricalcharacteristics At 25°C, A VDD25_CODEC= 2.5 V, fS = 48kHz, 20-bit audio data (unless otherwise noted) Parameter Conditions Min. T yp Max. Unit AUDIODAC Inputsignal full-scale level Differentialoutput，0dB line-out gain 1.68 VrmsSingle-endedoutput，0dB line-out gain 0.84 Inputcommon-mode voltage 1.23 SNR Signal-to-noiseratio, A-Wwithout Noise Gating fS=48 kHz, 1kHzfull-scale sine-wave output 104 dB Signal-to-noiseratio, A-Wwith Noise Gating fS=48 kHz, 1kHzfull-scale sine-wave output 112 DR Dynamicrange, A-weighted fS=48 kHz, 1kHz-60dB sine-wave output 104 THD Totalharmonic distortion fS=48 kHz, 1kHz-5dB sine-wave output -89 PSRR Powersupply rejection ratio 234Hz, 100 mVPP on AVDD, single-endedoutput - 234Hz, 100 mVPP on AVDD, differentialoutput - NoiseFloor A-weightedwithout Noise Gating 10 μV rmsNoiseFloor A-weightedwith Noise Gating 4.3 Crosstalk DACchannel separation 1kHzfull-scale sine-wave output 130 dB Freq. Response -5dB20Hz~24kHz sine-wave input 0.25 DCoffset P/Noutput DC offset 0.5 mV BL808Datasheet 79/93 @2022BouffaloLab

Table5.2: Digital-to-Analog converter electricalcharacteristics At 25°C, A VDD25_CODEC= 2.5 V, fS = 48kHz, 20-bit audio data (unless otherwise noted) Parameter Conditions Min. T yp Max. Unit DACprogrammable analogue amplifier gain range Analoguegain resolution = 3dB -21 0 dB DACprogrammable digital gain range Digitalgain resolution = 0.5dB -95.5 31.5 BL808Datasheet 80/93 @2022BouffaloLab

PowerConsumption of each power mode. Table6.1: Power Modes &Whole-chip Current Mode Conditions Performance @25℃ Mode Conditions Min. T yp Max. Unit RX 3.3V，RFonly 13 mA TX 11b- 11Mbps @21dBm 3.3V，RFonly Duty99% 295 HBN HBN0 Vdd11_aon= 0.9V 7.9 uA Vdd11_aon= 1.1V 14.3 PDS PDS7 Vdd11_aon= 0.9V 70.8 Vdd11_aon= 1.1V 121.7 Shut-down <0.5 BL808Datasheet 81/93 @2022BouffaloLab

7.1 Absolute Maximum Rating

Table7.1: Absolute Maximum Rating Pin Name Min. Max. Unit VDD33_DCDC18,VDD33_DCDC11 -0.3 3.63 V VDD33(USB) -0.3 3.63 V VDDIO1 -0.3 3.63 V VDDIO2 -0.3 3.63 V VDDIO3 -0.3 3.63 V VDDIO4 -0.3 3.63 V VDD33_RF -0.3 3.63 V AVDD33_CODEC -0.3 3.63 V

7.2 Operating Condition

7.2.1 Power characteristics

Table7.2: Recommended Power OperatingRange Pin Name Min. T yp Max. Unit VDD33_DCDC18,VDD33_DCDC11 3 3.3 3.63 V VDD33(USB) 3 3.3 3.63 V VDDIO2 3 3.3 3.63 V BL808Datasheet 82/93 @2022BouffaloLab

Table7.2: Recommended Power OperatingRange Pin Name Min. T yp Max. Unit VDD33_RF 3 3.3 3.63 V AVDD33_CODEC 3 3.3 3.63 V

7.2.2 IO DC characteristics

Table7.3: IO DC characteristics Symbol Description Conditions Min. T yp Max. Unit VOH Outputvoltage high 0.8* VIO V VOL Outputvoltage low 0.1* VIO V VIH Inputvoltage high 0.7* VIO VIO+ 0.3 V VIL Inputvoltage low -0.3 0.3* VIO V

7.2.3 Power-on sequence

In order to ensure normal power-on startup, the power, reset and Bootstrap pins need to meet the corresponding timingrequirements. VDD33 PU_CHIP Bootstrap XTAL VDDCORE VDDIO 90% t2.1 t2.2 Fig.7.1: Power-on sequence BL808Datasheet 83/93 @2022BouffaloLab

Table7.4: Power-on sequence parameters Parameters Description Min.(ms) T yp(ms) Max.(ms) t0 Risetime for supply voltage toreach 90% 2 t1 Delaytime before power rises untilPU_CHIP is pulled high 0.1 t2.1 Bootstrappin 1levelsetuptimebeforePU_CHIPispulledhigh 0 t2.2 Holdtime of Bootstrap pin levelafter PU_CHIP is pulled high2 t3 Thetime that PU_CHIP is pulledhigh to VDDCORE output 2 t4 The time when PU_CHIP is pulled high until XTAL starts to vibrate 1 Bootstrappin is GPIO39.

7.2.4 Temperature sensor characteristics

Table7.5: Recommended TemperatureOperating Range Item Min. Max. Unit Temperature MainDie -40 85 Multi-DieSiP -40 85

7.2.5 General operating conditions

Table7.6: General Operating Conditions Item Description Min. T yp Max. Unit FCPU CPUclock frequency (M0) 320 MHz CPUclock frequency (D0) 480 BL808Datasheet 84/93 @2022BouffaloLab

8.1 Moisture Sensitivity Level(MSL)

Themoisturesensitivitylevelofthechipis: MSL3. Afterthevacuumpackageisopened,itneedstobeusedupwithin 168hours (7 days) at ≤30°C/60%RH,otherwise it needs to be bakedand put online. Forbaking temperature and time, pleaserefer to IPC/JEDECJ-STD-033B01. Table8.1: Reference Conditions forDrying Mounted or Unmounted SMD Packages(User Bake: Floor lifebegins countingat time = 0 after bake) Package Body Level Bake @ 125°C Bake @ 90°C ≤5%RH Bake @ 40°C ≤5%RHBake @ 125°C Bake @ 90°C ≤5%RH Bake @ 40°C ≤5%RH Exceeding FloorLife by>72 h Exceeding FloorLife by≤72 h Exceeding FloorLife by>72 h Exceeding FloorLife by≤72 h Exceeding FloorLife by>72 h Exceeding FloorLife by≤72 h Package Body Level Exceeding FloorLife by>72 h Exceeding FloorLife by≤72 h Exceeding FloorLife by>72 h Exceeding FloorLife by≤72 h Exceeding FloorLife by>72 h Exceeding FloorLife by≤72 h Thickness ≤1.4mm 2 5hours 3hours 17hours 11hours 8days 5days 2a 7hours 5hours 23hours 13hours 9days 7days 3 9hours 7hours 33hours 23hours 13days 9days 4 11hours 7hours 37hours 23hours 15days 9days 5 12hours 7hours 41hours 24hours 17days 10days 5a 16hours 10hours 54hours 24hours 22days 10days BL808Datasheet 85/93 @2022BouffaloLab

8.2 Electro-Static discharge（ESD）

HumanBody Model(HBM): 2000V
Charged-DeviceModel(CDM): 500V

8.3 Reflow Profile

Fordetails, please refer to IPC/JEDECJ-STD-020E. Fig.8.1: Classification Profile(Not to scale) BL808Datasheet 86/93 @2022BouffaloLab

Table8.2: Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly Preheat/Soak TemperatureMin(T smin) TemperatureMax(T smax) Time(ts)from (TsmintoTsmax) 100°C 150°C 60-120seconds 150°C 200°C 60-120seconds Ramp-uprate (TLtoTp) 3°C/second max. 3°C/second max. Liquidoustemperature (TL) Time(tL)maintained above TL 183°C 60-150seconds 217°C 60-150seconds Peakpackage body temperature (Tp) 240°C+0/-5 °C 250°C+0/-5 °C Time(tp)*within 5 °C of thespecified classificationtemperature (Tc) 10-30seconds 20-40seconds Ramp-downrate (TptoTL) 6°C/second max 6°C/second max Time25 °C to peak temperature 6minutes max 8minutes max -Tolerancefor peak profile temperature (Tp) isdefined as a supplier minimum anda user maximum. BL808Datasheet 87/93 @2022BouffaloLab

BL808Datasheet 88/93 @2022BouffaloLab

Fig.10.1: QFN88 Packagedrawing BL808Datasheet 89/93 @2022BouffaloLab

Table10.1: QFN88 Size Description SYMBOL UNIT OF MEASURE = MILLIMETER UNIT OF MEASURE = INCH SYMBOL MIN NOM MAX MIN NOM MAX A3 0.20REF 0.008REF e 0.40BSC 0.016BSC R 0.075 - 0.125 0.003 - 0.005 aaa 0.10 0.004 bbb 0.07 0.003 ccc 0.10 0.004 ddd 0.05 0.002 eee 0.08 0.003 fff 0.10 0.004 Note: Controlsize: millimeter BL808Datasheet 90/93 @2022BouffaloLab

I Temperature code: I/H I：-40°~85° H：-40°~105° BL808x09 Lot Number YYWW-AC Part number: BL808C:Wi-Fi+BT/BLE+Audio+Video+AI, IP Camera etc BL808D:Wi-Fi+BT/BLE+Audio+Video+AI, Visual Doorbell etc 00: MSB=ﬂash, 0: no flash, 1:2Mb, 2:4Mb, 3:8Mb, 4:16Mb, LSB=pSRAM, 0:no pSRAM, 1:2Mb, 2: 4Mb, 3:8Mb, 4:16Mb, 5:32Mb, 6:64Mb, 7:128Mb, 8:256Mb, 9:512Mb, A:1Gb, B:2Gb, C:4Gb, D:8Gb... Lot number Date code Fig.11.1: TopMarkingDefinition BL808Datasheet 91/93 @2022BouffaloLab

Ordering Information

BL808x- 09-Q2I(-xx) Package code: Q(QFN), B(BGA),CSP … Show in package Environment code : +=RoHS 0/6 , - = RoHS 5/6 , 1 =RoHS 6/6 , 2 = Green Temperature code : I /H Optional for special case Connectivity+Audio+Video MSB=flash, 0: no flash, 1:2Mb, 2: 4Mb, 3:8Mb, 4:16Mb, 5:32Mb, 6:64Mb, LSB=pSRAM, 0:no pSRAM, 1:2Mb, 2: 4Mb, 3:8Mb, 4:16Mb, 5:32Mb, 6:64Mb, 7:128Mb, 8:256Mb, 9:512Mb, A:1Gb, B:2Gb, C:4Gb, D:8Gb... Part number: BL808x-> BL808D: QFN88 Wi-Fi+BT/BLE+Audio+Video+AI, Visual Doorbell BL808C: QFN88 Wi-Fi+BT/BLE+Audio+Video+AI, IP Camera BL808Datasheet 92/93 @2022BouffaloLab

Revision history

Table13.1: Document revision history Date Revision Changes 2021/12/17 0.9 Initialrelease 2022/1/14 0.95 Addaudio characteristics and RF characteristics data 2022/2/10 0.96 AddBLE RF characteristics and electrical characteristics 2022/3/3 0.97 AddBT RF characteristics and Bootstrap pindescription 2022/3/17 0.98 Addpower consumption data 2022/5/12 0.99 Modifymemory map and add EMAC timingdescription 2022/6/9 1.0 Addpinmux function 26 and 27 2022/8/17 1.1 Addspi and uart function descriptions, andadd temperature descriptions BL808Datasheet 93/93 @2022BouffaloLab

Product Information

BL808 specifications and overview.

Summary

2.4 GHz RF transceiver Version: 1.1

Description

2.4 GHz RF transceiver Version: 1.1

Source title BL808 Datasheet(PDF) - Bouffalo Lab Intelligent Technology Co., Ltd.

Related Parts

More parts from the same family.

Browse manufacturer