BL702

BL702 BOUFFALOALB | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 47

Technical content

Datasheet sections

• 1 Overview
• 2 FunctionalDescription
• 2.1 CPU
• 2.2 Cache
• 2.3 Memory
• 2.4 DMA
• 2.5 Bus
• 2.6 Interrupt
• 2.7 Boot
• 2.8 Power
• 2.9 Clock
• 2.10 Peripherals
• 2.10.1 GPIO
• 2.10.2 UART
• 2.10.3 SPI
• 2.10.4 I2C
• 2.10.5 I2S
• 2.10.6 TIMER
• 2.10.7 PWM
• 2.10.8 IR(IR-remote)
• 2.10.10 EMAC
• 2.10.11 QDEC
• 2.10.12 ADC
• 2.10.13 DAC
• 2.10.14 Debuginterface

Version：2.0 Copyright @ 2021 www.bouffalolab.com

Features

• Wireless – 2.4GHz RF transceiver – Bluetooth®Specification v5.0 – Bluetooth®Low Energy 1Mbps and 2Mbps – Bluetooth®Long Range Coded 500Kbps and125Kbps – Zigbee 3.0, Base Device Behavior, Core Stack R21,Green Power – IEEE802.15.4 MAC/PHY – SupportBLE/zigbee coexistence – Integratedbalun, PA/LNA
• MCU Subsystem – 32-bitRISC CPU with FPU – Level-1cache – OneRTCtimer update to oneyear – Two32-bit general purpose timers – EightDMA channels – CPU frequency configurable from 1MHz to 144MHz – JTAGdevelopment support – XIP QSPI Flash/pSRAM with hardware encryp- tionsupport
• Memory – 132KBRAM – 192KBROM – 1KbeFuse – EmbeddedFlash (optional) – EmbeddedpSRAM (BL704/BL706,optional)
• Security – Secureboot – Securedebug ports – QSPIFlashOn-The-FlyAESDecryption(OTFAD) -AES-128, CTR+ mode – SupportAES 128/192/256 bits – SupportMD5, SHA-1/224/256/384/512 – Support TRNG (True Random Number Genera- tor) – SupportPKA (Public Key Accelerator)
• Peripheral – USB2.0FS (Full-Speed) device interface – IRremote control interface – OneSPI master/slave – TwoUARTs SupportISO 17987(Local Interconnect Network) – OneI2C master – OneI2S master/slave – FivePWM channels – Quadraturedecoder – Key-Scan-Matrixinterface – 12-bitgeneral ADC – 10-bitgeneral DAC – PIR(Passive Infra-Red) detection – EthernetRMII interface(BL704/BL706) – Camerainterface(BL706) BL702/704/706Datasheet 2/47 @2021BouffaloLab

– 15(BL702)/23(BL704)/31(BL706) Flexible GPIOs (flexible)

• Power Management – ActiveCPU – Idle – PowerDown Sleep (flexible) – Hibernate – Off – ActiveRx – ActiveTx
• Clock – Externalmain clock XTAL32MHz – External low power consumption and the RTC clockXTAL32/32.768kHz – InternalRC 32kHz oscillator – InternalRC 32MHz oscillator – InternalSystem PLL – InternalAudio PLL BL702/704/706Datasheet 3/47 @2021BouffaloLab

BL702/704/706Datasheet 5/47 @2021BouffaloLab

BL702/704/706Datasheet 6/47 @2021BouffaloLab

7.1 Reference Conditions for Drying Mounted or Unmounted SMD Packages (User Bake: Floor life be-

BL702/704/706Datasheet 7/47 @2021BouffaloLab

BL702/704/706Datasheet 8/47 @2021BouffaloLab

BL702/BL704/BL706is highly integrated BLE andzigbee combo chipsets for IoT applications. Wireless subsystem contains 2.4G radio, BLE+zigbee baseband and MAC designs. Microcontroller subsystem con- tains 32-bit RISC CPU, high-speed cache and memories. Power Management Unit controls ultra-low-power modes. Moreover,variety of security featuresare supported. Peripheral interfaces include USB2.0, Ethernet(BL704/BL706), IR-remote, SPI, UART, ISO 17987, I2C, I2S, PWM, QDEC,KeyScan, ADC, DAC, PIR, Camera(BL706),and GPIOs. USB host PMU Clock System PLL RC Clock XTAL DMA Crypto Engine USB2.0 UART Camera DVP (BL706) SPI I2C ISO 17987 IR remote PWM Timers eFuse QDEC KeyScan I2S DAC Camera Sensor 32-bit RISC CPU Cache / RAM / ROM RF Zigbee BLE Audio PLL XIP Flash Controller Flash pSRAM (BL704/BL706) pSRAM Ethernet I/F (BL704/BL706) RJ45 (10/100M) ADC PIR GPIO Car System HID Device Fig.1.1: Block Diagram BL702/704/706Datasheet 9/47 @2021BouffaloLab

BL702/BL704/BL706main functions described as follows： SPI RISC 32-bit CPU ROM Cache TCM UART Flash Control DMA Channels Crypto Engines Zigbee 3.0 BLE 5.0 USB2.0 QSPI USB x8 I2C PWM IR-Remote DAC ADC EINT GPIO General Pinmux GPIO eFUSE SYSRAM GLB REG PMU RTC Timer x6 RF Bus pSRAM pSRAM (BL704/BL706) I2S EMAC (BL704/BL706) QDEC KYS CAM (BL706) Fig.2.1: System Architecture BL702/704/706Datasheet 10/47 @2021BouffaloLab

2.1 CPU

BL702/BL704/BL706 32-bit RISC CPU contains FPU (floating-point unit) for 32-bit single-precision arithmetic, three- stage pipelined (IF, EXE, WB), compressed 16 and 32-bit instruction set, standard JTAG debugger port including 4 hardware-programmable breakpoints, interrupt controller including 64 interrupts and 16 interrupt levels/priorities for low latency interrupt processing. Up to 144MHz clock frequency, can be dynamically configured to change clock frequency,enter the power savingmode to achieve low power consumption. Both zigBee/BLE stack and application run on single 32-bit RISC CPU for simple and ultra-low power applications. CPUperformance ~1.46 DMIPS/MHz. ~3.1 CoreMark/MHz.

2.2 Cache

BL702/BL704/BL706cacheimprovesCPUperformancetoaccessexternalmemory. Cachememoriescanbepartially orfully configured as TCM (tightlycoupled memory).

2.3 Memory

BL702/BL704/BL706memoriesinclude: on-chipzero-delaySRAMmemories,read-onlymemories,write-oncememories, embeddedflash memory (optional), embedded pSRAM(BL704/BL706,optional).

2.4 DMA

BL702/BL704/BL706DMA(directmemoryaccess)controllerhaseightdedicatedchannelsthatmanagedatatransfer betweenperipherals and memories to improvecpu/bus efficiency. There are four main types of transfers including memory to memory, memory to peripheral, peripheral to peripheral andperipheraltomemory. DMAalsosupportsLLI(linklistitem)thatmultipletransfersarepre-definedbyaseriesof linkedlists,thenhardwareautomaticallycompletealltransfersaccordingtoeachLLIsizeandaddress. DMAsupports peripheralUSB, UART,I2C, I2S, SPI, ADCand DAC.

2.5 Bus

BL702/BL704/BL706bus fabric connection and memory-mapsummarized as follows： Table2.1: Bus Connectiom Slave/Master CPU Ethernet DMA Crypto Engine Debug SRAM V V V V V Peripheral V - V - V BLE/zigbee V - V - V BL702/704/706Datasheet 11/47 @2021BouffaloLab

Table2.2: Memory Map Module Base Address Size Description RETRAM 0x40010000 4KB Deepsleep memory (Retention RAM) HBN 0x4000F000 4KB Deepsleep control (Hibernate) PDS 0x4000E000 4KB Sleepcontrol (Power Down Sleep) USB 0x4000D800 1KB USBcontrol EMAC 0x4000D000 2KB EthernetMAC control (BL704/BL706) DMA 0x4000C000 4KB DMAcontrol QSPI 0x4000B000 4KB Flash/pSRAMQSPI control CAM 0x4000AD00 256B CAMcontrol (BL706) I2S 0x4000AA00 256B I2Scontrol KYS 0x4000A900 256B Key-Scancontrol QDEC2 0x4000A880 64B Quadraturedecoder control QDEC1 0x4000A840 64B Quadraturedecoder control QDEC0 0x4000A800 64B Quadraturedecoder control IRR 0x4000A600 256B IRRemote control TIMER 0x4000A500 256B Timercontrol PWM 0x4000A400 256B PulseWidth Modulation *5 control I2C 0x4000A300 256B I2Ccontrol SPI 0x4000A200 256B SPImaster/slave control UART1 0x4000A100 256B UARTcontrol (support ISO 17987) UART0 0x4000A000 256B UARTcontrol (support ISO 17987) L1C 0x40009000 4KB Cachecontrol eFuse 0x40007000 4KB eFusememory control SEC 0x40004000 4KB Securityengine GPIP 0x40002000 4KB Generalpurpose DAC/ADC/ACOMP interface control MIX 0x40001000 4KB Mixedsignal register GLB 0x40000000 4KB Globalcontrol register pSRAM 0x24000000 8MB pSRAMmemory XIP 0x23000000 8MB XIPFlash memory OCRAM 0x22020000 64KB On-chipmemory DTCM 0x22014000 48KB Datacache memory ITCM 0x22010000 16KB Instructioncache memory BL702/704/706Datasheet 12/47 @2021BouffaloLab

Table2.2: Memory Map Module Base Address Size Description ROM 0x21000000 192KB Read-onlymemory

2.6 Interrupt

BL702/BL704/BL706supports internal RTCwake-up andexternal GPIO interrupts wake-up. The CPU interrupt controller supports a total of 64 maskable interrupt trigger sources including UART interrupt, I2C interrupt, SPI interrupt, timer interrupt, DMA interrupt, etc. All I/O pins can be configured as external interrupt input mode. The external interrupt supports four trigger types: high level trigger, low level trigger, rising edge trigger and fallingedge trigger.

2.7 Boot

BL702/BL704/BL706supports multiple boot options: UART,USB, and Flash.

2.8 Power

PMU (power management unit) manages the power of the entire chip and is divided into running, idle, sleep, hiber- nationandpoweroffmodes. Thesoftwarecanbeconfiguredtoentersleepmodeandwake-upviaRTCtimerorEINTto achievelow-power sleep and accurate wake-upmanagement. Powerdown sleep modes are flexiblefor applications to configure as thelowest power consumption.

2.9 Clock

Clock control unit generates clocks to the core MCU and the peripheral SOC devices. The root clock source can be XTAL, PLL or RC oscillator. Dynamic power-saved by proper configurations such as sel, div, en, etc. PMU runs at 32KHzclock to keep system low-powerin sleep mode. BL702/704/706Datasheet 13/47 @2021BouffaloLab

57.6MHz 96MHz CG DIV hclk SOC fclk f32 k_clk CG PMU DIV uart clk (~2MHz) xclk DIV CG i2c clk DIV CG spi clk DIV CG general adc clk CG pwm clk RC32K XTAL32K DIV CG en 11bit f32k_sel RC32M clkpll_ xta l_ rc3 2 m _ s e l PLL xta l_ clk pll_en bclk_enbclk_div hclk_enhclk_div root_clk_sel[1] pll_sel sel sel sel 3bit 6bit 16bit 8bit 5bit en en en en en pir CG CG Cnt XTAL 32MHz 96MHz 72MHz DIV CG flash clk en 3bit sel DIV CG ir clk 6bit en CG gpdac clk (~512KHz)DIV sel en duty AUPLL 24.576MHz 32.768MHz CG i2s clk(~2MHz) en 32MHz DIV sel 5bit CG CG CG en en en kys clk(1MHz) qdec clk(1MHz) kys clk(128KHz) /2 usb clk(duty 50/50) en CG48MHz duty root_clk_sel[0] Fig.2.2: Clock Architecture

2.10 Peripherals

Peripherals include USB2.0, Ethernet, IR-remote, SPI, UART, ISO 17987, I2C, I2S, PWM, QDEC, KeyScan, ADC, DAC, PIR, Camera. Each peripheral can be assigned to different groups of GPIOs through flexible configurations. EachGPIO can be used asa general-purpose input and output function. BL702/704/706Datasheet 14/47 @2021BouffaloLab

2.10.1 GPIO

BL702 includes 15 GPIOs, BL704 includes 23 GPIOs, BL706 includes 31 GPIOs, and each GPIO can be used as a general-purposeinputandoutputfunction. Thepull-up/pull-down/floatingcanbeconfiguredbysoftware. EachGPIO supports interrupt function, interrupt supports rising edge trigger, falling edge trigger, high level trigger and low level trigger. EachGPIO can be set toa high impedance state for powersaving in low power consumption mode.

2.10.2 UART

Built-in 2 UARTs (UART0 and UART1), and support LIN master/slave function. The working clock of the UART modulecanbeselectedasFCLKor96M,andthemaximumbaudrateis8M.SupporthardwareCTSandRTSsignal management. TX and RXhave independent FIFOs with a FIFOdepth of 128 bytes and supportDMA functions.

2.10.3 SPI

One SPI interface, which can be configured as master mode or slave mode, and the SPI module clock is BCLK. As a master, the maximum SPI Clock can reach 36MHz. As a slave, the maximum SPI Clcok of the master is 24MHz. Thebit width of each framecan be configured as 8 bits/16bits/24 bits/32 bits. The transmission and reception of SPI has independent FIFO, and the FIFO depth is fixed to 4 frames (that is, if the bitwidth of the frame is8 bits, the depth of theFIFO is 4 bytes), and theDMA function is supported.

2.10.4 I2C

One I2C interface, support host mode and 7 bit addressing, I2C module clock is BCLK, support standard and fast mode. With device address register, register address register, the length of the register address can be configured as1 byte/2 bytes/3 bytes/4 bytes. TheI2C transceiver has an independentFIFO, the FIFO depth is 2words, and it supports DMA function.

2.10.5 I2S

OneI2Sinterface,supportLeft-justified/Right-justified/DSPandotherdataformats,support8/16/24/32bitdatawidth, inaddition to mono/dual-channel mode, supportfour-channel mode at the same time. The I2S transceiver has an independent FIFO, and the FIFO depth is 16 frames. When the data width is 16 bits, the FIFO depth can be set to 32 frames. The I2S module has an independent Audio PLL, and supports two types of samplingrates of 48K (and itsinteger frequency division) and 44.1K (andits integer frequency division). BL702/704/706Datasheet 15/47 @2021BouffaloLab

2.10.6 TIMER

The TIMER module contains two general-purpose timers and a watchdog timer. The clock source of the general- purposetimercanbeFCLK/32K/1K/XTAL,andtheclocksourceofthewatchdogtimercanbeFCLK/32K/XTAL.Each Thecounter has an 8-bit frequencydivider. Each group of general-purpose timers contains three compare registers, supports compare interrupts, and count modesupports FreeRun mode and PreLoadmode. The bit width of the watchdog timer counter is 16 bits, and it supports two watchdog overflow modes: interrupt and reset.

2.10.7 PWM

5-channelPWMinterface,threekindsofclocksourcesBCLK/XCLK/32Kcanbeselected,thebitwidthofthefrequency divider register is 16 bits, and the bit width of the period register is 16 bits. Supports adjustable output polarity and dualthresholdsettingstoincreasetheflexibilityofpulseoutput. SupportPWMcyclecountinginterrupt,usedtocount thenumber of output pulses, etc.

2.10.8 IR(IR-remote)

One infrared remote control, supports two modes of generating and receiving, supports receiving data with fixed protocolsNEC and RC-5, and alsosupports receiving data in any formatin pulse width counting mode. The IR module clock source is XCLK, which has powerful infrared waveform editing capabilities and can send out waveforms that conform to various protocols. The transmit power is adjustable in 15 levels, and the receive FIFO depthcan reach 64 bytes. 2.10.9 USB2.0(Full Speed) Built-in a device controller compatible with full-speed USB, following the full-speed USB device standard, with 8 endpoints,eachofwhichhasa64-bytedeepFIFO,exceptforendpoint0,allotherendpointssupportinterrupt/batch /synchronoustransmission. Withstandby/resumefunction. The48MHzclockdedicatedtoUSBisdirectlygenerated bythe internal main PLL.

2.10.10 EMAC

EMACis a 10/100Mbps Ethernet controller(Ethernet Media Access Controller) compatible withIEEE 802.3. Compatible with the MAC layer functions defined by IEEE 802.3, support the PHY of the RMII interface defined by IEEE 802.3, interact with the PHY through MDIO, support 10Mbps and 100Mbps Ethernet, support half-duplex and full-duplex,data transmission and reception arerealized through the BufferDescriptor datastructure . EMAC control is embedded with AHB Master, which can read or write data directly from the memory. The Buffer DescriptordatastructureisstoredintheinternalRAMofEMAC.ThetotalnumberofBufferDescriptorsisupto128. TheusercanflexiblyconfigurethenumberofBufferDescriptorsfortransmissionandreceivingaccordingtothescene. BL702/704/706Datasheet 16/47 @2021BouffaloLab

2.10.11 QDEC

Thechiphasbuilt-inthreesetsofquadraturedecoders,whichareusedtodecodethetwosetsofpulseswithaphase difference of 90 degrees generated by the dual-channel rotary encoder into the corresponding speed and rotation. Direction. QDECclocksourcecanbe32K(f32k_clk)or32M(xclk),with16-bitpulsecountrange(-32768~32767pulse/sample), with12configurablesampleperiods(32us~131mspersampleat1MHz)),witha16-bitsettablereportperiod(0~65535 ample/report).

2.10.12 ADC

The chip has a built-in 12bits successive approximation analog-to-digital converter (ADC) with a maximum working clockof2MHz,supports12externalanaloginputsandseveralinternalanalogsignalselections,andsupportssingle- channelconversion and multi-channel scanning modes. ADCcanworkintwomodesofsingleconversionandmulti-channelscanning. Itsupports2.0V,3.2Voptionalinternal referencevoltage, and the conversion resultis 12/14/16bits (achieved by oversampling) left-justifiedmode. TheADC has a FIFO witha depth of 32, supports avariety of interrupts, and supports DMAoperations. Inadditiontomeasuringcommonanalogsignals,ADCcanalsobeusedtomeasurepowersupplyvoltage. Inaddition, ADCcan also be used fortemperature detection by measuring internal/external diodevoltage.

2.10.13 DAC

The chip has a built-in 10bits digital-to-analog converter (DAC) with a FIFO depth of 1 word and supports 2 DAC modulationoutputs. Canbeusedforaudioplayback,conventionalanalogsignalmodulation,DACinputclockcanbe selected as 32M or Audio PLL, support DMA to transfer memory to the DAC modulation register, DAC output pin is fixedto ChannelA to GPIO11,ChannelB to GPIO17.

2.10.14 Debug interface

Support standard JTAG 4-wire debugging interface, and use debuggers such as Jlink/OpenOCD/CK Link for debug- ging. BL702/704/706Datasheet 17/47 @2021BouffaloLab

BL70232-pin package includes 11power pins, 6 analog pins, and15 flexible GPIO pins. PAD_GPIO_0 PAD_GPIO_1 16 15 1413 1211 DCDC_OUT VDDCORE VDDBUS_USB PAD_GPIO_8 PAD_GPIO_7 PAD_GPIO_2 10 9 VDDIO_1 QFN32 (15GPIOs) SW_DCDC VDDIO_2 PAD_GPIO_9 XTAL32K_IN XTAL32K_OUT AVDD33_AON PU_CHIP ANT VDDIO_3 PAD_GPIO_23 PAD_GPIO_24 PAD_GPIO_25 PAD_GPIO_26 PAD_GPIO_28 VDDIO_1 PAD_GPIO_27 PAD_GPIO_17 PAD_GPIO_15 AVDD33_PA AVDD15 XTAL_HF_IN XTAL_HF_OUT PAD_GPIO_14 1.8V or 3.3V 3.3V GPIO0-8 / GPIO23-31 GPIO9-13 GPIO14-22/GPIO32-37(Embedded PSRAM) 28 27 26 25 32 31 30 29 1.8V or 3.3V VDDIO_3 VDDIO_2 AVDD_RF Fig.3.1: Pin layout(QFN32) BL70440-pin package includes 11power pins, 6 analog pins, and23 flexible GPIO pins. BL702/704/706Datasheet 18/47 @2021BouffaloLab

VDDIO_1 PAD_GPIO_0 18 17 16 151413 VDDBUS_USB PAD_GPIO_8 PAD_GPIO_7 PAD_GPIO_3 PAD_GPIO_2 PAD_GPIO_1 12 11 VDDIO_1 QFN40 (23GPIOs) ANT AVDD15 PU_CHIP XTAL32K_IN XTAL32K_OUT AVDD33_AON VDDCORE PAD_GPIO_23 PAD_GPIO_24 PAD_GPIO_25 PAD_GPIO_26 PAD_GPIO_21 PAD_GPIO_22 PAD_GPIO_27 PAD_GPIO_15 PAD_GPIO_9 PAD_GPIO_10 PAD_GPIO_11 PAD_GPIO_28 PAD_GPIO_17 PAD_GPIO_14 36 35 34 33 40 39 38 37 AVDD33_PA XTAL_HF_OUT XTAL_HF_IN DCDC_OUT SW_DCDC 32 31 20 19 VDDIO_2 PAD_GPIO_18 PAD_GPIO_20 PAD_GPIO_19 VDDIO_3 VDDIO_3 VDDIO_2 1.8V or 3.3V GPIO0-8 / GPIO23-31 GPIO9-13 GPIO14-22/GPIO32-37(Embedded PSRAM)1.8V or 3.3V 3.3V AVDD_RF Fig.3.2: Pin layout(QFN40) BL70648-pin package includes 11power pins, 6 analog pins, and31 flexible GPIO pins. BL702/704/706Datasheet 19/47 @2021BouffaloLab

VDDIO_1 PAD_GPIO_0 20 19 18 171615 VDDBUS_USB PAD_GPIO_8 PAD_GPIO_7 PAD_GPIO_3 PAD_GPIO_2 PAD_GPIO_1 14 13 VDDIO_1 QFN48 (31GPIOs) PU_CHIP XTAL32K_IN XTAL32K_OUT AVDD33_AON VDDCORE PAD_GPIO_23 PAD_GPIO_24 PAD_GPIO_25 PAD_GPIO_26 PAD_GPIO_29 PAD_GPIO_22 PAD_GPIO_27 PAD_GPIO_15 PAD_GPIO_9 PAD_GPIO_10 PAD_GPIO_11 PAD_GPIO_28 PAD_GPIO_17 PAD_GPIO_14 44 43 42 41 48 47 46 45 XTAL_HF_OUT 28 XTAL_HF_IN 27 SW_DCDC 40 39 22 21 VDDIO_2 PAD_GPIO_18 PAD_GPIO_20 PAD_GPIO_19 VDDIO_3 VDDIO_2 1.8V or 3.3V GPIO0-8 / GPIO23-31 GPIO9-13 GPIO14-22/GPIO32-37(Embedded PSRAM)1.8V or 3.3V 3.3V

12 DCDC_OUT AVDD15

AVDD33_PA 24 23 PAD_GPIO_21 38 37 PAD_GPIO_6 PAD_GPIO_5 PAD_GPIO_4 PAD_GPIO_12 PAD_GPIO_16 VDDIO_3 PAD_GPIO_31 PAD_GPIO_30 AVDD_RF Fig.3.3: Pin layout(QFN48) Table3.1: Pin description No VoltageDomain BL702 BL704 BL706 I/OType PinName Description

1 VDDIO_1 1 1 1 DI/DO PAD_GPIO_0 -

2 VDDIO_1 2 2 2 DI/DO PAD_GPIO_1 -

3 VDDIO_1 3 3 3 DI/DO PAD_GPIO_2 -

4 VDDIO_1 - 4 4 DI/DO PAD_GPIO_3 -

5 VDDIO_1 - - 5 DI/DO PAD_GPIO_4 -

6 VDDIO_1 - - 6 DI/DO PAD_GPIO_5 -

7 VDDIO_1 - - 7 DI/DO PAD_GPIO_6 -

8 VDDIO_1 4 5 8 DI/DO PAD_GPIO_7 -

9 VDDIO_1 5 6 9 DI/DO PAD_GPIO_8 -

10 VDDIO_2 11 12 15 DI/DO PAD_GPIO_9 -

11 VDDIO_2 - 13 16 DI/DO PAD_GPIO_10 -

12 VDDIO_2 - 14 17 DI/DO PAD_GPIO_11 -

13 VDDIO_2 - - 18 DI/DO PAD_GPIO_12 -

BL702/704/706Datasheet 20/47 @2021BouffaloLab

Table3.1: Pin description No VoltageDomain BL702 BL704 BL706 I/OType PinName Description

14 VDDIO_3 22 25 29 DI/DO PAD_GPIO_14 -

15 VDDIO_3 23 26 30 DI/DO PAD_GPIO_15 -

16 VDDIO_3 - - 31 DI/DO PAD_GPIO_16 -

17 VDDIO_3 24 27 32 DI/DO PAD_GPIO_17 -

18 VDDIO_3 - 28 33 DI/DO PAD_GPIO_18 -

19 VDDIO_3 - 29 34 DI/DO PAD_GPIO_19 -

20 VDDIO_3 - 30 35 DI/DO PAD_GPIO_20 -

21 VDDIO_3 - 32 37 DI/DO PAD_GPIO_21 -

22 VDDIO_3 - 33 38 DI/DO PAD_GPIO_22 -

23 VDDIO_1 26 34 39 DI/DO PAD_GPIO_23 -

24 VDDIO_1 27 35 40 DI/DO PAD_GPIO_24 -

25 VDDIO_1 28 36 41 DI/DO PAD_GPIO_25 -

26 VDDIO_1 29 37 42 DI/DO PAD_GPIO_26 -

27 VDDIO_1 30 38 43 DI/DO PAD_GPIO_27 -

28 VDDIO_1 31 39 44 DI/DO PAD_GPIO_28 -

29 VDDIO_1 - - 45 DI/DO PAD_GPIO_29 -

30 VDDIO_1 - - 46 DI/DO PAD_GPIO_30 -

31 VDDIO_1 - - 47 DI/DO PAD_GPIO_31 -

32 VDDIO_3 - - - DI/DO PAD_GPIO_32 -

33 VDDIO_3 - - - DI/DO PAD_GPIO_33 -

34 VDDIO_3 - - - DI/DO PAD_GPIO_34 -

35 VDDIO_3 - - - DI/DO PAD_GPIO_35 -

36 VDDIO_3 - - - DI/DO PAD_GPIO_36 -

37 VDDIO_3 - - - DI/DO PAD_GPIO_37 -

38 AVDD33_AON 12 15 19 Analog XTAL32K_IN Crystaloscillator 32.768kHz input 39 AVDD33_AON 13 16 20 Analog XTAL32K_OUT Crystaloscillator 32.768kHz output

40 AVDD33_AON 20 23 27 Analog XTAL_HF_IN Externalcrystal input, 32MHz

41 AVDD33_AON 21 24 28 Analog XTAL_HF_OUT Externalcrystal output, 32MHz

42 AVDD33_AON 15 18 22 Analog PU_CHIP Chippower-up

43 AVDD15 16 19 23 Analog ANT RFinput and output (single pin)

44 - 32 40 48 Power VDDIO_1 Externallypowered 3.3V or 1.8V 45 - 10 11 14 Power VDDIO_2 Externallypowered 3.3V 46 - 25 31 36 Power VDDIO_3 Externallypowered 3.3V or 1.8V 47 - 14 17 21 Power AVDD33_AON Externallypowered 3.3V 48 - 17 20 24 Power AVDD33_PA Externallypowered 3.3V 49 - 19 22 26 Power AVDD_RF Externallypowered 3.3/1.8/1.5V BL702/704/706Datasheet 21/47 @2021BouffaloLab

Table3.1: Pin description No VoltageDomain BL702 BL704 BL706 I/OType PinName Description 50 - 18 21 25 Power AVDD15 InternalLDO output (for internal useonly) 51 - 9 10 13 Power SW_DCDC DCDCpower 1.8V 52 - 8 9 12 Power DCDC_OUT DCDCpower 1.8V 53 - 6 7 10 Power VDDBUS_USB USBpower 54 - 7 8 11 Power VDDCORE InternalLDO output (for internal useonly) BL702/704/706Datasheet 22/47 @2021BouffaloLab

Table3.2: GPIO Muxed Pins PinName Flash1 I2S SPI (Default /SWAP=1) CAM UART2 (Default /SWAP=1) I2C Master PWM Analog External_PA JTAG (Default /SWAP=1) Ether_Mac QDEC Key_Scan_In Key_Scan_Drive IR PAD_GPIO_0 - BCLK MOSI /MISO PIX_CLK SIG0 /SIG4 SCL PWM_CH0 - FEM0 TMS/TCK MII_REF_CLK QDEC0_a ROW0 COL0 - PAD_GPIO_1 - FS MISO /MOSI FRAME_VLD SIG1 /SIG5 SDA PWM_CH1 - FEM1 TDI/TDO MII_TXD[0] QDEC0_b ROW1 COL1 - PAD_GPIO_2 - DIO/DO SS LINE_VLD SIG2 /SIG6 SCL PWM_CH2 - FEM2 TCK/TMS MII_TXD[1] QDEC0_led ROW2 COL2 - PAD_GPIO_3 - RCLK_O /DI SCLK PIX_DAT0 SIG3 /SIG7 SDA PWM_CH3 - FEM3 TDO/TDI - QDEC1_a ROW3 COL3 - PAD_GPIO_4 - BCLK MOSI /MISO PIX_DAT1 SIG4 /SIG0 SCL PWM_CH4 - FEM4 TMS/TCK - QDEC1_b ROW4 COL4 - PAD_GPIO_5 - FS MISO /MOSI PIX_DAT2 SIG5 /SIG1 SDA PWM_CH0 - FEM0 TDI/TDO - QDEC1_led ROW5 COL5 - PAD_GPIO_6 - DIO/DO SS PIX_DAT3 SIG6 /SIG2 SCL PWM_CH1 - FEM1 TCK/TMS - QDEC2_a ROW6 COL6 - PAD_GPIO_7 - RCLK_O /DI SCLK - SIG7 /SIG3 SDA PWM_CH2 USB_- DP/ADC_- CH6 FEM2 TDO/TDI MII_RXD[0] QDEC2_b ROW7 COL7 - PAD_GPIO_8 - BCLK MOSI /MISO - SIG0 /SIG4 SCL PWM_CH3 USB_- DM/ADC_- CH0 FEM3 TMS/TCK MII_RXD[1] QDEC2_led ROW0 COL8 - PAD_GPIO_9 - FS MISO /MOSI - SIG1 /SIG5 SDA PWM_CH4 ADC_CH7 FEM4 TDI/TDO - QDEC0_a ROW1 COL9 - PAD_GPIO_10 - DIO/DO SS - SIG2 /SIG6 SCL PWM_CH0 MICBIAS FEM0 TCK/TMS - QDEC0_b ROW2 COL10 - PAD_GPIO_11 - RCLK_O /DI SCLK - SIG3 /SIG7 SDA PWM_CH1 ADC_CH3 FEM1 TDO/TDI - QDEC0_led ROW3 COL11 - PAD_GPIO_12 - BCLK MOSI /MISO PIX_DAT4 SIG4 /SIG0 SCL PWM_CH2 ADC_CH4 FEM2 TMS/TCK - QDEC1_a ROW4 COL12 - PAD_GPIO_13 - FS MISO /MOSI - SIG5 /SIG1 SDA PWM_CH3 - FEM3 TDI/TDO - QDEC1_b ROW5 COL13 - PAD_GPIO_14 - DIO/DO SS - SIG6 /SIG2 SCL PWM_CH4 ADC_CH5 FEM4 TCK/TMS - QDEC1_led ROW6 COL14 - PAD_GPIO_15 - RCLK_O /DI SCLK - SIG7 /SIG3 SDA PWM_CH0 ADC_CH1 FEM0 TDO/TDI - QDEC2_a ROW7 COL15 - PAD_GPIO_16 - BCLK MOSI /MISO - SIG0 /SIG4 SCL PWM_CH1 - FEM1 TMS/TCK - QDEC2_b ROW0 COL16 - PAD_GPIO_17 SF1_IO0 /SF2_CS2 FS MISO /MOSI PIX_DAT4 SIG1 /SIG5 SDA PWM_CH2 ADC_- CH2/psw_- irrcv FEM2 TDI/TDO - QDEC2_led ROW1 COL17 IRRX (ir_rx_gpio_sel=1) PAD_GPIO_18 SF1_IO1 DIO/DO SS PIX_DAT5 SIG2 /SIG6 SCL PWM_CH3 ADC_CH8 FEM3 TCK/TMS RMII_MDC QDEC0_a ROW2 COL18 IRRX (ir_rx_gpio_sel=2) PAD_GPIO_19 SF1_CS RCLK_O /DI SCLK PIX_DAT6 SIG3 /SIG7 SDA PWM_CH4 ADC_CH9 FEM4 TDO/TDI RMII_MDIO QDEC0_b ROW3 COL19 IRRX (ir_rx_gpio_sel=3) PAD_GPIO_20 SF1_IO3 BCLK MOSI /MISO PIX_DAT7 SIG4 /SIG0 SCL PWM_CH0 ADC_CH10 FEM0 TMS/TCK RMII_RXERR QDEC0_led ROW4 COL0 IRRX (ir_rx_gpio_sel=4) PAD_GPIO_21 SF1_CLK FS MISO /MOSI - SIG5 /SIG1 SDA PWM_CH1 ADC_CH11 FEM1 TDI/TDO RMII_TX_EN QDEC1_a ROW5 COL1 IRRX (ir_rx_gpio_sel=5) BL702/704/706Datasheet 23/47 @2021BouffaloLab

Table3.2: GPIO Muxed Pins PinName Flash1 I2S SPI (Default /SWAP=1) CAM UART2 (Default /SWAP=1) I2C Master PWM Analog External_PA JTAG (Default /SWAP=1) Ether_Mac QDEC Key_Scan_In Key_Scan_Drive IR PAD_GPIO_22 SF1_IO2 DIO/DO SS - SIG6 /SIG2 SCL PWM_CH2 IRTX FEM2 TCK/TMS RMII_RX_DV QDEC1_b ROW6 COL2 IRRX (ir_rx_gpio_sel=6) PAD_GPIO_23 SF2_IO2 RCLK_O /DI SCLK PIX_DAT4 SIG7 /SIG3 SDA PWM_CH3 IRTX FEM3 TDO/TDI - QDEC1_led ROW7 COL3 IRRX (ir_rx_gpio_sel=7) PAD_GPIO_24 SF2_IO1 BCLK MOSI /MISO PIX_DAT5 SIG0 /SIG4 SCL PWM_CH4 - FEM4 TMS/TCK RMII_MDC QDEC2_a ROW0 COL4 IRRX (ir_rx_gpio_sel=8) PAD_GPIO_25 SF2_CS FS MISO /MOSI PIX_DAT6 SIG1 /SIG5 SDA PWM_CH0 - FEM0 TDI/TDO RMII_MDIO QDEC2_b ROW1 COL5 IRRX (ir_rx_gpio_sel=9) PAD_GPIO_26 SF2_IO3 DIO/DO SS PIX_DAT7 SIG2 /SIG6 SCL PWM_CH1 - FEM1 TCK/TMS RMII_RXERR QDEC2_led ROW2 COL6 IRRX (ir_rx_gpio_sel=10) PAD_GPIO_27 SF2_CLK RCLK_O /DI SCLK - SIG3 /SIG7 SDA PWM_CH2 - FEM2 TDO/TDI RMII_TX_EN QDEC0_a ROW3 COL7 IRRX (ir_rx_gpio_sel=11) PAD_GPIO_28 SF2_IO0 BCLK MOSI /MISO PIX_DAT4 SIG4 /SIG0 SCL PWM_CH3 - FEM3 TMS/TCK RMII_RX_DV QDEC0_b ROW4 COL8 IRRX (ir_rx_gpio_sel=12) PAD_GPIO_29 - FS MISO /MOSI PIX_DAT5 SIG5 /SIG1 SDA PWM_CH4 - FEM4 TDI/TDO - QDEC0_led ROW5 COL9 IRRX (ir_rx_gpio_sel=13) PAD_GPIO_30 - DIO/DO SS PIX_DAT6 SIG6 /SIG2 SCL PWM_CH0 - FEM0 TCK/TMS - QDEC1_a ROW6 COL10 IRRX (ir_rx_gpio_sel=14) PAD_GPIO_31 - RCLK_O /DI SCLK PIX_DAT7 SIG7 /SIG3 SDA PWM_CH1 - FEM1 TDO/TDI - QDEC1_b ROW7 COL11 IRRX (ir_rx_gpio_sel=15) 1 Thereare 2 groups of Flash, andthe smallest selection unit is group,which is configured according to groupwhen used. InDual CS mode, PAD_GPIO_17canbe configured as SF2_CS2 function. 2 Thedefault UARTsignal mapping tableis shown below. BL702/704/706Datasheet 24/47 @2021BouffaloLab

Table3.3: UARTSignal Mapping(Default) UARTSignal uart_sig_x_sel MappingSignal UART_SIG0 uart_sig_0_sel=0 UART0_RTS UART_SIG1 uart_sig_1_sel=1 UART0_CTS UART_SIG2 uart_sig_2_sel=2 UART0_TXD UART_SIG3 uart_sig_3_sel=3 UART0_RXD UART_SIG4 uart_sig_4_sel=4 UART1_RTS UART_SIG5 uart_sig_5_sel=5 UART1_CTS UART_SIG6 uart_sig_6_sel=6 UART1_TXD UART_SIG7 uart_sig_7_sel=7 UART1_RXD Note: UART_SIG0-UART_SIG7 can be configured as any of 8 Mapping Signals. For example: UART_SIG0 can alsobe configured as UART_RXD.Thespecific signal mapping example is shownin the table below. Table3.4: UARTSignal Mapping(Example) UARTSignal uart_sig_x_sel MappingSignal UART_SIG0 uart_sig_0_sel=7 UART1_RXD UART_SIG1 uart_sig_1_sel=6 UART1_TXD UART_SIG2 uart_sig_2_sel=5 UART1_CTS UART_SIG3 uart_sig_3_sel=4 UART1_RTS UART_SIG4 uart_sig_4_sel=3 UART0_RXD UART_SIG5 uart_sig_5_sel=2 UART0_TXD UART_SIG6 uart_sig_6_sel=1 UART0_CTS UART_SIG7 uart_sig_7_sel=0 UART0_RTS BL702/704/706Datasheet 25/47 @2021BouffaloLab

RFCharacteristics of Receiving and Transmittingmodes. Table4.1: RX RF Characteristics Mode Note Performance@25◦C Mode Note Min. Typ Max. Unit ZigbeeSensitivity 250Kbps -104 dBm BLESensitivity 125Kbps -104 -98 500Kbps -100 -97 1Mbps -97 -94 2Mbps -94 -92 Table4.2: TX RF Characteristics Mode Note Performance@25◦C Mode Note Min. Typ Max. Unit TXPower 0-14 dBm TXEVM 11 13 % BL702/704/706Datasheet 26/47 @2021BouffaloLab

PowerConsumption of each power mode. Table5.1: Power Modes &Whole-chip Current Symbol Parameter Conditions Performance @25◦CSymbol Parameter Conditions Typ Unit RX RFonly 3.5 mA TX 0dBm RFonly 4.8 10dBm RFonly 17 14dBm RFonly 45 Idd RunMode (Runin RAM) AllPeripherals clock ON Runwhile(1) RC32Mto PLL cpuclk=144MHz peripheralclk=72MHz 16.70 mA RC32Mto PLL cpuclk=96MHz peripheralclk=48MHz 12.11 RC32M cpuclk=32MHz peripheralclk=32MHz 7.03 AllPeripherals clock OFF Runwhile(1) RC32Mto PLL cpuclk=144MHz peripheralclk=72MHz 8.44 RC32Mto PLL cpuclk=96MHz peripheralclk=48MHz 6.43 RC32M cpuclk=32MHz peripheralclk=32MHz 3.36 Idd RunMode (Runin FLASH) AllPeripherals clock ON Runwhile(1) RC32Mto PLL cpuclk=144MHz peripheralclk=72MHz 15.86 mA RC32Mto PLL cpuclk=96MHz peripheralclk=48MHz 11.52 RC32M cpuclk=32MHz peripheralclk=32MHz 6.87 AllPeripherals clock OFF Runwhile(1) RC32Mto PLL cpuclk=144MHz peripheralclk=72MHz 7.72 RC32Mto PLL cpuclk=96MHz peripheralclk=48MHz 6.01 RC32M cpuclk=32MHz peripheralclk=32MHz 3.39 BL702/704/706Datasheet 27/47 @2021BouffaloLab

Table5.1: Power Modes &Whole-chip Current Symbol Parameter Conditions Performance @25◦CSymbol Parameter Conditions Typ Unit Idd IdleMode (WFI) AllPeripherals clock ON codein RAM RC32Mto PLL cpuclk=144MHz peripheralclk=72MHz 13.69 mA RC32Mto PLL cpuclk=96MHz peripheralclk=48MHz 10.13 RC32M cpuclk=32MHz peripheralclk=32MHz 6.45 AllPeripherals clock OFF codein RAM RC32Mto PLL cpuclk=144MHz peripheralclk=72MHz 5.43 RC32Mto PLL cpuclk=96MHz peripheralclk=48MHz 4.44 RC32M cpuclk=32MHz peripheralclk=32MHz 2.72 Idd IdleMode (WFI) AllPeripherals clock ON codein FLASH RC32Mto PLL cpuclk=144MHz peripheralclk=72MHz 13.66 mA RC32Mto PLL cpuclk=96MHz peripheralclk=48MHz 10.10 RC32M cpuclk=32MHz peripheralclk=32MHz 6.43 AllPeripherals clock OFF codein FLASH RC32Mto PLL cpuclk=144MHz peripheralclk=72MHz 5.58 RC32Mto PLL cpuclk=96MHz peripheralclk=48MHz 4.60 RC32M cpuclk=32MHz peripheralclk=32MHz 2.89 Idd LPMode (PDS) Level=0 ON:HBNdomain,PD_CORE,MISC,CPU,BZ,USB 170 uA Level=1 ON:HBNdomain,PD_CORE,MISC,CPU,BZ 165 Level=2 ON:HBNdomain,PD_CORE,MISC,CPU,USB 135 Level=3 ON:HBNdomain,PD_CORE,MISC,CPU 129 Level=4 ON:HBNdomain,PD_CORE,MISC,BZ,USB 149 Level=5 ON:HBNdomain,PD_CORE,MISC,BZ 144 Level=6 ON:HBNdomain,PD_CORE,MISC,USB 113 Level=7 ON:HBNdomain,PD_CORE,MISC 108 Level=31 ON:HBNdomain,PD_CORE 10 Idd HibernateMode (HBN) Level=0 4KBRAM retention + RTC+GPIO wakeup 1.8 uA Level=1 RTC+ GPIO wakeup 1.5 Level=2 GPIOwakeup 1.2 Shut-down 0.1 BL702/704/706Datasheet 28/47 @2021BouffaloLab

Note: 1. AllOCRAM in LP Mode canenter the retention state 2. MISCincludes: DMA, EF,GLB,GPIO_MUX, GPIP,I2C, IRR, PWM, SEC,SPI, TMR, UART 3. BZincludes: BLE, zigbee 4. BecauseMISCincludesGLBandGPIO_MUX,afterthispowerdomainispowereddown,thefunctionsconfigured throughGLB register and GPIO registerare all invalid BL702/704/706Datasheet 29/47 @2021BouffaloLab

6.1 Absolute Maximum Rating

Table6.1: AbsoluteMaximum Rating PinName Min. Max. Unit VDDIO_1 -0.3 3.63 V VDDIO_2 -0.3 3.63 V VDDIO_3 -0.3 3.63 V VSSBUS_USB -0.3 5.5 V AVDD33_AON -0.3 3.63 V AVDD33_PA -0.3 3.63 V AVDD33_RF -0.3 3.63 V ESDProtection(HBM) 2000 V StorageTemperature -40 125 ◦C

6.2 Operating Condition

BL702/704/706Datasheet 30/47 @2021BouffaloLab

6.2.1 Power characteristics

Table6.2: RecommendedPower Operating Range PinName Min. Typ Max. Unit VDDIO_2 1.8 3.3 3.63 V VDDIO_3 1.8 3.3 3.63 V VDDBUS_USB 4.5 5 5.5 V AVDD33_AON 1.8 3.3 3.63 V

6.2.2 Temperature sensor characteristics

Table6.3: RecommendedTemperatureOperating Range Item Min. Max. Unit Temperature MainDie -40 105 ◦C Multi-DieSiP -40 85 ◦C

6.2.3 General operating conditions

Table6.4: GeneralOperating Conditions Item Description Min. Typ Max. Unit FCPU CPU/TCM/Cache clockfrequency 0 32 144 MHz FSYS Systemclock frequency 0 32 72 MHz

6.2.4 GPADC characteristics

BL702/704/706Datasheet 31/47 @2021BouffaloLab

Table6.5: GPADCcharacteristics Symbol Parameter Conditions Min Typ Max Units VDD33 Vbatsupply voltage 2.3 3.6 V T Workingtempreture -40 125 ◦C Ivdd33 Currentconsumption of ADCon VDD33 PGA1&2off(2M clock) 150 μA PGA1&2on(2M clock) 350 Fclk ADCinput top clock frequency Clockfrom SOC 1.5 32 MHz Fsample Samplingrate 2.048M(12bitmode) 32K-128K(14bitmode) 8K-16K(16bitmode)

2 MHz

Differentialmode 6.4 V(vpp) Single-endedmode 3.2 Rin Totalinputchannel resistance 2 KΩ Tcal Calibrationtime Fsample=2M(16bit mode) 140 uS Tpu Powerup time 1 uS Tconv Totalconversion time 12bitmode 1 1/Fsample 14bitmode 1 16 14bitmode 2 64 16bitmode 3 128 16bitmode 4 256 1. 14-bitmode with 16 times average 2. 14-bitmode with 64 times average 3. 16-bitmode with 128 times average 4. 16-bitmode with 256 times average Note: Unlessotherwisespecified,theparametersgiveninTable1arederivedfromtestunder-40to125oC,supply AVDD=3.3V,DVDD=1.1V. BL702/704/706Datasheet 32/47 @2021BouffaloLab

Table6.6: ADCelectrical characteristic Symbol Parameter Conditions Min Typ Max Units DNL1 Differentiallinearity error +/-1 LSB INL1 Integrallinearity error +/-2 LSB Offset Inputoffset +/-2 LSB Ge1&2 Gainerror +/-1 % ENOB Effectivenumber of bits 12bitmode(201KHz input) 9.7 10.5 bit14bitmode(2.5KHz input) 10.8 11.4 16bitmode(1KHz input) 11.5 12.3 SNDR Signal-to-noise-distortion (PGAon) 12bitmode(201KHz input) 59 65 dB14bitmode(2.5KHz input) 66 72.4 16bitmode(1KHz input) 71 76.8 SNDR Signal-to-noise-distortion (PGAgain=4) 12bitmode(201KHz input) 58 64 dB14bitmode(2.5KHz input) 64 69.5 16bitmode(1KHz input) 70 74 1. moretest needed 2. aftercalibration BL702/704/706Datasheet 33/47 @2021BouffaloLab

7.1 Moisture Sensitivity Level(MSL)

Themoisturesensitivitylevelofthechipis: MSL3. Afterthevacuumpackageisopened,itneedstobeusedupwithin 168hours (7 days) at ≤30°C/60%RH,otherwise it needs to be bakedand put online. Forbaking temperature and time, pleaserefer to IPC/JEDECJ-STD-033B01. Table7.1: Reference Conditionsfor Drying Mounted or Unmounted SMDPackages (UserBake: Floor lifebegins counting at time = 0after bake) PackageBody Level Bake@ 125°C Bake@ 90°C Bake@ 40°C Bake@ 125°C ≤5%RH ≤5%RH Exceeding Exceeding Exceeding Exceeding Exceeding Exceeding FloorLife FloorLife FloorLife FloorLife FloorLife FloorLife PackageBody Level by>72 h by≤72 h by>72 h by≤72 h by>72 h by≤72 h Thickness≤1.4 mm 2 5hours 3hours 17hours 11hours 8days 5days 2a 7hours 5hours 23hours 13hours 9days 7days 3 9hours 7hours 33hours 23hours 13days 9days 4 11hours 7hours 37hours 23hours 15days 9days 5 12hours 7hours 41hours 24hours 17days 10days 5a 16hours 10hours 54hours 24hours 22days 10days BL702/704/706Datasheet 34/47 @2021BouffaloLab

7.2 Electro-Static discharge（ESD）

• HumanBody Model(HBM): 2000V
• Charged-DeviceModel(CDM): 500V

7.3 Reflow Profile

Fordetails, please refer to IPC/JEDECJ-STD-020E. Fig.7.1: Classification Profile(Not to scale) BL702/704/706Datasheet 35/47 @2021BouffaloLab

Table7.2: Classification Reflow Profiles ProfileFeature Sn-PbEutectic Assembly Pb-FreeAssembly Preheat/Soak TemperatureMin(T smin) 100°C 150°C TemperatureMax(T smax) 150°C 200°C Time(ts)from (TsmintoTsmax) 60-120seconds 60-120seconds Ramp-uprate (TLtoTp) 3°C/second max. 3°C/second max. Liquidoustemperature (TL) 183°C 217°C Time(tL)maintained above TL 60-150seconds 60-150seconds Peakpackage body temperature (Tp) 240°C+0/-5 °C 250°C+0/-5 °C Time(tp)*within 5 °C of thespecified 10-30seconds 20-40seconds classificationtemperature (Tc) Ramp-downrate (TptoTL) 6°C/second max 6°C/second max Time25 °C to peak temperature 6minutes max 8minutes max -Tolerancefor peak profile temperature (Tp) isdefined as a supplier minimum anda user maximum. BL702/704/706Datasheet 36/47 @2021BouffaloLab

32MHz 32.768kHz Antenna ANT 3.3V 15/23/31x GPIO XTAL32K_OUTXTAL32K_INXTAL_IN XTAL_OUT 1.8V or 3.3V CHIP_EN AVDD15_RF AVDD18_RF VDD33 VDDIO_3 AVDD33_2 AVDD33_1 VDDIO_2 GPIOs VDDCORE SW_DCDC DCDC_OUT 1.8V or 3.3V VDDIO_1 Fig.8.1: Reference Design BL702/704/706Datasheet 37/47 @2021BouffaloLab

Fig.9.1: QFN32 Packagedrawing Table9.1: QFN32 Size Description(UnitsOf Measure=Millimeter) SYMBOL MIN NOM MAX A 0.70 0.75 0.80 A1 0.00 0.02 0.05 BL702/704/706Datasheet 38/47 @2021BouffaloLab

Table9.1: QFN32 Size Description(UnitsOf Measure=Millimeter) SYMBOL MIN NOM MAX A2 0.50 0.55 0.60 A3 0.20REF b 0.15 0.20 0.25 D 3.90 4.00 4.10 E 3.90 4.00 4.10 D2 2.80 2.90 3.00 E2 2.80 2.90 3.00 e 0.30 0.40 0.50 H 0.30REF K 0.25REF L 0.25 0.30 0.35 R 0.09 - - c1 - 0.10 - c2 - 0.10 - BL702/704/706Datasheet 39/47 @2021BouffaloLab

Fig.10.1: QFN40 Packagedrawing Table10.1: QFN40 Size Description(UnitsOf Measure=Millimeter) SYMBOL MIN NOM MAX A 0.80 0.85 0.90 A1 0 0.02 0.05 BL702/704/706Datasheet 40/47 @2021BouffaloLab

Table10.1: QFN40 Size Description(UnitsOf Measure=Millimeter) SYMBOL MIN NOM MAX A2 0.60 0.65 0.70 A3 0.20REF b 0.15 0.20 0.25 D 4.90 5.00 5.10 E 4.90 5.00 5.10 D2 3.60 3.70 3.80 E2 3.60 3.70 3.80 e 0.35 0.40 0.45 K 0.20 - - L 0.35 0.40 0.45 R 0.075 - - C1 - 0.12 - C2 - 0.12 - BL702/704/706Datasheet 41/47 @2021BouffaloLab

Fig.11.1: QFN48Package drawing Table11.1: QFN48 SizeDescription(Units Of Measure=Millimeter) SYMBOL MIN NOM MAX A 0.80 0.85 0.90 A1 0 0.02 0.05 BL702/704/706Datasheet 42/47 @2021BouffaloLab

Table11.1: QFN48 SizeDescription(Units Of Measure=Millimeter) SYMBOL MIN NOM MAX A3 0.20REF b 0.15 0.20 0.25 D 5.90 6.00 6.10 E 5.90 6.00 6.10 D2 4.30 4.40 4.50 E2 4.30 4.40 4.50 e 0.30 0.40 0.50 H 0.35REF K 0.30 0.40 0.50 L 0.30 0.40 0.50 R 0.075 - - BL702/704/706Datasheet 43/47 @2021BouffaloLab

I Temperature code: C/I/H BL702C-A0 Lot Number YYWW-AC Part number: BL702/4/6(C/S): C:BLE+Zigbee Combo, S:BLE+802.15.4 Slim 00: MSB=flash, 0: no flash, A:4Mb, 1: 8Mb, 3(no use),... LSB=pSRAM, 0:no pSRAM, other:TBD Lot number Date code Fig.12.1: TopMarking Definition BL702/704/706Datasheet 44/47 @2021BouffaloLab

Ordering Information

Package code: Q(QFN), B(BGA),CSP Band: S: Single-band 2.4G; D: dualband, 2.4G/5G; NA; MSB=flash, 0: no flash, 1: 8Mbit, 4:32Mbit, , A:4Mbit LSB=pSRAM, 0:no pSRAM, other: TBD Show in package Environment code : +=RoHS 0/6 , - = RoHS 5 /6 , 1 =RoHS 6 / 6 , 2 = Green Temperature code : C/ I /H Part number: C/S: BLE+Zigbee Combo, BLE+802.15.4 Slim, BL70xC-> 702C: QFN32 Zigbee/BLE Combo 702S: QFN32 BLE+802.15.4 Slim(no zigbee stack), Or MCU 704S: QFN40 BLE+802.15.4 Slim(no zigbee stack), Or MCU 706C: QFN48 Zigbee/BLE Combo 706S: QFN48 BLE+802.15.4 Slim(no zigbee stack), Or MCU Fig.13.1: Part Number Table13.1: Part Order Options Product No.

Description

BL702S-A0-Q2I BLE+802.15.4Slim, MCU, QFN32, 4Mb flash BL702C-10-Q2H Zigbee+BLECombo, QFN32, 8Mb flash BL702/704/706Datasheet 45/47 @2021BouffaloLab

Table13.1: Part Order Options Product No. BL704S-10-Q2I BLE+802.15.4Slim, MCU, QFN40, 8Mb flash BL706C-10-Q2I Zigbee+BLECombo, QFN48, 8Mb flash BL706S-10-Q2I BLE+802.15.4Slim, MCU, QFN48, 8Mb flash BL702/704/706Datasheet 46/47 @2021BouffaloLab

Revision history

Table14.1: Documentrevision history Date Revision Changes 2020/9/15 1.0 Initialrelease 2020/9/22 1.1 Addpackage information(QFN48) 2020/10/20 1.2 Modifythe number of TIMER 2020/11/13 1.3 UpdatePDS/HBN power consumption data 2020/12/4 1.4 Differentiatedifferentpackage information 2021/1/11 1.5 AddGPIO Muxed Pins 2021/1/22 1.6 AddReference design 2021/3/16 1.7 AddProduct use, ADC characteristics, modifythe default functionof SPI pins 2021/4/9 1.8 Addperipheral introduction and modify power consumption data 2021/5/27 1.9 ModifyPinmux description and minimum temperaturevalue 2021/6/9 2.0 Updateproduct number and power consumption parameters BL702/704/706Datasheet 47/47 @2021BouffaloLab