BL602 | DigiCamel IC Datasheet

Online Datasheet

Read BL602 online.

BL602 BOUFFALOALB | Alldatasheet

Document overview

Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 30

Technical content

Datasheet sections

1 Overview
1.1 Wireless
1.2 MCUSubsystem
1.3 Memory
1.4 Security
1.5 Peripheral
1.6 PowerManagement
1.7 Clock
2 FunctionalDescription
2.1 CPU
2.2 Cache
2.3 Memory
2.4 DMA
2.5 Bus
2.6 Interrupt
2.7 Boot
2.8 Power
2.9 Clock
2.10 Peripherals
3 PinDefinition
4 ElectricalSpecifications
4.1 AbsoluteMaximum Rating
4.2 OperatingCondition
5 ReferenceDesign (simplified)

Version：1.6 Copyright @ 2020 www.bouffalolab.com

BL602/604Datasheet 3/30 @2020BouffaloLab

BL602/604Datasheet 4/30 @2020BouffaloLab

BL602/604Datasheet 5/30 @2020BouffaloLab

BL602/BL604 is Wi-Fi + BLE combo chipset for ultra-low-cost and low-power application. Wireless subsystem con- tains2.4Gradio,Wi-Fi802.11b/g/nandBLE5.0baseband/MACdesigns. Microcontrollersubsystemcontainsalow- power32-bitRISCCPU,high-speedcacheandmemories. PowerManagementUnitcontrolslow-powermodes. More- over,variety of security featuresare supported. Peripheralinterfaces include SDIO, SPI, UART,I2C,IR remote, PWM, ADC, DAC, PIR,and GPIOs. AP Host PMU Clock System PLL RC Clock XTAL DMA Crypto Engine SDIO UART XIP Flash SPI I2C PWM IR remote ADC PIR eFuse TSEN EINT DAC GPIO Nor Flash 32-bit RISC CPU Cache / RAM / ROM RF WiFi BLE Figure1.1: FunctionalBlock Diagram BL602/604Datasheet 6/30 @2020BouffaloLab

1.1 Wireless

SupportIEEE 802.11b/g/n protocol
2.4GHzband1T1Rmode,support20MHz,datarate upto 72.2 Mbps
Wi-Fi security WPS/WEP/WPA/WPA2 Per- sonal/WPA2Enterprise/WPA3
WirelessMultimedia (WMM)
Frameaggregation (AMPDU, AMSDU)
ImmediateBlock ACK
Fragmentationand defragmentation
Beaconautomatic reception (hardware TSF)
Hardwaresupport 6 × virtual Wi-Fiinterface
SupportStationmode,SoftAPmode,Station+SoftAP mode,Sniffermode
Supportmultiple cloud access at the sametime
Integratedbalun, PA/LNA
Bluetooth®Low Energy 5.0, Bluetooth Mesh
BLEassists in achieving fast Wi-Fi connection
Wi-Fiand BLE coexist
SupportBLE 5.0 channel selection #2
2M PHY / Coded PHY / ADV extension is not sup- ported

1.2 MCU Subsystem

32-bitRISC CPU with FPU (floatingpoint unit)
Level-1cache
OneRTCtimer update to oneyear
Two32-bit general purpose timers
FourDMA channels
DFS (Dynamic Frequency Scaling) from 1MHz to 192MHz
JTAGdevelopment support
XIPQSPI/SPIFlashwithhardwaredecryptionsupport

1.3 Memory

276KBRAM
128KBROM
1KbeFuse
EmbeddedFlash (Optional)

1.4 Security

Secureboot,support ECC-256 signed image
Securedebug ports
QSPI/SPI Flash On-The-Fly AES Decryption (OT- FAD),supportAES-128 CTR mode
AES128/192/256 bits
SHA-1/224/256
TRNG(TrueRandom Number Generator)
PKA(PublicKeyAccelerator),supportbignumberop- eration,softwaresupport sign/verify API BL602/604Datasheet 7/30 @2020BouffaloLab

1.5 Peripheral

OneSDIO 2.0 slave
OneSPI master/slave with max clock40Mbps
Two UART with max baudrate 10Mbps,support RTS/CTSflow control
OneI2C master with max clock3Mbps
Five PWM channels with max output frequency 40MHz
Two10-bitgeneralDACchannelswithmaxconversion rate512Ksps
Twelve12-bitgeneralADCchannelswithmaxconver- sionrate 2Msps
Two general analog comparators (ACOMP),can be CPUwake up source
One PIR (Passive Infra-Red) detection,can be CPU wakeup source
One infrared remote controller(IR),support NEC RC5 protocol
16or 23 GPIOs

1.6 Power Management

Off
Hibernate(flexible modes)
PowerDown Sleep (flexible modes)
Active

1.7 Clock

SupportXTAL24/32/38.4/40MHz
InternalRC 32kHz oscillator
InternalRC 32MHz oscillator
InternalSystem PLL
XTAL32kHz BL602/604Datasheet 8/30 @2020BouffaloLab

BL602/BL604main functions described as follows： SPI RISC CPU FPU MPU NVIC ROM Cache TCM UART Flash Control DMA Channels Crypto Engines WiFi 802.11b/g/n BLE 4.2 SDIO Slave QSPI SDIO I2C PWM IR DAC ADC EINT GPIO General Pinmux GPIO eFUSE SYSRAM GLB REG PMU RTC Timer x2 RF Bus Figure2.1: SystemArchitecture

2.1 CPU

BL602/BL604 32-bit RISC CPU contains FPU (floating-point unit) for 32-bit single-precision arithmetic, three-stage pipelined(IF,EXE,WB),compressed16and32-bitinstructionset,standardJTAGdebuggerportincluding4hardware- BL602/604Datasheet 9/30 @2020BouffaloLab

programmablebreakpoints,interruptcontrollerincluding64interruptsand16interruptlevels/prioritiesforlowlatency interruptprocessing. Upto192MHzclockfrequency,canbedynamicallyconfiguredtochangeclockfrequency,enter thepower saving mode to achievelow power consumption. BothWiFi/BLEstackandapplicationrunonsingle32-bitRISCCPUforsimpleandultra-lowpowerapplications. CPU performance~1.46 DMIPS/MHz. ~3.1CoreMark/MHz.

2.2 Cache

BL602/BL604 cache improves CPU performance to access external memory. Cache memories can be partially or fullyconfigured as TCM (tightly coupledmemory).

2.3 Memory

BL602/BL604 memories include: on-chip zero-delay SRAM memories, read-only memories, write-once memories, embeddedflash memory (optional).

2.4 DMA

BL602/BL604DMA(directmemoryaccess)controllerhasfourdedicatedchannelsthatmanagedatatransferbetween peripheralsandmemoriestoimprovecpu/busefficiency. Therearethreemaintypesoftransfersincludingmemoryto memory,memorytoperipheral,andperipheraltomemory. DMAalsosupportsLLI(linklistitem)thatmultipletransfers are pre-defined by a series of linked lists, then hardware automatically complete all transfers according to each LLI sizeand address. DMAsupports peripheral UART,I2C, SPI, ADCand DAC.

2.5 Bus

BL602/BL604bus fabric connection and memory-mapsummarized as follows: Table2.1: Bus Connection Slave/Master CPU SDIO DMA Crypto Engine Debug SRAM V V V V V Peripheral V V V - V WiFi/BLE V V V - V Table2.2: Memory Map Module Base Address Size Description WRAM 0x42030000 112KB WirelessSRAM memory RETRAM 0x40010000 4KB Deepsleep memory (Retention RAM) BL602/604Datasheet 10/30 @2020BouffaloLab

Table2.2: Memory Map Module Base Address Size Description HBN 0x4000F000 4KB Deepsleep control (Hibernate) PDS 0x4000E000 4KB Sleepcontrol (Power Down Sleep) SDU 0x4000D000 4KB SDIOcontrol DMA 0x4000C000 4KB DMAcontrol QSPI 0x4000B000 4KB Flashcontrol IRR 0x4000A600 256B IRRemote control TIMER 0x4000A500 256B Timercontrol PWM 0x4000A400 256B PulseWidth Modulation *5 control I2C 0x4000A300 256B I2Ccontrol SPI 0x4000A200 256B SPImaster/slave control UART1 0x4000A100 256B UARTcontrol UART0 0x4000A000 256B UARTcontrol L1C 0x40009000 4KB Cachecontrol eFuse 0x40007000 4KB eFusememory control TZ2 0x40006000 4KB Trustisolation TZ1 0x40005000 4KB Trustisolation SEC 0x40004000 4KB Securityengine GPIP 0x40002000 4KB Generalpurpose DAC/ADC/ACOMP interface control MIX 0x40001000 4KB Mixedsignal register GLB 0x40000000 4KB Globalcontrol register RAM 0x22020000 /0x42020000 64KB On-chip memory.If used as data memory, use address 0x42020000 for ac- cess;if used as program memory,use address 0x22020000 for access XIP 0x23000000 16MB XIPFlash memory TCM1 0x22014000 /0x42014000 48KB Cache memory.If used as data memory, use address 0x42014000 for ac- cess;if used as program memory,use address 0x22014000 for access TCM0 0x22008000 /0x42008000 48KB Cache memory.If used as data memory, use address 0x42008000 for ac- cess;if used as program memory,use address 0x22008000 for access ROM 0x21000000 128KB Read-onlymemory BL602/604Datasheet 11/30 @2020BouffaloLab

2.6 Interrupt

BL602/BL604supports internal RTCwake-up andexternal interrupts wake-up. CPUinterrupt controller supports stack/nesting, level/pulse,and high/low active.

2.7 Boot

BL602/BL604supports multiple boot options: UART,SDIO, and Flash.

2.8 Power

PMU (power management unit) manages the power of the entire chip and is divided into active, idle, sleep, and hibernatepowermodes. Thesoftwarecanbeconfiguredtoentersleepmodeandwake-upviaRTCtimerorEINTto achievelow-power sleep and accurate wake-upmanagement. Powerdown sleep modes are flexiblefor applications to configure as thelowest power consumption.

2.9 Clock

Clock control unit generates clocks to the core MCU and the peripheral SOC devices. The root clock source can be XTAL, PLL or RC oscillator. Dynamic power-saved by proper configurations such as sel, div, en, etc. PMU runs at 32kHzclock to keep system low-powerin sleep mode. BL602/604Datasheet 12/30 @2020BouffaloLab

f 32k_clk CG PMU DIV uart clk (~2MHz) CG gpdac clk 512KHz DIV xclk DIV CG i2c clk DIV CG spi clk DIV CG general adc clk96 MHz CG pwm clk RC32K XTAL32K DIV CG en 11bit f32k_sel RC32M DMLQMM@YUBM@SDN@TFM PLL YUBM@DML root_clk_sel[0] pll_en bclk_en bclk_div hclk_en hclk_div root_clk_sel[1] pll_sel sel sel sel sel 3bit 6bit 16bit 8bit 5bit en en en en en en pir CG CG Cnt XTAL 24/32/38.4/40M 96MHz 80MHz DIV CG ﬂash clk en 3bit sel DIV CG ir clk 6bit en Figure2.2: ClockArchitecture

2.10 Peripherals

Peripheralsinclude SDIO, SPI, UART,I2C, IRremote, PWM, ADC, DAC, PIR. Eachperipheral can be assigned todifferentgroups of GPIOs through flexibleconfigurations. EachGPIO can be used asa general-purpose input and output function. BL602/604Datasheet 13/30 @2020BouffaloLab

BL60232-pin package includes 10 powerpins, 6 analog pins, and 16flexible GPIO pins. PAD_GPIO_0 PAD_GPIO_1 16 15 14 13 12 11 AVDD33_2 AVDD33_1 PAD_GPIO_5 PAD_GPIO_4 PAD_GPIO_3 PAD_GPIO_2 10 9 VDDIO_1 BL602C/E QFN32 ANT VDD15 AVDD18 CHIP_EN XTAL32K_IN XTAL32K_OUT AVDD33 PAD_GPIO_7 DCDC_OUT VDDCORE PAD_GPIO_16 PAD_GPIO_17 PAD_GPIO_20 PAD_GPIO_22 VDDIO_1 PAD_GPIO_21 SW_DCDC VDD33_DCDC PAD_GPIO_8 XTAL_IN XTAL_OUT PAD_GPIO_11 PAD_GPIO_12 PAD_GPIO_14 VDD33_DCDC AVDD33 GPIO0-6/GPIO16-GPIO22/ Embedded ﬂash GPIO9-15 PAD_GPIO_7-8 28 27 26 25 32 31 30 29 3.3V 3.3V 1.8V3.3V Figure3.1: BL602 pinlayout BL602/604Datasheet 14/30 @2020BouffaloLab

BL60440-pin package includes 10 powerpins, 6 analog pins, 1 resetpin, and 23 flexible GPIO pins. VDDIO_1 PAD_GPIO_0 18 17 16 15 14 13 PAD_GPIO_6 PAD_GPIO_5 PAD_GPIO_4 PAD_GPIO_3 PAD_GPIO_2 PAD_GPIO_1 12 11 VDDIO_1 BL604C/E QFN40 ANT VDD15 AVDD18 CHIP_EN XTAL32K_IN XTAL32K_OUT AVDD33 VDDCORE PAD_GPIO_16 PAD_GPIO_17 PAD_GPIO_18 PAD_GPIO_19 PAD_GPIO_21 PAD_GPIO_22 PAD_GPIO_20 VDD33_DCDC PAD_GPIO_15 PAD_GPIO_9 PAD_GPIO_10 PAD_GPIO_11 PAD_GPIO_12 PAD_GPIO_13 PAD_GPIO_14 VDD33_DCDC AVDD33 3.3V 3.3V GPIO9-15 PAD_EXT_RST_N/PAD_GPIO_7-8 36 35 34 33 40 39 38 37 AVDD33_19 AVDD33_210 XTAL_OUT 22 XTAL_IN 21 DCDC_OUT SW_DCDC 32 31 20 19 PAD_GPIO_7 PAD_GPIO_8 1.8V3.3V GPIO0-6/GPIO16-GPIO22/Embedded ﬂash PAD_EXT_RST_N Figure3.2: BL604 pinlayout BL602/604Datasheet 15/30 @2020BouffaloLab

Table3.1: Pin description No VoltageDomain BL602 BL604 I/OType PinName Description

1 VDDIO_1 1 2 DI/DO PAD_GPIO_0 -

2 VDDIO_1 2 3 DI/DO PAD_GPIO_1 -

3 VDDIO_1 3 4 DI/DO PAD_GPIO_2 -

4 VDDIO_1 4 5 DI/DO PAD_GPIO_3 -

5 VDDIO_1 5 6 DI/DO PAD_GPIO_4 -

6 VDDIO_1 6 7 DI/DO PAD_GPIO_5 -

7 VDDIO_1 - 8 DI/DO PAD_GPIO_6 -

8 AVDD33 16 19 DI/DO PAD_GPIO_7 -

9 AVDD33 17 20 DI/DO PAD_GPIO_8 -

10 VDD33_DCDC - 23 DI/DO PAD_GPIO_9 -

11 VDD33_DCDC - 24 DI/DO PAD_GPIO_10 -

12 VDD33_DCDC 20 25 DI/DO PAD_GPIO_11 -

13 VDD33_DCDC 21 26 DI/DO PAD_GPIO_12 -

14 VDD33_DCDC - 27 DI/DO PAD_GPIO_13 -

15 VDD33_DCDC 22 28 DI/DO PAD_GPIO_14 -

16 VDD33_DCDC - 29 DI/DO PAD_GPIO_15 -

17 VDDIO_1 27 34 DI/DO PAD_GPIO_16 -

18 VDDIO_1 28 35 DI/DO PAD_GPIO_17 -

19 VDDIO_1 - 36 DI/DO PAD_GPIO_18 -

20 VDDIO_1 - 37 DI/DO PAD_GPIO_19 -

21 VDDIO_1 29 38 DI/DO PAD_GPIO_20 -

22 VDDIO_1 30 39 DI/DO PAD_GPIO_21 -

23 VDDIO_1 31 40 DI/DO PAD_GPIO_22 -

24 VDDIO_1 - - DI/DO PAD_GPIO_23 -

25 VDDIO_1 - - DI/DO PAD_GPIO_24 -

26 VDDIO_1 - - DI/DO PAD_GPIO_25 -

BL602/604Datasheet 16/30 @2020BouffaloLab

Table3.1: Pin description No VoltageDomain BL602 BL604 I/OType PinName Description

27 VDDIO_1 - - DI/DO PAD_GPIO_26 -

28 VDDIO_1 - - DI/DO PAD_GPIO_27 -

29 VDDIO_1 - - DI/DO PAD_GPIO_28 -

30 AVDD33 12 14 Analog CHIP_EN Chipenable

31 AVDD33 - 18 DI PAD_EXT_RST_N Externalreset

32 AVDD33 13 15 Analog XTAL32K_IN Crystaloscillator 32.768kHz input 33 AVDD33 14 16 Analog XTAL32K_OUT Crystaloscillator 32.768kHz output 34 AVDD33 18 21 Analog XTAL_IN Externalcrystal input, support 24/32/38.4/40MHz 35 AVDD33 19 22 Analog XTAL_OUT Externalcrystal output, support 24/32/38.4/40MHz

36 VDD15 9 11 Analog ANT RFinput and output (single pin)

37 - 32 1 Power VDDIO_1 Externallypowered 3.3V or 1.8V 38 - 23 30 Power VDD33_DCDC DCDC 39 - 24 31 Power SW_DCDC DCDC 40 - 25 32 Power DCDC_OUT DCDC 41 - 7 9 Power AVDD33_1 Externallypowered 3.3V 42 - 8 10 Power AVDD33_2 Externallypowered 3.3V 43 - 15 17 Power AVDD33 Externallypowered 3.3V 44 - 10 12 Power VDD15 Power1.5V 45 - 11 13 Power AVDD18 Power1.8V 46 - 26 33 Power VDDCORE Corepower BL602/604Datasheet 17/30 @2020BouffaloLab

Table3.2: GPIO Muxed Pins PinName Flash1 SDIO SPI UART2(Default /SWAP=1) I2CMaster PWM Analog External_PA JTAG(Default /SWAP=1) IR PAD_GPIO_0 SF2_D1 CLK MIS0 /MOSI SIG0/SIG4 SCL PWM_CH0 - FEM0 TMS/TCK - PAD_GPIO_1 SF2_D2 CMD MOSI /MISO SIG1/SIG5 SDA PWM_CH1 - FEM1 TDI/TDO - PAD_GPIO_2 SF2_D3 DAT0 SS SIG2/SIG6 SCL PWM_CH2 - FEM2 TCK/TMS - PAD_GPIO_3 - DAT1 SCLK SIG3/SIG7 SDA PWM_CH3 - FEM3 TDO/TDI - PAD_GPIO_4 - DAT2 MISO /MOSI SIG4/SIG0 SCL PWM_CH4 ADC_CH1 FEM0 TMS/TCK - PAD_GPIO_5 - DAT3 MOSI /MISO SIG5/SIG1 SDA PWM_CH0 ADC_CH4 FEM1 TDI/TDO - PAD_GPIO_6 - - SS SIG6/SIG2 SCL PWM_CH1 ADC_CH5 FEM2 TCK/TMS - PAD_GPIO_7 - - SCLK SIG7/SIG3 SDA PWM_CH2 - FEM3 TDO/TDI - PAD_GPIO_8 - - MISO /MOSI SIG0/SIG4 SCL PWM_CH3 - FEM0 TMS/TCK - PAD_GPIO_9 - - MOSI /MISO SIG1/SIG5 SDA PWM_CH4 ADC_CH6/7 FEM1 TDI/TDO - PAD_GPIO_10 - - SS SIG2/SIG6 SCL PWM_CH0 MICBIAS /ADC_CH8/9 FEM2 TCK/TMS - PAD_GPIO_11 - - SCLK SIG3/SIG7 SDA PWM_CH1 ADC_CH10 /IRTX FEM3 TDO/TDI IRRX (ir_rx_gpio_sel=1) PAD_GPIO_12 - - MISO /MOSI SIG4/SIG0 SCL PWM_CH2 ADC_CH0 FEM0 TMS/TCK IRRX (ir_rx_gpio_sel=2) PAD_GPIO_13 - - MOSI /MISO SIG5/SIG1 SDA PWM_CH3 ADC_CH3 /DAC_A FEM1 TDI/TDO IRRX (ir_rx_gpio_sel=3) PAD_GPIO_14 - - SS SIG6/SIG2 SCL PWM_CH4 ADC_CH2 /DAC_B FEM2 TCK/TMS - PAD_GPIO_15 - - SCLK SIG7/SIG3 SDA PWM_CH0 psw_irrcv_out /ADC_CH11 FEM3 TDO/TDI - BL602/604Datasheet 18/30 @2020BouffaloLab

Table3.2: GPIO Muxed Pins PinName Flash1 SDIO SPI UART2(Default /SWAP=1) I2CMaster PWM Analog External_PA JTAG(Default /SWAP=1) IR PAD_GPIO_16 - - MISO /MOSI SIG0/SIG4 SCL PWM_CH1 - FEM0 TMS/TCK - PAD_GPIO_17 SF1_D3 - MOSI /MISO SIG1/SIG5 SDA PWM_CH2 - FEM1 TDI/TDO - PAD_GPIO_18 SF1_D2 - SS SIG2/SIG6 SCL PWM_CH3 - FEM2 TCK/TMS - PAD_GPIO_19 SF1_D1 - SCLK SIG3/SIG7 SDA PWM_CH4 - FEM3 TDO/TDI - PAD_GPIO_20 SF1_D0 /SF2_D0 - MISO /MOSI SIG4/SIG0 SCL PWM_CH0 - FEM0 TMS/TCK - PAD_GPIO_21 SF1_CS /SF2_CS - MOSI /MISO SIG5/SIG1 SDA PWM_CH1 - FEM1 TDI/TDO - PAD_GPIO_22 SF1_CLK /SF2_CLK - SS SIG6/SIG2 SCL PWM_CH2 - FEM2 TCK/TMS - PAD_GPIO_23 SF0_CLK - - - - - - - - - PAD_GPIO_24 SF0_CS - - - - - - - - - PAD_GPIO_25 SF0_D0 - - - - - - - - - PAD_GPIO_26 SF0_D1 - - - - - - - - - PAD_GPIO_27 SF0_D2 - - - - - - - - - PAD_GPIO_28 SF0_D3 - - - - - - - - - 1 Thereare 3 groups of Flash,and the smallest selection unit isgroup, which is configured according togroup when used. 2 Thedefault UARTsignal mapping tableis shown below. BL602/604Datasheet 19/30 @2020BouffaloLab

Table3.3: UARTSignal Mapping(Default) UARTSignal uart_sig_x_sel MappingSignal UART_SIG0 uart_sig_0_sel=0 UART0_RTS UART_SIG1 uart_sig_1_sel=1 UART0_CTS UART_SIG2 uart_sig_2_sel=2 UART0_TXD UART_SIG3 uart_sig_3_sel=3 UART0_RXD UART_SIG4 uart_sig_4_sel=4 UART1_RTS UART_SIG5 uart_sig_5_sel=5 UART1_CTS UART_SIG6 uart_sig_6_sel=6 UART1_TXD UART_SIG7 uart_sig_7_sel=7 UART1_RXD Note: UART_SIG0-UART_SIG7 can be configured as any of 8 Mapping Signals. For example: UART_SIG0 can alsobe configured as UART_RXD.Thespecific signal mapping example is shownin the table below. Table3.4: UARTSignal Mapping(Example) UARTSignal uart_sig_x_sel MappingSignal UART_SIG0 uart_sig_0_sel=7 UART1_RXD UART_SIG1 uart_sig_1_sel=6 UART1_TXD UART_SIG2 uart_sig_2_sel=5 UART1_CTS UART_SIG3 uart_sig_3_sel=4 UART1_RTS UART_SIG4 uart_sig_4_sel=3 UART0_RXD UART_SIG5 uart_sig_5_sel=2 UART0_TXD UART_SIG6 uart_sig_6_sel=1 UART0_CTS UART_SIG7 uart_sig_7_sel=0 UART0_RTS BL602/604Datasheet 20/30 @2020BouffaloLab

4.1 Absolute Maximum Rating

Table4.1: AbsoluteMaximum Rating PinName Min. Max. Unit AVDD33_1 -0.3 3.63 V AVDD33_2 -0.3 3.63 V AVDD33 -0.3 3.63 V DVDD33_DCDC -0.3 3.63 V DVDDIO_1 -0.3 3.63 V ESDProtection(HBM) 2000 V StorageTemperature -45 135 ◦C

4.2 Operating Condition

Table4.2: RecommendedPower Operating Range PinName Min. Typ Max. Unit AVDD33_1 2.1 3.3 3.63 V AVDD33_2 2.1 3.3 3.63 V AVDD33 2.1 3.3 3.63 V DVDD33_DCDC 2.1 3.3 3.63 V BL602/604Datasheet 21/30 @2020BouffaloLab

Table4.3: RecommendedTemperatureOperating Range Item Min. Max. Unit Temperature MainDie -30 105 ◦C Multi-DieSiP -30 85 ◦C Table4.4: GeneralOperating Conditions Item Description Min. Typ Max. Unit FCPU CPU/TCM/Cache clockfrequency 1 160 192 MHz FSYS Systemclock frequency 1 80 96 MHz BL602/604Datasheet 22/30 @2020BouffaloLab

Reference Design (simplified) EXT_RST (BL604 Only) BL602/604 24/32/38.4/40MHz (Required) 32.768kHz (Optional) Antenna ANT 3.3V 16/23x GPIO XTAL32K_OUTXTAL32K_INXTAL_IN XTAL_OUT 1.8V or 3.3V CHIP_EN AVDD15_RF AVDD18_RF VDD33 VDDIO_1 AVDD33_2 AVDD33_1 AVDD33_DCDC GPIOs VDDCORE SW_DCDC DCDC_OUT Figure5.1: ReferenceDesign BL602/604Datasheet 23/30 @2020BouffaloLab

Figure6.1: QFN32 Packagedrawing Table6.1: QFN32 Size Description(UnitsOf Measure=Millimeter) SYMBOL MIN NOM MAX A 0.70 0.75 0.80 A1 0.00 0.02 0.05 BL602/604Datasheet 24/30 @2020BouffaloLab

Table6.1: QFN32 Size Description(UnitsOf Measure=Millimeter) SYMBOL MIN NOM MAX A2 0.50 0.55 0.60 A3 0.20REF b 0.15 0.20 0.25 D 3.90 4.00 4.10 E 3.90 4.00 4.10 D2 2.80 2.90 3.00 E2 2.80 2.90 3.00 e 0.30 0.40 0.50 H 0.30REF K 0.25REF L 0.25 0.30 0.35 R 0.09 - - c1 - 0.10 - c2 - 0.10 - BL602/604Datasheet 25/30 @2020BouffaloLab

Figure7.1: QFN40 Packagedrawing Table7.1: QFN40 Size Description(UnitsOf Measure=Millimeter) SYMBOL MIN NOM MAX A 0.80 0.85 0.90 A1 0 0.02 0.05 BL602/604Datasheet 26/30 @2020BouffaloLab

Table7.1: QFN40 Size Description(UnitsOf Measure=Millimeter) SYMBOL MIN NOM MAX A2 0.60 0.65 0.70 A3 0.20REF b 0.15 0.20 0.25 D 4.90 5.00 5.10 E 4.90 5.00 5.10 D2 3.60 3.70 3.80 E2 3.60 3.70 3.80 e 0.35 0.40 0.45 K 0.20 - - L 0.35 0.40 0.45 R 0.075 - - C1 - 0.12 - C2 - 0.12 - BL602/604Datasheet 27/30 @2020BouffaloLab

I Temperature code: C/ I / A / M BL604 C 20 Lot Number - xxyy YYWW-AC Part number : BL602/4 ( C / L / E ): wiﬁ- ble combo /Light/ Enhance 00 : Lot number Date code MSB=flash,0:no flash,1:8Mbit,2:16Mbit,3(no use),4:32Mbit LSB=pSRAM,0:no pSRAM,1(no use),2:16Mbit,3(no use),4:32Mbit Figure8.1: TopMarking Definition BL602/604Datasheet 28/30 @2020BouffaloLab

Ordering Information

Environment code : +=RoHS 0/6 , - = RoHS 5 /6 , 1 =RoHS 6 / 6 , 2 = Green Temperature code : C / I /A /M Package code : Q (QFN), B (BGA) , CSP … Band: S : Single - band 2.4 G ; D: dualband , 2.4 G /5 G ; NA : 2 .4 G MSB = flash , 0 : no flash, 1: 8Mbit , 2 :16Mbit , 3 ( no use) , 4 :32Mbit LSB = pSRAM, 0:no pSRAM, 1(no use) , 2 :16 Mbit, 3 (no use) 4 :32 Mbit … Part number : C / L / E: wifi - ble combo /Light /Enhance Eg. BL602 C / L / E, BL604 C/L /E Show in package Figure9.1: Part Number Table9.1: Part Order Options Product No. Description BL602C-00-Q2I WiFi/BLECombo, QFN32 BL602C-20-Q2I WiFi/BLECombo, QFN32, flash 16Mb BL604E-20-Q2I WiFi/BLEEnhance, QFN40, flash 16Mb BL602/604Datasheet 29/30 @2020BouffaloLab

Revision history

Table10.1: Documentrevision history Date Revision Changes 2020/2/13 0.9 Initialrelease 2020/4/20 1.0 AddMarking Definition 2020/5/28 1.1 Modifyclock frequency 2020/7/28 1.2 ModifyProduct Number 2020/12/15 1.4 Modifyperipheral characteristics 2020/12/31 1.5 Modifyfunction description 2020/1/13 1.6 Updatereference design BL602/604Datasheet 30/30 @2020BouffaloLab

Product Information

BL602 specifications and overview.

Summary

BL602/BL604 is Wi-Fi + BLE combo chipset for ultra-low-cost and low-power application. 2020/1/13 1.6

Description

BL602/BL604 is Wi-Fi + BLE combo chipset for ultra-low-cost and low-power application. 2020/1/13 1.6

Source title BL602 Datasheet(PDF) - Bouffalo Lab Intelligent Technology Co., Ltd.

Related Parts

More parts from the same family.

Browse manufacturer