AV9155C

AV9155C ICST | Alldatasheet

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Systems, Inc. General Description Features AV9155C Block Diagram AV9155C Rev F 12/13/00 Low Cost 20-Pin Frequency Generator The A V9155C is a low cost frequency generator designed specifically for desktop and notebook PC applications with either 3.3V or 5.0V power supply voltage. Its CPU clocks provide all necessary CPU frequencies for 286, 386 and 486 systems, including support for the latest speeds of processors. The device uses a 14.318 MHz crystal to generate the CPU and all peripheral clocks for integrated desktop motherboards. The dual 14.318 MHz clock outputs allows one output for the system and one to be the input to an ICS graphics frequency generator such as the A V9194. The CPU clock offers the unique feature of smooth, glitch- free transitions from one frequency to the next, making this ideal device to use whenever slowing the CPU speed. The A V9155C makes a gradual transition between frequencies, so that it obeys the Intel cycle-to-cycle timing specification for 486 systems. The simultaneous 2X and 1X CPU clocks offer controlled skew to within 1.5ns (max) of each other. ICS offers several versions of the A V9155C. The different devices are shown below:

• Compatible with 286, 386, and 486 CPUs
• Supports turbo modes
• Generates communications clock, keyboard clock, floppy disk clock, system reference clock, bus clock and CPU clock
• Output enable tristates outputs
• Up to 100 MHz at 5V or 3.3V
• 20-pin DIP or SOIC
• All loop filter components internal
• Skew-controlled 2X and 1X CPU clocks
• Power-down option ICS has been shipping motherboard frequency generators since April 1990, and is the leader in the area of multiple output clocks on a single chip. The A V9155C is a third generation device, and uses ICS’s patented analog CMOS phase-locked loop technology for low phase jitter. ICS offers a broad family of frequency generators for motherboards, graphics and other applications, including cost-effective versions with only one or two output clocks. Consult ICS for all of your clock generation needs. Pentium is a trademark of Intel Corporation. TRAPN OITPIRCSED 10-C5519VAK LCSUBzHM61htiwrotarenegkcolcdraobrehtoM 20-C5519VAK LCSUBzHM23htiwrotarenegkcolcdraobrehtoM 32-C5519VAm uitnePsedulcnI /GD4 seicneuqerf 63-C5519VAk colcISCSzHM04laicepsaserutaeF

20-Pin DIP or SOIC 20-Pin DIP or SOIC Pin Descriptions for AV9155C-01, -02 NIP REBMUN EMANNIPE PYTN OITPIRCSED 1z HM348.1t uptuO. tuptuokcolczHM48.1 22 Xt uptuO. noitcennoclatsyrC 31 Xt upnI. noitcennoclatsyrC 4D DV- . )V0.5roV3.3(ylppusrewoplatigiD 5D NG- . dnuorGlatigiD 6z HM23/zHM61t uptuO. tuptuokcolc)20-(zHM23ro)10-(zHM61 7z HM42t uptuO. tuptuokcolcO/Inoitanibmoc/ksidyppolfzHM42 8z HM21t uptuO. tuptuokcolcdraobyekzHM21 9D NGA- . )noisrevlanigiro(dnuorggolanA 01E Ot upnI) .pu-lluplanretnisaH(.wolnehwstuptuollasetatsirT.elbanetuptuO 112 SFt upnI) .pu-lluplanretnisaH(.2#tcelesycneuqerfkcolcUPC 21# DPt upnI) .pu-lluplanretnisaH(.wolnehwpihceritneffostuhS.nwod-rewoP 31z HM813.41t uptuO. tuptuokcolcecnereferzHM813.41 41z HM813.41t uptuO. tuptuokcolcecnereferzHM813.41 51D NG- . dnuorglatigiD 61D DV- . )V0.5roV3.3(ylppusrewoplatigiD 71U PCX2t uptuO. tuptuokcolcUPCX2 81U PCt uptuO. tuptuokcolcUPCX1 911 SFt upnI) .pu-lluplanretnisaH(.1#tcelesycneuqerfkcolcUPC 020 SFt upnI) .pu-lluplanretnisaH(.0#tcelesycneuqerfkcolcUPC

Functionality - AV9155C-01 (Using 14.318 MHz input. All frequencies in MHz.) CLOCK#2 CPU and 2XCPU *VDD minimum 3.15V . PERIPHERAL CLOCKS REFERENCE CLOCKS Functionality - AV9155C-02 (Using 14.318 MHz input. All frequencies in MHz.) CLOCK#2 CPU and 2XCPU * VDD minimum 3.15V PERIPHERAL CLOCKS REFERENCE CLOCKS Frequency Transitions A key feature of the A V9155C is its ability to provide smooth, glitch-free frequency transitions on the CPU and 2XCPU clocks when the frequency select pins are changed. These frequency transitions do not violate the Intel 486 specification of less than 0.1% frequency change per clock period. Using an Input Clock as Reference The A V9155C is designed to accept a 14.318 MHz crystal as the input reference. With some external changes, it is possible to use a crystal oscillator or clock input. Please see application note AN04 for details on driving the A V9155C with a clock. KLCMMOC )1niP( KLCSUB )6niP( KLCDF )7niP( KLCBK )8niP( 348.16 14 22 1 KLCMMOC )1niP( KLCSUB )6niP( KLCDF )7niP( KLCBK )8niP( 348.12 34 22 1 1KLCFER )31niP( 2KLCFER )41niP( 813.418 13.41 1KLCFER )31niP( 2KLCFER )41niP( 813.418 13.41 2SF )11niP( 1SF )91niP( 0SF )02niP( UPCX2 )71niP( UPC )81niP( 66.66 *08 *001 33.33 *04 *05 2SF )11niP( 1SF )91niP( 0SF )02niP( UPCX2 )71niP( UPC )81niP( 66.66 *08 *001 33.33 *04 *05

Pin Descriptions for AV9155C-23, -36 20-Pin DIP or SOIC 20-Pin DIP or SOIC NIP REBMUN NIP EMAN EPYTN OITPIRCSED 1z HM04/348.1t uptuO. tuptuokcolc)63-(ISCSzHM04/)32-(zHM48.1 22 Xt uptuO. noitcennoclatsyrC 31 Xt upnI. noitcennoclatsyrC 4D DV- . )V0.5roV3.3(ylppusrewoplatigiD 5D NG- . dnuorglatigiD 6z HM51/zHM61t uptuO. tuptuokcolc)63-(zHM51/)32-(zHM61 7z HM42t uptuO. tuptuokcolcO/Inoitanibmoc/ksidyppolfzHM42 8z HM21t uptuO. tuptuokcolcdraobyekzHM21 9D NGA- . )noisrevlanigiro(dnuorggolanA 01E Ot upnI) .pu-lluplanretnisaH(.wolnehwstuptuollasetatsirT.elbanetuptuO 112 SFt upnI) .pu-lluplanretnisah32-(.2#tcelesycneuqerfkcolcUPC 21# DPt upnI) .pu-lluplanretnisaH(.wolnehwpihceritneffostuhS.nwod-rewoP 31z HM813.41t uptuO. tuptuokcolcecnereferzHM813.41 41z HM813.41t uptuO. tuptuokcolcecnereferzHM813.41 51D NG- . dnuorglatigiD 61D DV- . )V0.5roV3.3(ylppusrewoplatigiD 71U PCX2t uptuO. tuptuokcolcUPCX2 81U PCt uptuO. tuptuokcolcUPCX1 911 SFt upnI) .pu-lluplanretnisah32-(.1#tcelesycneuqerfkcolcUPC 020 SFt upnI) .pu-lluplanretnisah32-(.0#tcelesycneuqerfkcolcUPC

CLOCK#2 CPU and 2XCPU *VDD minimum 3.15V PERIPHERAL CLOCKS REFERENCE CLOCKS CLOCK#2 CPU and 2XCPU *VDD minimum 3.15V PERIPHERAL CLOCKS REFERENCE CLOCKS KLCMMOC )1niP( niP(KLCSUB KLCDF )7niP( KLCBK )8niP( 348.16 14 22 1 KLCISCS )1niP( niP(KLCSUB KLCDF )7niP( KLCBK )8niP( 045 14 22 1 1KLCFER )31niP( 2KLCFER )41niP( 813.418 13.41 1KLCFER )31niP( 2KLCFER )41niP( 813.418 13.41 2SF )11niP( 1SF )91niP( 0SF )02niP( UPCX2 )71niP( UPC )81niP( 66.66 *08 *001 33.33 *04 *05 Functionality - AV9155C-23 (Using 14.318 MHz input. All frequencies in MHz.) Functionality - AV9155C-36 (Using 14.318 MHz input. All frequencies in MHz.) 2SF )11niP( 1SF )91niP( 0SF )02niP( UPCX2 )71niP( UPC )81niP( *57 66.66 *08 *5.73 33.33 *04

Electrical Characteristics at 5V Absolute Maximum Ratings Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. V DD = 4.0 to 5.5V (5V +10%/-20%); T A=0°C to 70 °C unless otherwise stated Notes: 1 Parameter is guaranteed by design and characterization, not subject to production testing. scitsiretcarahCCD RETEMARAPL OBMYSS NOITIDNOCTSETN IMP YTX AMS TINU egatloVwoLtupnIV L IV D DV 5=- - 8 .0V egatloVhgiHtupnIV H IV D DV 5=0 .2- - V #DP,egatloVhgiHtupnIV D PHIV D Dt upni#DProf,V5=2 .2- - V tnerruCwoLtupnII L IV N I) nippu-llup(V0=- 6 15 3A µ tnerruChgiHtupnII H IV N IV=D D5 -0 5 A µ egatloVwoLtuptuOV L OI L OA m8=- 5 1.04 .0V egatloVhgiHtuptuO 1 VHOI H OA m52-=4 .27 .3- V tnerruCwoLtuptuO 1 ILOV L O8 .0=5 12 3-A m tnerruChgiHtuptuO 1 IHOV H OV 0.2=- 8 4-0 3-A m tnerruCylppuSI D Dz HM66,dedaolnU- 8 30 6A m nwod-rewoP,tnerruCylppuSI D PDDK LCSx 0 =#DP000=- 7 .05 .1A m egnahCycneuqerFtuptuO dnaylppuSrevo erutarepmeT 1 FD lacipytottcepserhtiW ycneuqerf -2 00.01 0.0% tnerructiucrictrohS 1 ICSk colctuptuohcaE5 20 4-A m ecnaticapaCtupnI 1 CI 2 X,1XtpecxE- - 0 1F p ecnaticapaCdaoL 1 CL 2 X,1XsniP- 0 2-F p rotsiseRpu-lluP 1 RupV taN IV=D DV 1-0 210 530 07m hok

Electrical Characteristics at 5V VDD = 4.0 to 5.5V (5V +10%/-20%); T A=0°C to 70 °C unless otherwise stated Notes: 1 Parameter is guaranteed by design and characterization, not subject to production testing. scitsiretcarahCCA RETEMARAPL OBMYSS NOITIDNOCTSETN IMP YTX AMS TINU emiTesiRkcolCtupnI 1 trCI- - 0 2s n emiTllaFkcolCtupnI 1 tfCI- - 0 2s n emitesiRtuptuO 1 tr V 0.2ot8.0,daolFp52- 5 .12s n emitesiR 1 tr %08ot%02,daolFp52 VDD -0 .20 .4s n emitllaFtuptuO 1 tf V 8.0ot0.2,daolFp52- 0 .10 .2s n emitllaF 1 tf %02ot%08,daolFp52 VDD -3 .10 .3s n elcycytuD 1 dt V 4.1tadaolFp525 5/542 5/845 4/55% ,elcycytuD 1 skcolcecnereferd t V 4.1tadaolFp526 33 40 5% amgiseno,rettiJ 1 05ot02, skcolczHM 1 04dnaUPCno UPCX2nozHM001ot t1sljs elcyc000,01- 8 .00 .2% amgiseno,rettiJ 1 dexif, 02wolebskcolc&kcolc zHM04woleb,UPCnozHM UPCX2no t2sljs elcyc000,01- 8 .00 .2% etulosba,rettiJ 1 05ot02, skcolczHM 1 04dnaUPCno UPCX2nozHM001ot t1bajs elcyc000,010 .4-0 .20 .4% etulosba,rettiJ 1 kcolcdexif, nozHM02wolebskcolc& nozHM04woleb,UPC UPCX2 t2bajs elcyc000,010 .5-0 .20 .5% ycneuqerFtupnI 1 fni2 8 13.412 3z HM tuptuOmumixaM ycneuqerF 1 ftuoU PCX2ta0 010 22z HM dnaUPCneewtebwekskcolC stuptuoUPCX2 1 Tks- 0 410 04s p emiTpu-rewoP 1 tOPtz HM66ot- 8 5 1s m emiTnoitisnarTycneuqerF 1 ttfH M66.66ot8morf- 5 .62 1s m zHM08ot23morf- 8 .12 .3s m zHM23ot08morf- 5 .20 .5s m

Electrical Characteristics at 3.3V VDD =3.0V to 3.7V , TA=0°C to 70°C unless otherwise stated Notes: 1 Parameter is guaranteed by design and characterization, not subject to production testing. scitsiretcarahCCD RETEMARAPL OBMYSS NOITIDNOCTSETN IMP YTX AMS TINU egatloVwoLtupnIV L IV D DV 3.3=- - V 2.0D DV egatloVhgiHtupnIV H IV D DV 3.3=V 7.0D D- - V #DP,egatloVhgiHtupnIV D PHIV D Dt upni#DProf,V3.3=2 .2- - V tnerruCwoLtupnII L I) nippu-llup(V0=NIV- 1 15 2A µ tnerruChgiHtupnII H IV N IV=D D5 -0 5 A µ egatloVwoLtuptuOV L OI L OA m4=- V 50.0D DV 1.0D DV egatloVhgiHtuptuO 1 VHOI H OA m5.3-=- V 49.0D D- V tnerruCwoLtuptuO 1 ILOV L OV 2.0=D D2 12 2-A m tnerruChgiHtuptuO 1 IHOV H OV 7.0=D D- 1 1-5 .6-A m tnerruCylppuSI D Dz HM6.66,dedaolnU- 8 25 4A m nwod-rewoP,tnerruCylppuSI D PDDK LCSx 0 =#DP000=- 5 2.05 .0A m egnahCycneuqerFtuptuO dnaylppuSrevo erutarepmeT 1 FD lacipytottcepserhtiW ycneuqerf -2 00.01 0.0% tnerructiucrictrohS 1 ICSk colctuptuohcaE0 20 3-A m ecnaticapaCtupnI 1 CI 2 X,1XtpecxE- - 0 1F p ecnaticapaCdaoL 1 CL 2 X,1XsniP- 0 2-F p rotsiseRpu-lluP 1 RupV taN IV=D DV 1-0 210 330 56m hok

Electrical Characteristics at 3.3V VDD = +3.3V ±10%, TA=0°C to 70 °C unless otherwise stated Notes: 1 Parameter is guaranteed by design and characterization, not subject to production testing. 2 Output frequencies on 2XCPU of 80 or 100 MHz require minimum V DD of 3.15V (3.3 -5%). scitsiretcarahCCA RETEMARAPL OBMYSS NOITIDNOCTSETN IMP YTX AMS TINU emiTesiRkcolCtupnI 1 trCI- - 0 2s n emiTllaFkcolCtupnI 1 tfCI- - 0 2s n emitesiR 1 tr %08ot%02,daolFp52 VDD -0 .30 .4s n emitllaF 1 tf %02ot%08,daolFp52 VDD -8 .15 .2s n elcycytuD 1 dt V %05tadaolFp52D D0 48 40 6% ,elcycytuD 1 skcolcecnereferd t V %05tadaolFp52D D3 36 37 6% amgiseno,rettiJ 1 t1sljs elcyc000,01- 8 .05 .2% etulosba,rettiJ 1 t1bajs elcyc000,010 .5-0 .20 .5% ycneuqerFtupnI 1 fni2 8 13.412 3z hM ycneuqerFtuptuOmumixaM 2,1 ftuoU PCX2ta7 0 41-z HM dnaUPCneewtebwekskcolC stuptuoUPCX2 1 Tks0 010 220 05s p emiTpu-rewoP 1 ttOPz HM66ot- 6 2 1s m emiTnoitisnarTycneuqerF 1 ttfz HM0.05ot8morf- 6 2 1s m

CLOCK#2 CPU and 2XCPU PERIPHERAL CLOCKS Actual Output Frequencies (Using 14.318 MHz input. All frequencies in MHz.) AV9155C-23 CPU CLOCK PERIPHERAL CLOCKS AV9155C-36 CPU CLOCK PERIPHERAL CLOCKS 2SF )11niP( 1SF )91niP( 0SF )02niP( UPCX2 )71niP( UPC )81niP( 05.7 15.51 22.23 90.04 11.05 28.66 81.08 32.001 57.3 67.7 11.61 50.02 60.52 14.33 90.04 11.05 2SF )11niP( 1SF )91niP( 0SF )02niP( UPCX2 )71niP( UPC )81niP( 450.8 200.61 578.95 688.93 311.05 674.66 181.08 622.001 720.4 100.8 639.92 349.91 750.52 832.33 190.04 311.05 KLCMMOC )1niP( KLCSUB )7niP( KLCDF )6niP( KLCBK )8niP( 00.040 0.510 0.420 0.21 2SF )11niP( 1SF )91niP( 0SF )02niP( UPCX2 )71niP( UPC )81niP( 071.57 049.13 631.06 090.04 311.05 674.66 181.08 309.15 *585.73 079.51 860.03 540.02 750.52 832.33 190.04 259.52 KLCMMOC )1niP( niP(KLCSUB KLCDF )7niP( KLCBK )8niP( KLCMMOC )1niP( KLCSUB )6niP( KLCDF )7niP( KLCBK )8niP( 648.10 0.610 0.420 0.21

Notes: 1. ICS recommends the use of an isolated ground plane for the A V9155C. All grounds shown on this drawing should be connected to this ground plane. This ground plane should be connected to the system ground plane at a single point. Please refer to A V9155C Board Layout Diagram. 2. A single power supply connection for all VDD lines at the 2.2µF decoupling capacitor is recommended to reduce interaction of analog and digital circuits. The 0.1 µF decoupling capacitors should be located as close to each VDD pin as possible. 3. A 33ΩΩΩΩΩ series termination resistor should be used on any clock output which drives more than one load or drives a long trace (more than about two inches), especially when using high frequencies (>50 MHz). This termination resistor is put in series with the clock output line close to the clock output. It helps improve jitter performance and reduce EMI by damping standing waves caused by impedance mismatches in the output clock circuit trace. 4. The ferrite bead does not enhance the performance of the A V9155C, but will reduce EMI radiation from the VDD line. AV9155C Recommended External Circuit

AV9155C Recommended Board Layout This is the recommended layout for the A V9155C to maximize clock performance. Shown are the power and ground connections, the ground plane, and the input/output traces. Use of the isolated ground plane and power connection, as shown, will prevent stray high frequency ground and system noise from propagating through the device. When compared to using the system ground and power planes, this technique will minimize output clock jitter. The isolated ground plane should be connected to the system ground plane at one point, near the 2.2µF decoupling cap. For lowest jitter performance, this isolated ground plane should be kept away from clock output pins and traces. Keeping the isolated ground plane area as small as possible will minimize EMI radiation. Use a sufficient gap between the isolated ground plane and system ground plane to prevent AC coupling. The ferrite bead in the VDD line optional, but will help reduce EMI. The traces to distribute the output clocks should be over a system ground or power supply plane. The trace width should be about two times the thickness of the PC board between the trace and the underlying plane. These guidelines help minimize clock jitter and EMI radiation. The traces to distribute power should be as wide as possible.

Ordering Information

Example: 20-Pin DIP Package AV9155C-02CN20, AV9155C-23CN20, AV9155C-36CN20 Notes: Tape and reel packaging should be ordered with the suffix T&R. For instance, if the -01 in DIP and tape & reel is required, order the part as A V9155C-01CN20T&R. ICS XXXX-PPP M X#W Lead Count & Package Width Lead Count=1, 2 or 3 digits W=.3” SOIC or .6” DIP; None=Standard Width Package Type N=DIP (Plastic#) T&R=Tape and Reel Pattern Number (2 or 3 digit number for parts with ROM code patterns) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, A V=Standard Device

AV9155C-01CW20, AV9155C-02CM20, AV9155C-23CM20, AV9155C-36CM20 TNUOCDAELL 41L 61L 81L 02L 42L 82L 23 ICS XXXX-PPP M X#W Lead Count & Package Width Lead Count=1, 2 or 3 digits W=.3” SOIC or .6” DIP; None=Standard Width Package Type W=SOIC T&R=Tape and Reel Pattern Number (2 or 3 digit number for parts with ROM code patterns) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV=Standard Device Example: