AV9154A ICST | Alldatasheet
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Technical content
Features
9154 Rev B 04/17/97
Description of new pin: SLOWCLK# forces 2XCPUCLK output to ramp smoothly to 8MHz and CPUCLK output to 4 MHz when pulled low. Description of new pis: SLOWCLK# forces 2XCPUCLK output to ramp smoothly to 8MHz when pulled low. STOPCLK# provides gilitch- free stop of the 2XCPUCLK output when pulled low. When raised back high, the 2XCPUCLK output clock resumes full speed operation (no clock frequency ramp up since the internal VCO is not stopped). 16-Pin PDIP or SOIC 9154-04 16-Pin PDIP or SOIC 9154-26 16-Pin PDIP or SOIC 9154-10
The ICS9154A -43 incorporates a unique stop clock feature compatible with static logic processors. When the stop clock pin goes low, the 2XCPUCLK will go low after the next occurring falling edge. When STOPCLK again goes high, 2XCPUCLK resumes on the next rising edge of the internal clock. This feature enables fast, glitch-free starts and stops of the 2XCPUCLK and is guaranteed that the CPU does not receive any short period clocks.
Frequencies based upon 14.318 MHz input) Note: Internal Pull-up Resistors. * -04 and -10 have no pull-ups or frequency select pins ** -10 has no pull-up or Pin 9 PDFCLK P IN N U MB E R PIN NAME TYPE DESCRIPTION 444444 V D D P D i gital power (3.3 or 5V). 13 13 13 13 13 13 VDD P Digital power (3.3 or 5V). 555555 G N D P D i gital ground. 12 12 12 12 12 12 GDD P Digital ground. 888888 A G N D P A n a l o g g r o u n d . 1 16 1 16 1 1 FS0 I Frequency select 0 for CPU clock (has internal pull-up).* 16 15 16 15 16 16 FS1 I Frequency select 1 for CPU clock (has internal pull-up).* 10 - 10 10 9 10 FS2 I Frequency select 2 for CPU clock (has internal pull-up).* - - 9 9 - - OE I Tristates outputs when low (has internal pull-up).* ---- 1 5 1 5 S L O W C L K # I Slows 2XCPU clock to 8 MHz (active low) (has internal pull-up). -----9 S T O P C L K # I Stops 2XCPU clock glitch-free (active low) (has internal pull-up). 333333 X 1 I C r ystal In. 222222 X 2 O C r ystal Out. 11 10 11 11 10 11 14.318 MHz O 14.318 MHz reference clock output. - 7 1 - - 1.84 MHz O 1.84 MHz (comm) clock output. 6 1 1 6666 2 4 M H z O 2 4 M H z ( f l oppy disk) clock output. -6---- 1 6 M H z O 1 6 M H z c l o c k o utput. - - 7 7 - - 12 MHz O 12 MHz keyboard clock output. 7 1 - - 7 7 8 MHz O 8 MHz keyboard clock output. 14 14 14 - 11 - CPUCLK O CPU clock output. 15 - 15 14 14 14 2XCPUCLK O 2X CPU clock output. 9----- P D # I P o w e r - D o w n A l l ( a ctive low) (has internal pull-up). -9----P D F C L K # I Power-Down Fixed Clock (1.84, 8, 16, 24) (active low).**
- These selections only operate at 5 V . Actual Frequencies (using 14.318 MHz input, all frequencies in MHz) FS2 FS1 FS0 -27 2CPUCLK -42 -43 2XCPUCLK CPUCLK 2XCPUCLK 0 0 0 75.17* 16.00 8.00 16.00 0 0 1 31.94 40.09 20.05 40.09 0 1 0 60.14 33.41 16.71 33.41 0 1 1 40.09 25.06 12.55 25.06 1 0 0 50.11 60.14 30.07 60.14 1 0 1 66.48 20.05 10.03 20.05 1 1 0 80.18* 66.48 33.24 66.48 1 1 1 51.90 50.11 25.06 50.11 Clock Tables (using 14.318 MHz input, all frequencies in MHz) FS2 FS1 FS0 -27 2XCPUCLK -42 -43 2XCPUCLK 2XCPUCLK CPUCLK ^ 0 0 0 75* 16 8 16 0 0 1 32 40 20 40 0 1 0 60 33.33 16.67 33.33 0 1 1 40 25 12.50 25 1 0 0 50 60 30 60 1 0 1 66.66 20 10 20 1 1 0 80* 66.66 33.33 66.66 1 1 1 52 50 25 50 Fixed Clock Output Actual Frequencies (using 14.318 MHz input, all freqencies in MHz) 14.318 1.84 24.0 12.0 8.0 Clock Tables in MHz for -04 and -10 (using 14.318 MHz input , all frequencies in MHz) FS(3:0) -04 -10 2XCPU CPU CPUCL- K 0 100* 50* PDCPU 1 80* 40* 40 2 66.6 33.3 50 3 50 25 66.6 44 0 2 0- 53 2 1 6- 62 4 1 2- 71 6 8 - Clock T able for A V9154A-26 (using 14.318 MHz input all frequencies in MHz) FS(2:0) 2XCPU (MHz) CPUCLK (MHz) 0 100.23* 50.11 1 80.18* 40.09 2 66.48* 33.24 3 50.11 25.06 4 40.09 20.05 5 32.22 16.11 6 24.23 12.12 7 15.75 7.88
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stess specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. V DD = 3.3 V ± 10%, TA = 0 - 70 oC unless otherwise stated Electrical Characteristics at 3.3 V Notes: 1. Parameter is guaranteed by design and characterization. DC Characteristics PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Input Low Voltage VIL - - 0.2 VDD V Input High Voltage VIH 0.7 V - - V Input Low Current IIL VIN = 0V (pull-up pin) - 2.5 7.0 A Input High Current IIH V IN = VDD -5.0 - 5.0 A Output Low Voltage VOL IOL = 6mA - 0.05 VDD 0.1 VDD V Output High Voltage 1 VOH IOH = -4mA 0.85 VDD 0.94 VDD - V Output Low Current1 IOL VOL = 0.2VDD 15.0 24 - mA Output High Current1 IOH VOH = 0.7VDD - -13 -8.0 mA Supply Current IDD unloaded, 60 MHz - 16 34 mA Output Frequency Change over Supply and Temperature FD With respect to typical frequency - 0.002 0.01 % Short circuit current1 ISC each output clock 20 30 - mA Input Capacitance1 CI except X1, X2 - - 10 pF Load Capacitance1 CL pins X1, X2 - 20 - pF Pull-up Resistor1 Rpu at VDD - 0.5V - 620 900 k ohm
Electrical Characteristics at 3.3 V V DD = 3.3 V ± 10%, TA = 0 - 70 oC unless otherwise stated Notes: 1. Parameter is guaranteed by design and characterization. Not subject to production testing. AC Characteristics PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Input Clock Rise Time1 tICr - - 20 ns Input Clock Fall Time1 tICf - - 20 ns Rise time, 20% to 80% V DD 1 tr 15pF load - 2.2 3.5 ns Fall time, 80% to 20% V DD 1 tf 15pF load - 1.2 2.5 ns Duty cycle at 50% VDD 1 dt 15pF load 40/60 48/52 60/40 % Duty cycle, reference clocks1 dt 15pF load 50/65 43/57 65/50 % Jitter, one sigma, 20-66 MHz clocks1 tj1s 10,000 cycles - 100 200 ps Jitter, one sigma, clocks below 20 MHz 1 tjls 10,000 cycles - 1.0 2.0 % Jitter, absolute, 20-66 MHz clocks1 tjab 10,000 cycles -350 - 350 ps Jitter, absolute, clocks below 20 MHz 1 tjab 10,000 cycles - 1.5 4.0 % Input Frequency1 fin 2 14.318 32 MHz Maximum Output Frequency1 fout 70 - - MHz Clock skew between CPU and 2XCPU outputs1 T sk AV9154A-42 - 220 500 ps Power-up Time1 ttPO off to 50 MHz - 6 12 ms Frequency Transition Time 1 tft from 8 to 50 MHz - 4.5 10 ms
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Input Low Voltage V IL V DD =5 V - - 0.8 V Input High Voltage V IH V DD =5 V 2.0 - - V Input Low Current I IL V IN=0 V (pull-up pin) - 6 15 A Input High Current I IH V IN = VDD -5 - 5 A Output Low Voltage V OL IOL = 10 mA - 0.15 0.4 V Output High Voltage1 V OH IOH = -30 mA 2.4 3.7 - V Output Low Current1 IOL V OL = 0.8 V 25 45 - mA Output High Current1 IOH V OH = 2.4 V - -53 -35 mA Supply Current I DD unloaded, 66 MHz - 25 50 mA Output Frequency Change over Supply and Temperature1 FD with respect to typical frequency - 0.002 0.01 % Short circuit current
1 ISC each output clock 25 40 - mA
Input Capacitance1 C I except X1, X2 - - 10 pF Load Capacitance1 C L pins X1, X2 - 20 - pF Pull-up Resistor1 R pu A + VDD -1 V - 400 700 k ohm Electrical Characteristics at 5.0 V Notes: 1. Parameter is guaranteed by design and characterization. Not subject to production testing. V DD = +5 ± 10% V , TA = 0 - 70oC unless otherwise stated
Electrical Characteristics at 5.0 V V DD = +5 ±10% V , TA = 0 - 70oC unless otherwise stated AC Characteristics PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Input Clock Rise Time1 tICr - - 20 ns Input Clock Fall Time1 tICf - - 20 ns Output Rise time, 0.8 to 2.0V1 tr 15pF load - 1.5 2 ns Rise time, 20% to 80% V1 tr 15pF load - 2.0 3 ns Output Fall time, 2.0 to 0.8V1 tf 15pF load - 0.5 1.5 ns Fall time, 80% to 20% V1 tf 15pF load - 2.0 3.0 ns Duty cycle at 1.4V1 dt 15pF load, VDD = 5V±5% 45/55 48/52 55/45 % Duty cycle, reference clocks1 dt 15 pF load 40/65 43/57 65/40 % Jitter, one sigma, 20 MHz-
80 MHz clocks1 tj1s 10,000 cycles - 70 140 ps
Jitter, one sigma, clocks below 20 MHz1 tjls 10,000 cycles - 0.8 2.0 % Jitter, absolute, 20 MHz-
80 MHz clocks1 tjab 10,000 cycles -250 - 250 ps
Jitter, absolute, clocks below 20 MHz1 tjab 10,000 cycles - 1.0 3.0 % Input Frequency f in 2 14.318 32 MHz Maximum Output Frequency1 fout 140 - - MHz Clock skew between CPU and 2XCPU outputs1 Tsk AV9154A-42 - 140 400 ps Power-up Time1 ttPO to 80 MHz - 8 15 ms Frequency Transition Time1 tft from 8 to 66.66 MHz - 6.5 12 ms Notes: 1. Parameter is guaranteed by design and characterization. Not subject to production testing.
Example: ICS XXXX-PPP M X#W Lead Count & Package Width Lead Count=1,2, or 3 digits W=0.3" SOIC or 0.6" DIP; None=Standard Width Package Type N=DIP (Plastic), S=SOIC Device Type (consists of 3 or 4-digit numbers) Prefix ICS, AV=Standard Device; GSP=Genlock device Pattern Number (2 or 3-digit number for parts with ROM-code patterns) 0.765 0.130 0.060 0.018 0.100 0.130 0 ~ 5º 0.010 0.260 0.360 0.015min 0.325 16-Pin PDIP Package 0.390 0.031 0.024 0.016 0.050 0.063 0.006±0.004 0.238 0.154 0.008 0.015 0.025 16-Pin SOIC Package