AV9108 ICST | Alldatasheet

Document overview

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Technical content

Features

  • • Ru ns up to 80 MHz at 3.3V
  • • 50/50 typical duty cycle at 5V
  • • ±250ps absolute jitter
  • • G enerates frequencies from 2 to 140 MHz
  • • 2 to 32 MHz input reference frequency
  • • Up to 16 frequencies stored internally
  • • Patented on-chip Phase Locked Loop with V C O for clock generation
  • • Provides reference clock and synthesized clock
  • • On-chip loop filter
  • • Low pow er 0.8µ CMO S technology
  • • 8-pin or 14-pin DIP or SOIC package

Pin Descriptions for AV9108-03, AV9108-05 and AV9108-10 PIN NUMB ER PIN NA M E TY PE D ESCRI PTION-05/-10/-13 -03 1 14 FS0 Input Frequency Select 0 for CLK1 (-03 has pull-up). 5 1 FS1 Input Frequency Select 1 for CLK1 (-03 has pull-up). 2 FS2 Input Frequency Select 2 for CLK1 (-03 has pull-up). 3 FS3 Input Frequency Select 3 for CLK1 (-03 has pull-up). 4 AGND - Ana log GROUND. 2 5 GMD - Digital GROUND. 6 PD Input PO W ER-DO W N . Shuts off chip when low . Internal pull-up. 3 7 X1 /ICLK Input C RYS TA L OUTP U T or INPU T C LOC K frequency. Typically 14.318 M H z system clock. 4 8 X2 O utput C RYS TA L OUT PU T (No Connect wh en clock used.). 9 OE(R EFCLK) Input OUTPU T ENABL E. Tristates R EFCLK wh en low . Pull-up. 10 OE(C LK1) Input OUTPU T ENABL E. Tristates C LK1 wh en low . Pull-up. 6 11 CLK1 O utput CLOCK 1 Ou tput (see decoding tables). 7 12 V D D - Digital powe r supply (+3V DC). 8 13 REFCLK O utput REFER ENC E C LOC K output. Produces a buffered version of the input clock or crystal frequency (typically 14.318 M Hz ). FS0 1 8 RE FCLK GND 2 7 VDD X1/ICLK 3 6 CLK1 X2 4 5 FS1 AV9108-05/-10 8-Pin DIP, SO IC FS1 1 14 FS0 FS2 2 13 RE FCLK FS3 3 12 VDD AG ND 4 11 CLK1 G N D 5 10 O E (CLK1) PD 6 9 O E (REFCLK) X1/ICLK 7 8 X2 AV9108-03/-11 14-Pin DIP, SO IC AV9108

Dec oding Table for AV9108-05, 14.318 input FS1 FS0 CLK1

40.01 MH z

50.11 MHz

66.61 MH z

80.01 MH z

Dec oding Table for AV9108-03, 14.318 input FS3 FS2 FS1 FS0 CLK1

16.00 MHz

39.99 MHz

50.11 MH z

80.01 MHz

66.58 MHz

100.23 M H z

8.02 M H z

4.01 M H z

20.00 MHz

25.06 MHz

40.01 MHz

33.29 MHz

2.05 M H z

Dec oding Table for AV9108-10, 14.318 input FS1 FS0 CLK1

25.057 M Hz

33.289 M Hz

40.006 M Hz

50.113 M H z

Dec oding Table for AV9108-11 (in MH z) FS3 FS2 FS1 FS0 CLK1

16.00 M H z

33.39 M H z

50.11 M H z

80.01 M H z

66.58 M H z

100.23 MHz

60.00 M H z

4.01 M Hz

8.02 M Hz

20.05 M H z

25.06 M H z

39.99 M H z

33.25 M H z

30.00 M H z

No te: The dash num ber following ICS91 08 m ust be included wh en ordering product since it specifies the frequency decoding table being ordered. D ecoding options can be created by a sim ple m etal m ask change. AV9 108

Frequency Accuracy and Calculation The accuracy of the frequencies produced by the ICS91 08 depends on the input frequency and the desired actual output frequency. The form ula for calculating the exact frequency is as follows: AOu tput Frequency = Input Frequency × B wh ere A =2, 3, 4 ... 128, and B =2, 3, 4 ... 32. For exam ple, to calculate the actual output frequency for a video m onitor expecting a 44.900 MH z clock and using a

14.318 MH z input clock, the closest A/B ratio is 69/22, wh ich

gives an output of 44.906 M H z (w ithin 0.02% of the target frequency). Ge nerally, the ICS9 108 can produce frequencies within 0.1% of the desired output. Allowable Input and Output Frequencies The input frequency should be betwe en 2 and 32 MHz and the A/B ratio should not exceed 24. The output should fall in the range of 2-120 MH z. O utput Enable The Output Enable feature tristates the specified output clock pins. This places the selected output pins in a high im pedance state to allow for system level diagnostic testing. Po w er-Dow n If equipped, the pow er-dow n shuts off the specified PLL or entire chip to save current. A few m illiseconds are required to reach full functioning speed from a pow er-down state. Frequency Transitions A key ICS91 08 feature is the ability to provide glitch-free frequency transitions across its output frequency range. The ICS91 08 provides sm ooth transitions betw een any of the two groups of eight frequencies (wh en FS3=0 or FS3=1), so that the device will switch glitch-free betwe en 4-100 MH z and 2-50 MH z. AV9108

A bsolute M aximum R atings Stresses above those listed under Absolute Ma xim um R atings m ay cause perm anent dam age to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not im plied. Exposure to absolute m axim um rating conditions for extended periods m ay affect product reliability. Electrical Characteristics at 5V (Operating V D D = +4.5V to +5.5V ; TA =0°C to 70°C unless otherwise stated) DC Cha racteristics PARAM ETER SY M BOL TES T CONDI TIONS M IN TYP M A X UNI TS Input Low Voltage V IL - - 0.8 V Input High Voltage V IH 2.0 - - V Input Low Current IIL V IN =0V - 6.0 16 µA Input High Current IIH V IN =V DD -2.0 - 2.0 µA Ou tput Low Voltage V OL IO L=10mA - 0.15 0.40 V Ou tput High Voltage, Note 1 V OH IOH =-30m A 2.4 3.25 - V Ou tput Low Cu rrent, No te 1 IOL V O L=0.8V 22.0 35.0 - m A Ou tput High Current, Note 1 IOH V OH =2.0V - -50.0 -35.0 m A Supply Current ICC Un load, 50 M Hz - 18.0 42.0 m A Supply Current ICC (PD low) Un load, Logic Inputs 000 - 38.0 100.0 µA Supply Current ICC (PD low) Un load, Logic Inputs 111 - 14.0 40.0 µA Pull-up Resistor, No te 1 R pu - 380.0 700.0 k ohm s AC Cha racteristics Rise Time 0.8 to 2.0V, No te 1 Tr 15pf load - 0.60 1.40 ns Fall Time 2.0 to 0.8V, N ote 1 Tf 15pf load - 0.40 1.00 ns Rise Time 20% to 80% , No te 1 Tr 15pf load - 2.0 3.5 ns Fall Time 80% to 20%, N ote 1 Tf 15pf load - 1.0 2.5 ns Du ty Cycle, No te 1 D t 15pf load @ 1.4V 45.0 50.0 55.0 % Jitter, O ne Sigm a, No te 1 Tjis From 20 to 100 M H z - 50.0 150.0 ps Jitter, O ne Sigm a, No te 1 Tjis From 14 to 16 MHz 100.0 200.0 ps Jitter, O ne Sigm a, No te 1 Tjis From 14 to B elow 0.2 1.0 % Jitter, A bsolute, No te 1 Tjab From 20 to 100 M H z -250.0 250.0 ps Jitter, A bsolute, No te 1 Tjab From 14 to 16 MHz -500.0 500.0 ps Jitter, A bsolute, No te 1 Tjab From 14 to B elow 1.0 3.0 % Input Frequency, No te 1 Fi 11.0 14.3 19.0 M H z Ou tput Frequency Fo 2.0 - 120.0 M H z Pow er-up Tim e, No te 1 Tpu - 7.58 18.0 m s Transition Time, No te 1 Tft 8 to 66.6 MH z - 6.0 13.0 ms No te 1: Param eter is guaranteed by design and characterization. No t 100% tested in production. AV9 108

Electrical Characteristics at 3.3V (Operating V D D = +3.0V to +3.7V ; TA =0°C to 70°C unless otherwise stated) DC Cha racteristics PARAM ETER SYMBOL TE ST COND ITIONS M IN TYP MAX UN ITS Input Low Voltage V IL - - 0.20V DD V Input High Voltage V IH 0.7V DD - - V Input Low Current IIL V IN =0V - 2.5 7.0 µA Input High Current IIH V IN =V DD -2.0 - 2.0 µA Ou tput Low Voltage V OL IO L=6mA - 0.15 0.1 V Ou tput H igh Voltage V OH IOH =-5m A 0.85 0.92 - V Ou tput Low Cu rrent IOL V O L=0.2V DD 15.0 22.0 - mA Ou tput High Current IOH V O L=0.7V DD - -17.0 -10.0 mA Supply Current ICC Un loaded, 50 M H z - 22.0 40.0 m A Supply Current ICC (PD low) Un load, Logic Inputs 000 - 13.0 40.0 µA Supply Current ICC (PD low) Un load, Logic Inputs 111 - 4.0 12.0 µA Pull-up Resistor R pu - 550.0 900.0 k ohm s AC Cha racteristics Rise Time 20% to 80% , No te 1 Tr 15pf load - 2.2 3.5 ns Fall Time 80% to 20% Tf 15pf load - 1.2 2.5 ns Du ty Cycle D t 15pf load @ 50% 40.0 46.0 60.0 % Jitter, O ne Sigm a Tjis From 25 to 85 MH z - 50.0 150.0 ps Jitter, O ne Sigm a Tjis From 14 to 20 MHz 100.0 200.0 ps Jitter, O ne Sigm a Tjis From 14 to B elow 0.4 1.0 % Jitter, Absolute Tjab From 25 to 85 MH z -250.0 250.0 ps Jitter, Absolute Tjab From 14 to 20 MH z -500.0 500.0 ps Jitter, Absolute Tjab From 14 to B elow 1.0 3.0 % Input Frequency Fi 13.3 14.3 15.3 MHz Ou tput Frequency Fo 2.0 - 90.0 MHz Pow er-up Tim e, No te 1 Tpu - 7.58 18.0 m s Transition Time, No te 1 Tft 8 to 66.6 MH z - 6.0 13.0 ms Paramet er is guaranteed by design and characterization. AV9108

AV9108-XXCN8, ICS9108-XXCN14 Exam ple: XXX XXX X- XX M X#W Lead C ount & Package W idth Lead Count=1, 2 or 3 digits W=.3 ” SOIC or .6” DIP; None=Standard W idth Package Type N=DI P (Plastic) Pattern Nu m ber (2 or 3 digit num ber for parts with R O M code patterns) Dev ice Type (consists of 3 or 4 digit num bers) Prefix ICS, AV =Standard D evice; G SP=Ge nlock D evice AV9 108

ICS9108-XXCS8, IS9108-XXCS14 Exam ple: XXX XXX X- XX M X#W Lead C ount & Package W idth Lead Count=1, 2 or 3 digits W=.3 ” SOIC or .6” DIP; None=Standard W idth Package Type S=SOIC Pattern Nu m ber (2 or 3 digit num ber for parts with R O M code patterns) Dev ice Type (consists of 3 or 4 digit num bers) Prefix ICS, AV =Standard D evice; G SP=Ge nlock D evice AV9108