AT655S28

AT655 POSEICO | Alldatasheet

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PHASE CONTROL THYRISTOR AT655 Repetitive voltage up to 2800 V Mean on-state current 1545 A Surge current 30 kA FINAL SPECIFICATION feb 97 - ISSUE : 03 Symbol Characteristic Conditions Tj [°C] Value Unit BLOCKING V RRM Repetitive peak reverse voltage 125 2800 V V RSM Non-repetitive peak reverse voltage 125 2900 V V DRM Repetitive peak off-state voltage 125 2800 V I RRM Repetitive peak reverse current V=VRRM 125 70 mA I DRM Repetitive peak off-state current V=VDRM 125 70 mA CONDUCTING I T (AV) Mean on-state current 180° sin, 50 Hz, Th=55°C, double side cooled 1545 A I T (AV) Mean on-state current 180° sin, 50 Hz, Tc=85°C, double side cooled 1330 A I TSM Surge on-state current sine wave, 10 ms 125 30 kA I² t I² t without reverse voltage 4500 x1E3 A²s V T On-state voltage On-state current = 2900 A 25 1.8 V V T(TO) Threshold voltage 125 1.05 V r T On-state slope resistance 125 0.290 mohm SWITCHING di/dt Critical rate of rise of on-state current, min. From 75% VDRM up to 1730 A, gate 10V 5ohm 125 200 A/µs dv/dt Critical rate of rise of off-state voltage, min. Linear ramp up to 70% of VDRM 125 500 V/µs td Gate controlled delay time, typical VD=100V, gate source 10V, 10 ohm , tr=.5 µs 25 3 µs tq Circuit commutated turn-off time, typical dV/dt = 20 V/µs linear up to 75% VDRM 320 µs Q rr Reverse recovery charge di/dt=-20 A/µs, I= 1140 A 125 µC I rr Peak reverse recovery current VR= 50 V A I H Holding current, typical VD=5V, gate open circuit 25 300 mA I L Latching current, typical VD=5V, tp=30µs 25 700 mA GATE V GT Gate trigger voltage VD=5V 25 3.5 V I GT Gate trigger current VD=5V 25 300 mA V GD Non-trigger gate voltage, min. VD=VDRM 125 0.25 V V FGM Peak gate voltage (forward) 30 V I FGM Peak gate current 10 A V RGM Peak gate voltage (reverse) 5 V P GM Peak gate power dissipation Pulse width 100 µs 150 W P G Average gate power dissipation 2 W MOUNTING R th(j-h) Thermal impedance, DC Junction to heatsink, double side cooled 21 °C/kW R th(c-h) Thermal impedance Case to heatsink, double side cooled 6 °C/kW T j Operating junction temperature -30 / 125 °C F Mounting force 22.0 / 24.5 kN Mass 520 g ORDERING INFORMATION : AT655 S 28 standard specification VDRM&VRRM/100 Via N. Lorenzi 8 - I 16152 GENOVA - ITALY Tel. int. +39/(0)10 6556549 - (0)10 6556488 Fax Int. +39/(0)10 6442510 Tx 270318 ANSUSE I - ANSALDO Ansaldo Trasporti s.p.a. Unita' Semiconduttori

AT655 PHASE CONTROL THYRISTOR FINAL SPECIFICATION feb 97 - ISSUE : 03 DISSIPATION CHARACTERISTICS SQUARE WAVE DC 180°120° 90° 60° 30° 500 1000 1500 2000 2500 3000 3500 0 500 1000 1500 2000 2500 IF(AV) [A] PF(AV) [W] ANSALDO DC 180°120°90° 60°30° 100 110 120 130 0 500 1000 1500 2000 2500 IF(AV) [A] Th [°C]

AT655 PHASE CONTROL THYRISTOR FINAL SPECIFICATION feb 97 - ISSUE : 03 DISSIPATION CHARACTERISTICS SINE WAVE 180° 120° 90° 60° 30° 500 1000 1500 2000 2500 3000 3500 0 500 1000 1500 2000 2500 IF(AV) [A] PF(AV) [W] ANSALDO 180° 120° 90° 60°30° 100 110 120 130 0 500 1000 1500 2000 2500 IF(AV) [A] Th [°C] ANSALDO

AT655 PHASE CONTROL THYRISTOR FINAL SPECIFICATION feb 97 - ISSUE : 03 Cathode terminal type DIN 46244 - A 4.8 - 0.8 Gate terminal type AMP 60598 - 1 Distributed by ON-STATE CHARACTERISTIC Tj = 125 °C 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 On-state Voltage [V] On-state Current [A] TRANSIENT THERMAL IMPEDANCE DOUBLE SIDE COOLED 0.0 5.0 10.0 15.0 20.0 25.0 0.001 0.01 0.1 1 10 100 t[s] Zth j-h [°C/kW] SURGE CHARACTERISTIC Tj = 125 °C 1 10 100 n° cycles ITSM [kA] ANSALDO All the characteristics given in this data sheet are guaranteed only with uniform clamping force, cleaned and lubricated heatsink, surfaces with flatness < .03 mm and roughness < 2 µm. In the interest of product improvement ANSALDO reserves the right to change any data given in this data sheet at any time without previous notice. If not stated otherwise the maximum value of ratings (simbols over shaded background) and characteristics is reported.