AS8NVC512K32

AS8NVC512K32 AUSTIN | Alldatasheet

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AUSTIN SEMICONDUCTOR, INC. nvSRAMnvSRAMnvSRAMnvSRAMnvSRAM AS8nvC512K32 AS8nvC512K32 Rev. 0.0 08/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. Austin Semiconductor, Inc. ADVANCE INFORMATION 512K x 32 Module nvSRAM 5.0V High Speed SRAM with Non-Volatile Storage AVAILABLE AS MILITARY SPECIFICATIONS

• Military Processing (MIL-STD-883C para 1.2.2)  Temperature Range -55C to 125C

FEATURES

 -55oC to 125 oC Operation  True non-volatile SRAM (no batteries)  20 ns, 25 ns, and 45 ns access times  Automatic STORE on power down with only a small capacitor  STORE to QuantumTrap ® nonvolatile elements initiated by software, device pin, or AutoStore ® on power down  RECALL to SRAM initiated by software or power up  Infinite Read, Write, and Recall cycles  200,000 STORE cycles to QuantumTrap  20 year data retention  Single 5.0V ±10% power supply  Ceramic Hermetic 68 Quad Flatpak -Can order with X7R CAPS on package -Matches compatible pinout footprint of SRAM & EEPROM Module FUNCTIONAL DESCRIPTION The Austin Semiconductor AS8nvC512K32 is a fast static RAM, with a nonvolatile element in each memory cell. The memory is organized as 512K bytes of 8 bits for each of 4 die to form 512Kx32. The embedded nonvolatile elements incorporate QuantumTrap technology, producing the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while independent nonvolatile data resides in the highly reliable QuantumTrap cell. Data transfers from the SRAM to the nonvolatile elements (the STORE operation) takes place automatically at power down. On power up, data is restored to the SRAM (the RECALL operation) from the nonvolatile memory. Both the STORE and RECALL operations are also available under software control. LOGIC BLOCK DIAGRAM 67$7,&5$0 $55$< &2/801,2 &2/801'(& 32:(5 &21752/ 6725(5(&$// &21752/ 4XDWUXP7UDS 6725( 5(&$// 9&& 9&$3 +6% 62)7:$5( '(7(&7 $$ %+( %/( '428 '429 '430 '431 m[1, 2, 3] DQ0-DQ31 (1-4) (1-4)

AUSTIN SEMICONDUCTOR, INC. nvSRAMnvSRAMnvSRAMnvSRAMnvSRAM AS8nvC512K32 AS8nvC512K32 Rev. 0.0 08/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. Austin Semiconductor, Inc. ADVANCE INFORMATION PIN ASSIGNMENT (Top View)

68 Lead CQFP (Q)

CS1\\ OE\\ CS2\\ A17 WE2\\ WE3\\ WE4\\ A18 NC HSB\\ VCAP CS3\\ GND CS4\\ WE1\\ A10 Vcc MILITARY PINOUT/BLOCK DIAGRAM CS CS CS CS M1 VCAP 1 HSB 2 Notes: 1. This pin left open if ordered with capacitors already mounted in package. 2. HSB\\ signal is wired to all 4 die in module. This can be left open if not used. PinName I/OType Description A0–A18 Address InputsUsedtoSelectoneofthe524,288bytesofthenvSRAMforx8Configuration. A0–A17 Address InputsUsedtoSelectoneofthe262,144wordsofthenvSRAMforx16Configuration. DQ0–DQ7 DQ0–DQ15 DQ16ͲDQ23 DQ24ͲDQ31 WE\\1Ͳ4 Input WriteEnableInput,ActiveLOW.WhenselectedLOW,dataontheI/Opinsiswrittentothespecific addresslocation. CE\\1Ͳ4 Input Chip EnableInput,ActiveLOW.WhenLOW,selectsthechip.WhenHIGH,deselectsthechip. OE\\ Input OutputEnable,ActiveLOW.TheactiveLOWOEinputenablesthedataoutputbuffersduringreadcycles. I/OpinsaretriͲstatedondeassertingOEHIGH. VSS Ground Ground fortheDevice.Mustbeconnectedtothegroundofthesystem. VCC PowerSupply Power SupplyInputstotheDevice. HSB\\ Input/Output HardwareStoreBusy(HSB\\).WhenLOWthisoutputindicatesthatahardwarestoreisinprogress.When pulledLOWexternaltothechipitinitiatesanonvolatileSTOREoperation.Aweakinternalpullupresistor keepsthispinHIGHifnotconnected(connectionoptional).AftereachstoreoperationHSB\\isdriven HIGHforshorttimewithstandardoutputhighcurrent. VCAP PowerSupply AutoStoreCapacitor.SuppliespowertothenvSRAMduringpowerlosstostoredatafromSRAMto nonvolatileelements.(leavepinopenifcapsmountedonpackage) NC No Connect No Connect.Thispinisnotconnectedtothedie. Input Input/Output Bidirectional DataI/OLinesfordieM1(DQ0Ͳ7),M2(DQ8Ͳ15),M3(DQ16Ͳ23),M4(DQ24Ͳ31)

AUSTIN SEMICONDUCTOR, INC. nvSRAMnvSRAMnvSRAMnvSRAMnvSRAM AS8nvC512K32 AS8nvC512K32 Rev. 0.0 08/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. Austin Semiconductor, Inc. ADVANCE INFORMATION Hardware RECALL (Power Up) During power up or after any low power condition (VCC< VSWITCH), an internal RECALL request is latched. When VCC again exceeds the sense voltage of VSWITCH, a RECALL cycle is automatically initiated and takes tHRECALL to complete. During this time, HSB is driven LOW by the HSB driver. Software STORE Transfer data from the SRAM to the nonvolatile memory with a software address sequence. The AS8nvC512K32 software STORE cycle is initiated by executing sequential CE controlled read cycles from six specific address locations in exact order. During the STORE cycle an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. After a STORE cycle is initiated, further input and output are disabled until the cycle is completed. Because a sequence of READs from specific addresses is used for STORE initiation, it is important that no other read or write accesses intervene in the sequence, or the sequence is aborted and no STORE or RECALL takes place. To initiate the software STORE cycle, the following read sequence must be performed. 1. Read Address 0x4E38 Valid READ 2. Read Address 0xB1C7 Valid READ 3. Read Address 0x83E0 Valid READ 4. Read Address 0x7C1F Valid READ 5. Read Address 0x703F Valid READ 6. Read Address 0x8FC0 Initiate STORE Cycle The software sequence may be clocked with CE controlled reads or OE controlled reads. After the sixth address in the sequence is entered, the STORE cycle commences and the chip is disabled. HSB is driven LOW. It is important to use read cycles and not write cycles in the sequence, although it is not necessary that OE be LOW for a valid sequence. After the tSTORE cycle time is fulfilled, the SRAM is activated again for the read and write operation. Software RECALL Transfer the data from the nonvolatile memory to the SRAM with a software address sequence. A software RECALL cycle is initiated with a sequence of read operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle, the following sequence of CE controlled read operations must be performed. 1. Read Address 0x4E38 Valid READ 2. Read Address 0xB1C7 Valid READ 3. Read Address 0x83E0 Valid READ 4. Read Address 0x7C1F Valid READ 5. Read Address 0x703F Valid READ 6. Read Address 0x4C63 Initiate RECALL Cycle Internally, RECALL is a two step procedure. First, the SRAM data is cleared; then, the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time, the SRAM is again ready for read and write operations. The RECALL operation does not alter the data in the nonvolatile elements. Mode Selection Notes 7. While there are 19 address lines on the AS8nvC512K32, only the 13 address lines (A 14 - A2) are used to control software modes. Rest of the address lines are don’t care. 8. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvola tile cycle. 13.WE\\ must be HIGH during SRAM read cycles. CE\\1Ͳ4 WE\\1Ͳ4 OE\\13 A15ͲA07 Mode I/O0Ͳ31 Power HXXX N o t Selected Output HighZ Standby L H L X Read SRAM Output Data Active L L X X Write SRAM Input Data Active L H L 0x4E38 Read SRAM Output Data Active8 0xB1C7 Read SRAM Output Data 0x83E0 Read SRAM Output Data 0x7C1F Read SRAM Output Data 0x703F Read SRAM Output Data 0x8B45 AutoStore Output Data Disable

AUSTIN SEMICONDUCTOR, INC. nvSRAMnvSRAMnvSRAMnvSRAMnvSRAM AS8nvC512K32 AS8nvC512K32 Rev. 0.0 08/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. Austin Semiconductor, Inc. ADVANCE INFORMATION Mode Selection (continued) Preventing AutoStore The AutoStore function is disabled by initiating an AutoStore disable sequence. A sequence of read operations is performed in a manner similar to the software STORE initiation. To initiate the AutoStore disable sequence, the following sequence of CE controlled read operations must be performed: 1. Read address 0x4E38 Valid READ 2. Read address 0xB1C7 Valid READ 3. Read address 0x83E0 Valid READ 4. Read address 0x7C1F Valid READ 5. Read address 0x703F Valid READ 6. Read address 0x8B45 AutoStore Disable The AutoStore is re-enabled by initiating an AutoStore enable sequence. A sequence of read operations is performed in a manner similar to the software RECALL initiation. To initiate the AutoStore enable sequence, the following sequence of CE controlled read operations must be performed: 1. Read address 0x4E38 Valid READ 2. Read address 0xB1C7 Valid READ 3. Read address 0x83E0 Valid READ 4. Read address 0x7C1F Valid READ 5. Read address 0x703F Valid READ 6. Read address 0x4B46 AutoStore Enable If the AutoStore function is disabled or re-enabled, a manual STORE operation (hardware or software) must be issued to save the AutoStore state through subsequent power down cycles. The part comes from the factory with AutoStore enabled. Data Protection The AS8nvC512K32 protects data from corruption during low voltage conditions by inhibiting all externally initiated STORE and write operations. The low voltage condition is detected when VCC < VSWITCH. If the AS8nvC512K32 is in a write mode (both CE and WE are LOW) at power up, after a RECALL or STORE, the write is inhibited until the SRAM is enabled after tLZHSB (HSB to output active). This protects against inadvertent writes during power up or brown out conditions. CE\\1Ͳ4 WE\\1Ͳ4 OE\\13 A15ͲA07 Mode I/O0Ͳ31 Power L H L 0x4E38 Read SRAM Output Data Active8 0xB1C7 Read SRAM Output Data 0x83E0 Read SRAM Output Data 0x7C1F Read SRAM Output Data 0x703F Read SRAM Output Data 0x4B46 AutoStore Enable Output Data L H L 0x4E38 Read SRAM Output Data ActiveICC28 0xB1C7 Read SRAM Output Data 0x83E0 Read SRAM Output Data 0x7C1F Read SRAM Output Data 0x703F Read SRAM Output Data 0x8FC0 Nonvolatile Store Output HighZ L H L 0x4E38 Read SRAM Output Data Active8 0xB1C7 Read SRAM Output Data 0x83E0 Read SRAM Output Data 0x7C1F Read SRAM Output Data 0x703F Read SRAM Output Data 0x4C63 Nonvolatile OutputHighZ Recall

AUSTIN SEMICONDUCTOR, INC. nvSRAMnvSRAMnvSRAMnvSRAMnvSRAM AS8nvC512K32 AS8nvC512K32 Rev. 0.0 08/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. Austin Semiconductor, Inc. ADVANCE INFORMATION Best Practices nvSRAM products have been used effectively for over 15 years. While ease-of-use is one of the product’s main system values, experience gained working with hundreds of applications has resulted in the following suggestions as best practices: „ The nonvolatile cells in this nvSRAM product are delivered from Austin Semiconductor with 0x00 written in all cells. Incoming inspection routines at customer or contract manufacturer’s sites sometimes reprogram these values. Final NV patterns are typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End product’s firmware should not assume an NV array is in a set programmed state. Routines that check memory content values to determine first time system configuration, cold or warm boot status, and so on should always program a unique NV pattern (that is, complex 4-byte pattern of 46 E6 49 53 hex or more random bytes) as part of the final system manufacturing test to ensure these system routines work consistently. „ Power up boot firmware routines should rewrite the nvSRAM into the desired state (for example, autostore enabled). While the nvSRAM is shipped in a preset state, best practice is to again rewrite the nvSRAM into the desired state as a safeguard against events that might flip the bit inadvertently such as program bugs and incoming inspection routines. „ The V CAP value specified in this data sheet includes a minimum and a maximum value size. Best practice is to meet this requirement and not exceed the maximum V CAP value because the nvSRAM internal algorithm calculates VCAP charge and discharge time based on this max VCAP value. Customers that want to use a larger VCAP value to make sure there is extra store charge and store time should discuss their V CAP size selection with Austin Semiconductor to understand any impact on the V CAP voltage level at the end of a tRECALL period.

AUSTIN SEMICONDUCTOR, INC. nvSRAMnvSRAMnvSRAMnvSRAMnvSRAM AS8nvC512K32 AS8nvC512K32 Rev. 0.0 08/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. Austin Semiconductor, Inc. ADVANCE INFORMATION Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Maximum Accumulated Storage Time Ambient Temperature with V oltage Applied to Outputs Transient V oltage (<20 ns) on Package Power Dissipation Surface Mount Pb Soldering (per MIL-STD-883, Method 3015) Operating Range Notes 9. Typical conditions for the active current shown on the DC Electrical characteristics are average values at 25°C (room temper ature), and V CC = 5V. Not 100% tested. 10. The HSB\\ pin has I OUT = -8 uA for V OH of 2.4V when both active HIGH and LOW drivers are disabled. When they are enabled standard V OH and VOL are valid. This parameter is characterized but not tested. 11. V CAP (storage capacitor) nominal value is 88 uF total cap. Over the Operating Range (V CC = 5.0V ±10%) Range Ambient Temperature Vcc Military Ͳ55oCto+125oC 5.0V±10% Industrial Ͳ40oCto+85oC 5.0V±10% Parameter Description Min Max Unit Military 450 400 350 mA mA mA Industrial 350 325 275 mA mA mA ICC2 AverageVCCCurrent duringSTORE 60 mA ICC3 AverageVccCurrentat tRC=200ns,5V,25°C typical 220 mA ICC4 AverageVCAPCurrent duringAutoStoreCycle 40 mA ISB VCCStandbyCurrent 40 mA InputLeakageCurrent (exceptHSB\\) Ͳ55 μ A InputLeakageCurrent (forHSB\\) Ͳ400 10 μA IOZ OffͲStateOutput LeakageCurrent Ͳ10 10 μA VIH InputHIGHVoltage 2.2 VCC + 0.3 V VIL InputLOWVoltage VSSͲ 0.3 0.8 V VOH OutputHIGHVoltage 2.4 V VOL OutputLOWVoltage 0.45 V VCAP

11 StorageCapacitor 80 180 μF

tRC=20ns tRC=25ns tRC=45ns Valuesobtainedwithoutoutputloads(IOUT=0mA)ICC1 AverageVCCCurrent AllInputsDon’tCare,VCC=Max AveragecurrentfordurationtSTORE BetweenVCAPpinandVSS,10.0VRated AllI/PcyclingatCMOSlevels. Valuesobtainedwithoutoutputloads(IOUT=0mA). AllInputsDon’tCare,VCC=Max AveragecurrentfordurationtSTORE currentlevelafternonvolatilecycleiscomplete. Inputsarestatic.f=0MHz. IIX VCC=Max,VSSчVINчVCC VCC=Max,VSSчVINчVCC VCC=Max,VSSчVOUTчVCC,CE\\orOE\\шVIHorBHE\\/BLE\\шVIH orWE\\чVIL IOUT=–2mA IOUT=4mA

AUSTIN SEMICONDUCTOR, INC. nvSRAMnvSRAMnvSRAMnvSRAMnvSRAM AS8nvC512K32 AS8nvC512K32 Rev. 0.0 08/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. Austin Semiconductor, Inc. ADVANCE INFORMATION Data Retention and Endurance Capacitance In the following table, the capacitance parameters are listed. 12 Thermal Resistance In the following table, the thermal resistance parameters are listed. 12 AC Test Loads AC Test Conditions Note 12. These parameters are guaranteed but not tested. Parameter Description Test Conditions 44 ͲTSOPII 44 ͲGullwing Unit ȺJA ThermalResistance (JunctiontoAmbient) TBD TBD oC/W ȺJC ThermalResistance (JunctiontoCase) TBD TBD oC/W Testconditionsfollowstandardtestmethods andproceduresformeasuringthermal impedance,inaccordancewithEIA/JESD51. 5.0V OUTPUT 5 pF 789: 5.0V OUTPUT 30 pF 789: for tri-state specs 577: 577: Parameter Description Min Unit DATAR DataRetention 20 Years NVC NonvolatileSTOREOperation 200 Cycles Parameter Description Test Conditions Min Unit CIN InputCapacitance(Addr,OE\\,HSB\\) 50 pF CIN InputCapacitance(CE\\1Ͳ4,WE\\1Ͳ4 20 pF COUT(DQ) I/OCapacitance 25 pF TA=25°C,f=1MHz, VCC=0to3.0V

AUSTIN SEMICONDUCTOR, INC. nvSRAMnvSRAMnvSRAMnvSRAMnvSRAM AS8nvC512K32 AS8nvC512K32 Rev. 0.0 08/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. Austin Semiconductor, Inc. ADVANCE INFORMATION AC Switching Characteristics Switching Waveforms SRAM Read Cycle #1: Address Controlled 13, 14, 17 Address Data Output Address Valid Previous Data Valid Output Data Valid tRC tAA tOHA Notes 13.WE\\ must be HIGH during SRAM read cycles. 14. Device is continuously selected with CE\\, OE\\ LOW. 15.Measured ±200 mV from steady state output voltage. 16. If WE\\ is LOW when CE\\ goes LOW, the outputs remain in the high impedance state. 17. HSB\\ must remain HIGH during read and write cycles. AustinSemi Parameters Alt Parameters Min Max Min Max Min Max tACE tACS ChipEnableAccessTime 20 25 45 ns tRC 13 tRC ReadCycleTime 20 25 45 ns tAA 14 tAA AddressAccessTime 20 25 45 ns tDOE tOE OutputEnabletoDataValid 10 12 20 ns tOHA14 tOH OutputHoldAfterAddressChange 2 2 2 ns tLZCE12,15 tLZ ChipEnabletoOutputActive 2 2 2 ns tHZCE12,15 tHZ ChipDisabletoOutputActive 8 10 15 ns tLZOE12,15 tOLZ OutputEnabletoOutputActive 0 0 0 ns tHZOE12,15 tOHZ OutputDisabletoOutputInactive 8 10 15 ns tPU12 tPA ChipEnabletoPowerActive 0 0 0 ns tPD12 tPS ChipDisabletoPowerStandby 20 25 45 ns tDBE Ͳ ByteEnabletoDataValid 10 12 20 ns tLZBE12 Ͳ ByteEnabletoOutputActive 0 0 0 ns tHZBE12 Ͳ ByteDisabletoOutputInactive 8 10 15 ns tWC tWC WriteCycleTime 20 25 45 ns tPWE tWP WritePulseWidth 15 20 30 ns tSCE tCW ChipEnabletoEndofWrite 15 20 30 ns tSD tDW DataSetuptoEndofWrite 8 10 15 ns tHD tDH DataHoldAfterEndofWrite 0 0 0 ns tAW tAW AddressSetuptoEndofWrite 15 20 30 ns tSA tAS AddressSetuptoEndofWrite 0 0 0 ns tHA tWR AddressHoldAfterEndofWrite 0 0 0 ns tHZWE 12,15,16 tWZ WriteEnabletoOutputDisable 8 10 15 ns tLZWE 12,15 tOW OutputActiveafterEndofWrite 2 2 2 ns tBW Ͳ ByteEnabletoEndofWrite 15 20 30 ns SRAMReadCycle SRAMWriteCycle Parameters

Description

AUSTIN SEMICONDUCTOR, INC. nvSRAMnvSRAMnvSRAMnvSRAMnvSRAM AS8nvC512K32 AS8nvC512K32 Rev. 0.0 08/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. Austin Semiconductor, Inc. ADVANCE INFORMATION SRAM Write Cycle #1: WE\\ Controlled 3, 16, 17,18 Address ValidAddress Data Output Output Data Valid Standby Active High Impedance CE OE BHE, BLE ICC tHZCEtRC tACE tAA tLZCE tDOE tLZOE tDBE tLZBE tPU tPD tHZBE tHZOE SRAM Read Cycle #2: CE\\ and OE\\ Controlled 3, 13, 17 Data Output Data Input Input Data Valid High Impedance Address ValidAddress Previous Data tWC tSCE tHA tBW tAW tPWE tSA tSD tHD tHZWE tLZWE WE BHE, BLE CE Note 18. CE\\ or WE\\ must be >V IH during address transitions.

AUSTIN SEMICONDUCTOR, INC. nvSRAMnvSRAMnvSRAMnvSRAMnvSRAM AS8nvC512K32 AS8nvC512K32 Rev. 0.0 08/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. Austin Semiconductor, Inc. ADVANCE INFORMATION SRAM Write Cycle #2: CE\\ Controlled3, 16, 17, 18 Data Output Data Input Input Data Valid HighI mpedance Address ValidAddress tWC tSD tHD BHE, BLE WE CE tSA tSCE tHA tBW tPWE

AUSTIN SEMICONDUCTOR, INC. nvSRAMnvSRAMnvSRAMnvSRAMnvSRAM AS8nvC512K32 AS8nvC512K32 Rev. 0.0 08/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. Austin Semiconductor, Inc. ADVANCE INFORMATION AutoStore/Power Up RECALL Switching Waveforms AutoStore or Power Up RECALL22 Notes 19. tHRECALL starts from the time V CC rises above V SWITCH. 20. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware Store takes place. 21. On a Hardware STORE, Software Store / Recall, AutoStore Enable / Disable and AutoStore initiation, SRAM operation continues to be enabled for time t DELAY. 22. Read and write cycles are ignored during STORE, RECALL, and while VCC is below V SWITCH. 23. HSB\\ pin is driven HIGH to VCC only by internal 100 kOhm resistor, HSB\\ driver is disabled. VSWITCH VHDIS VVCCRISE tSTORE tSTORE tHHHD tHHHD tDELAY tDELAY tLZHSB tLZHSB tHRECALL tHRECALL HSB OUT Autostore POWER- UP RECALL Read & Write Inhibited (RWI) POWER-UP RECALL Read & Write BROWN OUT Autostore POWER-UP RECALL Read & Write POWER DOWN Autostore Note20 Note20 Note23 Min Max Min Max Min Max tHRECALL PowerUpRECALLDuration 20 20 20 ms tSTORE20 STORECycleDuration 10 10 10 ms tDELAY TimeAllowedtoCompleteSRAMCycle 20 25 25 ns VSWITCH LowVoltageTriggerLevel 3.65 3.65 3.65 V tVCCRISE VCCRiseTime 150 150 150 μs VHDIS HSB\\OutputDriverDisableVoltage 1.9 1.9 1.9 V tLZHSB HSB\\ToOutputActiveTime 5 5 5 μs tHHHD HSB\\HighActiveTime 500 500 500 ns UnitParameters Description 20ns 25 ns 45 ns

AUSTIN SEMICONDUCTOR, INC. nvSRAMnvSRAMnvSRAMnvSRAMnvSRAM AS8nvC512K32 AS8nvC512K32 Rev. 0.0 08/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. Austin Semiconductor, Inc. ADVANCE INFORMATION Software Controlled STORE/RECALL Cycle In the following table, the software controlled STORE and RECALL cycle parameters are listed. 24, 25 Switching Waveforms CE\\ and OE \\Controlled Software STORE/RECALL Cycle25 AutoStore Enable/Disable Cycle Notes 24. The software sequence is clocked with CE\\ controlled or OE\\ controlled reads. 25. The six consecutive addresses must be read in the order listed in the MODE Selection Table. WE\\ must be HIGH during all six consecutive cycles. Min Max Min Max Min Max tRC STORE/RECALLInitiationCycleTime 20 25 45 ns tSA AddressSetupTime 0 0 0 ns tCW ClockPulseWidth 15 25 30 ns tHA AddressHoldTime 0 0 0 ns tRECALL RECALLDuration 200 200 200 μs Parameters Description 20ns 25 ns 45 ns Unit W5& W5& W6$ W&: W&: W6$ W+$ W/=&( W+=&( W+$ W+$ W+$ W'(/$< W6725(W5(&$// W+++' W/=+6% +LJK,PSHGDQFH $GGUHVV $GGUHVV$GGUHVV +6% 6725(RQO\\ '$7$ 5:, gy W5& W5& W6$ W&: W&: W6$ W+$ W/=&( W+=&( W+$ W+$ W+$ W'(/$< $GGUHVV $GGUHVV$GGUHVV '$7$ 5:, W66

AUSTIN SEMICONDUCTOR, INC. nvSRAMnvSRAMnvSRAMnvSRAMnvSRAM AS8nvC512K32 AS8nvC512K32 Rev. 0.0 08/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. Austin Semiconductor, Inc. ADVANCE INFORMATION Truth Table For SRAM Operations HSB\\ should remain HIGH for SRAM Operations. Forx32Configuration CE\\1Ͳ4 WE\\1Ͳ4 OE\\ Inputs /Outputs Mode Power H X X High Z Deselect /PowerDown Standby L H L Data Out(DQ0ͲDQ31) Read Active L H H High Z Output Disabled Active L L X Data In(DQ0ͲDQ31) Write Active

AUSTIN SEMICONDUCTOR, INC. nvSRAMnvSRAMnvSRAMnvSRAMnvSRAM AS8nvC512K32 AS8nvC512K32 Rev. 0.0 08/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. Austin Semiconductor, Inc. ADVANCE INFORMATION Ceramic 68 Quad Flatpak

AUSTIN SEMICONDUCTOR, INC. nvSRAMnvSRAMnvSRAMnvSRAMnvSRAM AS8nvC512K32 AS8nvC512K32 Rev. 0.0 08/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. Austin Semiconductor, Inc. ADVANCE INFORMATION *AVAILABLE PROCESSES Temperature IT = Industrial Temperature Range -40 oC to +85oC XT = Military Temperature Range -55 oC to +125oC

Ordering Information

ASIPartNumber Configuration Package Type Speed Operating Range AS8nvC512K32QCͲ20XT 512K x32 68 QuadFlatpak 20 XT AS8nvC512K32QCͲ25XT 512K x32 68 QuadFlatpak 25 XT AS8nvC512K32QCͲ45XT 512K x32 68 QuadFlatpak 45 XT AS8nvC512K32QͲ20XT 512K x32 68 QuadFlatpak 20 IT AS8nvC512K32QͲ25XT 512K x32 68 QuadFlatpak 25 IT AS8nvC512K32QͲ45XT 512K x32 68 QuadFlatpak 45 IT QC=Capacitors&resistorsmountedonpackage Q=Nocapacitororresistor

AUSTIN SEMICONDUCTOR, INC. nvSRAMnvSRAMnvSRAMnvSRAMnvSRAM AS8nvC512K32 AS8nvC512K32 Rev. 0.0 08/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. Austin Semiconductor, Inc. ADVANCE INFORMATION DOCUMENT TITLE 512K x 32 nvSRAM 5.0V High Speed SRAM with Non-Volatile Storage

REVISION HISTORY

Rev # History Release Date Status

0.0 Document Creation August 2009 Advance