AS8F2M32 AUSTIN | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 12
Technical content
AUSTIN SEMICONDUCTOR, INC. FLASHFLASHFLASHFLASHFLASH AS8F2M32 AS8F2M32 Rev. 2.5 05/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. Austin Semiconductor, Inc. FIGURE 1: PIN ASSIGNMENT (Top View)
68 Lead CQFP
- Military Processing (MIL-STD-883C para 1.2.2) Temperature Range -55C to 125C
FEATURES
Fast access times of 90ns, 120ns, and 150ns 5.0V ±10%, single power supply operation Low power consumption(TYP): 4µA CMOS stand-by * TYP ICC(active) <120mA for READ/WRITE 20 year DATA RETENTION Minimum 1,000,000 Program/Erase Cycles per sector guaranteed 32 equal sectors of 64 Kbytes each Any combination of Sectors can be Erased Group Sector Protection Supports FULL Chip Erase Compatible with JEDEC standards Embedded Erase and Program Algorithms Data\\ Polling and Toggle bits for detection of program or erase cycle completion. Erase Suspend/Resume Hardware Reset pin (RESET\\) Built in Decoupling Caps and Multiple Ground Pins for Low Noise Operation Separate Power and Ground Planes to improve noise immunity OPTION MARKING Timing 90ns -90 120ns -120 150ns -150 Packages Ceramic Quad Flat Pack (0.88" sq) Q - MAX height .140" - Stand-off Height .035" min GENERAL DESCRIPTION The Austin Semiconductor, Inc. AS8F2M32 is a 64 Mbit, 5.0 volt- only Flash memory. This device is designed to be programmed in- system with the standard system 5.0 volt VCC supply. The AS8F2M32 offers an access time of 90ns, allowing high-speed microprocessors to operate without wait states. To eliminate bus contention, the device has separate chip enable (CE\\), write enable (WE\\) and output enable (OE\\) controls. The device requires only a single 5.0 volt power supply for both read and write functions. internally generated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC single-power-supply FLASH standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-matching that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reaching data out of the device is similar to reading from other FLASH or EPROM devices. Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm - an internal algorithm that automatically time the program pulse widths and verifies proper cell margin. Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm - an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by observing the RY/BY\\ pin, or by reading the DQ7 (DATA\\ Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. (continued on page 2) For more products and information please visit our web site at www.austinsemiconductor.com
AUSTIN SEMICONDUCTOR, INC. FLASHFLASHFLASHFLASHFLASH AS8F2M32 AS8F2M32 Rev. 2.5 05/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. Austin Semiconductor, Inc. GENERAL DESCRIPTION (cont.) The Sector Erase Architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware Data Protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The Hardware Sector Protection feature disables both program and erase operations in any combinations of the sectors of memory. This can be achieved via programming equipment. The Erase Suspend feature enables the user to put erase on hold for any period of time to read data form, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The Hardware RESET\\ pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET\\ pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the FLASH memory. The system can place the device into the standby mode. Power consumption is greatly reduced in this mode. FIGURE 2: FUNCTIONAL BLOCK DIAGRAM PIN DESCRIPTION PIN DESCRIPTION I/O0-31 Data Inputs/Outputs A0-20 Address Inputs WE\\1-4 Write Enables CS\\1-4 Chip Selects OE\\ Output Enable VCC Power Supply GND Ground RESET\\ Reset WE1\\, CS1\\W E 2\\, CS2\\W E 3\\, CS3\\W E 4\\, CS4\\ RESET\\ OE\\ A0 - A20 2M x 8 2M x 8 2M x 8 2M x 8 8 8 8 8 I/O0-7 I/O8-15 I/O16-23 I/O24-31
AUSTIN SEMICONDUCTOR, INC. FLASHFLASHFLASHFLASHFLASH AS8F2M32 AS8F2M32 Rev. 2.5 05/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. Austin Semiconductor, Inc. *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Expo- sure to absolute maximum rating conditions for extended pe- riods may affect reliability. **Junction temperature depends upon package type, cycle time, loading, ambient temperature and airflow, and humidity (plastics). ABSOLUTE MAXIMUM RATINGS* V oltage on any pin relative to VSS, VT ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS DESCRIPTION CONDITIONS SYMBOL MIN MA X UNITS Input Leakage Current VCC = 5.5, VIN = GND to VCC ILI -10 10 µA Output Leakage Current VCC = 5.5, VIN = GND to VCC ILOx32 -10 10 µA VCC Active Current for Read CS\\ = V IL, OE\\ = VIH ICC1 160 mA VCC Active Current for Program or Erase CS\\ = V IL, OE\\ = VIH ICC2 240 mA VCC CMOS Standby VCC = 5.5V, All Inputs @ VCC - 0.2V or VSS +0.2V, RESET\\ = CS\\1-4 = VCC -0.2V ISB 4m A VCC Standby Current V CC = 5.5, CS\\ = VIH, RESET\\ = VCC ± 0.3V, f=0 I CC3 8m A Output Low Voltage IOL = 12.0 mA, VCC = 4.5 V OL 0.45 V Output High Voltage IOH = -2.5 mA, VCC = 4.5 V OH 0.85 x VCC V Low VCC Lock-Out Voltage V LKO 3.2 4.2 V PARAMETER SYMBOL MIN TYP MA X UNIT Supply Voltage VCC 4.5 5.0 5.5 V Ground VSS 000V Input High Voltage VIH 2.2 --- VCC + 0.5 V Input Low Voltage VIL -0.5 --- +0.8 V CAPACITANCE (TA = +25°C)* PARAMETER SYM CONDITIONS MA X UNITS OE\\ COE 50 pF WE\\1-4 CWE 50 pF CS\\1-4 CCS 20 pF Data I/O CI/O 20 pF Address input CAD 50 pF VIN = 0V, f = 1.0 MHz *Parameter is guaranteed, but not tested.
AUSTIN SEMICONDUCTOR, INC. FLASHFLASHFLASHFLASHFLASH AS8F2M32 AS8F2M32 Rev. 2.5 05/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. Austin Semiconductor, Inc. ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS MIN MAX MIN MAX MIN MAX Write Cycle Time tAVAV tWC 90 120 150 ns Chip Select Setup Time tELWL tCS 000 n s Write Enable Pulse Width tWLWH tWP 45 50 50 ns Address Setup Time tAVWL tAS 000 n s Data Setup Time tDVWH tDS 45 50 50 ns Data Hold Time tWHDX tDH 000 n s Address Hold Time tWLAX tAH 45 50 50 ns Write Enable Pulse Width High tWHWL tWPH 20 20 20 ns Duration of Byte Progreamming Operation1 tWHWH1 300 300 300 µs Sector Erase2 tWHWH2 15 15 15 sec Read Recovery Time before Write tGHWL 000 µ s VCC Setup Time t VCS 50 50 50 µs Chip Programming Time3 44 44 44 sec Chip Erase Time4 256 256 256 sec Output Enable Hold Time5 tOEH 10 10 10 ns RESET\\ Pulse Width tRP 500 500 500 ns Read Cycle Time tAVAV tRC 90 120 150 ns Address Access Time tAVQV tACC 90 120 150 ns Chip Select Access Time tELQV tCE 90 120 150 ns Output Enable to Output Valid tGLQV tOE 40 50 55 ns Chip Select High to Output High6 tEHQZ tDF 20 30 35 ns Output Enable High to Output High6 tGHQZ tDF 20 30 35 ns Output Hold from Adresses, CS\\ or OE\\ Change, whichever is First tAXQX tOH 000 n s RST Low to Read Mode6 tReady 20 20 20 µs Write Cycle Time tAVAV tWC 90 120 150 ns Write Enable Setup Time tWLEL tWS 000 n s Chip Select Pulse Width tELEH tCP 45 50 50 ns Address Setup Time tAVEL tAS 000 n s Data Setup Time tDVEH tDS 45 50 50 ns Data Hold Time tEHDX tDH 000 n s Address Hold Time tELAX tAH 45 50 50 ns Chip Select Pulse Width High tEHEL tCPH 20 20 20 ns Duration of Byte Progreamming Operation1 tWHWH1 300 300 300 µs Sector Erase Time2 tWHWH2 15 15 15 sec Read Recovery Time tGHEL 000 µ s Chip Programming Time3 44 44 44 sec Chip Erase Time4 256 256 256 sec Output Enable Hold Time5 tOEH 10 10 10 ns CS\\ CONTROLLED (WRITE/ERASE/PROGRAM OPERATIONS) UNITS WE\\ CONTROLLED (WRITE/ERASE/PROGRAM OPERATIONS) READ-ONLY OPERATIONS SYM -90 -120 -150PARAMETER
AUSTIN SEMICONDUCTOR, INC. FLASHFLASHFLASHFLASHFLASH AS8F2M32 AS8F2M32 Rev. 2.5 05/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. Austin Semiconductor, Inc. FIGURE 9: Alternate CS\\ Controlled Programming Operation Timings NOTES: 1. PA is the address of the memory location to be programmed. 2. PD is the data to be programmed at byte address. 3. D 7\\ is the output of the complement of the data written to each chip. 4. DOUT is the output of the data written to the device. 5. Figure indicates last two bus cycles of four bus cycle sequence.
AUSTIN SEMICONDUCTOR, INC. FLASHFLASHFLASHFLASHFLASH AS8F2M32 AS8F2M32 Rev. 2.5 05/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. Austin Semiconductor, Inc. MECHANICAL DEFINITION ASI Case #703 (Package Designator QW) NOTES: 1. Dimensions are shown as millimeters(inches).
AUSTIN SEMICONDUCTOR, INC. FLASHFLASHFLASHFLASHFLASH AS8F2M32 AS8F2M32 Rev. 2.5 05/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. Austin Semiconductor, Inc. MECHANICAL DEFINITIONS* (Package Designator QT)
AUSTIN SEMICONDUCTOR, INC. FLASHFLASHFLASHFLASHFLASH AS8F2M32 AS8F2M32 Rev. 2.5 05/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. Austin Semiconductor, Inc.
ORDERING INFORMATION
*AVAILABLE PROCESSES Temperature IT = Industrial Temperature Range -40 oC to +85oC XT = Extended Temperature Range -55 oC to +125oC MIL = MIL-STD-883C para 1.2.2 Processing -55 oC to +125oC NOTE: QW package is planned future offering Device Number Package Type Speed ns Process AS8F2M32 QW - 90 /* AS8F2M32 QW - 120 /* AS8F2M32 QW - 150 /* Device Number Package Type Speed ns Process AS8F2M32 Q - 90 /* AS8F2M32 Q - 120 /* AS8F2M32 Q - 150 /* EXAMPLE: AS8F2M32QW-120/XT EXAMPLE: AS8F2M32QT-90/MIL
AUSTIN SEMICONDUCTOR, INC. FLASHFLASHFLASHFLASHFLASH AS8F2M32 AS8F2M32 Rev. 2.5 05/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. Austin Semiconductor, Inc. DOCUMENT TITLE 64Mb, 2M x 32 Flash Memory Module
REVISION HISTORY
Rev # History Release Date Status