AS8650 AMSCO | Alldatasheet
Document overview
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- PDF pages: 46
Technical content
Datasheet sections
- 1 General Description
- 2 Key Features
- 3 Applications
- 4 Pin Assignments
- 4.1 Pin Descriptions
- 5 Absolute Maximum Ratings
- 6 Electrical Characteristics
- 6.1 Electrical System Specification
- 6.2 DCDC Converter
- 6.3 Low Drop Out Regulators
- 6.4 CAN Transceiver
- 6.4.1 Timing Diagrams
- 6.5 Undervoltage Detection
- 7 Detailed Description
- 7.1 Operating Modes and States
- 7.1.1 Normal Mode
- 7.1.2 Receive-only Mode
- 7.1.3 Standby Mode
- 7.1.4 Sleep Mode
- 7.2 Power Management Strategy
- 7.3 State Diagram
- 7.4 Initialization Sequence
- 7.5 DCDC Converter
- 7.6 Voltage Regulator LDO1
- 7.7 Voltage Regulator LDO2
- 7.8 Voltage Regulator LDO3
- 7.9 Over-Temperature Monitor
- 7.10 Undervoltage Reset
- 7.11 Reset Block
- 7.12 CAN Transceiver
- 7.12.1 BUS Driver
- 7.12.2 Normal Receiver
- 7.12.3 Low Power Receiver
- 7.12.4 Operating Modes
- 7.12.5 Local Wake-up Event
- 7.12.6 Remote Wake-up
- 7.13 Internal Flags
- 7.13.1 VSUP_UV_flag
- 7.13.2 VSUP_POK_flag
- 7.13.3 V5V_UV_flag
- 7.13.4 V5V_POK_flag
- 7.13.5 VLDO2_UV_flag
- 7.13.6 VLDO2_POK_flag
- 7.13.7 VLDO3_UV_flag
- 7.13.8 VLDO3_POK_flag
1 General Description
wake-up via remote wake-up at CAN bus lines and a local wake pin. status flags can be accessed with the SPI interface. The product is available in a 36-pin QFN (6x6x0.9) package.
2 Key Features
3 Applications
(LIN interface) in order to change from CAN to LIN easy. Figure 1. AS8650 Block Diagram
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4 Pin Assignments
Figure 2. Pin Assignments (T op View)
4.1 Pin Descriptions
Table 1. Pin Descriptions
6 WAKE
9 GND_CAN Power Supply Input Power supply
10 SPLIT Analog Input / Output high-voltage Common-mode stabilization output
11 I2C_EN Digital Input I2C/SPI select signal (High = I2C, Low = SPI)
12 SDAI2C / SDISPI
13 SDOSPI Digital Output SPI data out
14 SCLKI2C / SCLKSPI
15 CSSPI Digital input with pull-up SPI chip select
16 RxD Digital output with pull-up CAN Transceiver receive signal
18 TxD Digital input with pull-up CAN Transceiver transmit signal
19 RESET Digital Output Digital Output referenced to VLDO1, active low
23 VLDO1 Power Supply Input Regulated voltage output
24 VLDO1FB Pin with Digital / Analog Input /
25 VLDO2 Power Supply Input Regulated voltage output
26 VLDO2FB Pin with Digital / Analog Input /
27 VLDO3FB Regulated voltage feedback
28 VLDO3
29 V5V_LDO1 Step-down converter 5V output, supply for LDO1
30 V5V_LDO3 Step-down converter 5V output, supply for LDO3
31 V5V_LDO2 Step-down converter 5V output, supply for LDO2
32 FB (DCDC) Analog Input DCDC output voltage feedback
5 Absolute Maximum Ratings
maximum rating conditions for extended periods may affect device reliability. Table 2. Absolute Maximum Ratings1
- All voltages mentioned above are referred with respect to ground reference voltage V GND.
6 Electrical Characteristics
Table 3. Electrical Characteristics CAN dominant, not production tested.
6.1 Electrical Syst em Specification
6.2 DCDC Converter
-40°C < TJ < 150°C; all voltages are with respect to ground, normal operating mode, unless otherwise mentioned. Table 4. Electrical System Specification
6.3 Low Drop Out Regulators
voltage regulator, which provides a regulated (band-gap stabilized) output voltage from the DCDC converter output voltage (V5V). Table 6. VLDO11 Block Specifications
- Please note that the VLDO1 is not programmable.
IOUTLDO1 Output current Guaranteed by design. Table 7. VLDO21 Block Specifications IOUTLDO2 Output current Guaranteed by design.
6.4 CAN Transceiver
6V < VSUP < 18V; -40°C < Tj < 150ºC; all voltages are with respect to ground; 4.75V < V5V_LDO1 < 5.25V; RL=60Ω. Table 8. VLDO31 Block Specifications IOUTLDO3 Output current Guaranteed by design. Table 9. DC Electrical Characteristics
Table 10. AC Electrical Characteristics Table 11. T emperature Limiter
6.4.1 Timing Diagrams
Figure 3. Timing Diagram and Hysteresis of CAN Receiver
6.5 Undervoltage Detection
Table 12. Undervoltage Detection VSUP_POKTH VSUP undervoltage threshold off VSUP rising edge.
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7 Detailed Description
The AS8650 consists of the following components on chip: DCDC converter with 5V outputs that supplies the three LDO voltage regulators and the CAN Transceiver One voltage regulator for 3.3V output voltage and two programmable voltage regulators in the range of 3.3V to 1.8V CAN bus Transceiver according to ISO 11898 Integrated RESET unit with a power-on-reset delay and a programmable watchdog time
7.1 Operating Modes and States
The AS8650 provides four main operating modes normal, receive only, standby, and sleep. In normal mode, the CAN Transceiver can be disabled in case of over-temperature condition. The detailed transition table for each mode is shown in the subsequent pages.
7.1.1 Normal Mode
In normal mode DCDC converter, the three voltage regulators, BUS Transceiver, and Window Watchdog are turned on with full functionality. All the LDO regulators are capable of delivering maximum load current possible as per their respective ratings. The BUS Transceiver is capable of sending the TxD data from the microcontroller to the CANH at the maximum rate.
7.1.2 Receive-only Mode
In this mode, the CAN transmitter is disabled. The CAN receiver, the three voltage regulators, and over-temperature monitor circuit are enabled.
7.1.3 Standby Mode
This is the mode after power up. The Standby mode is a functional low-power mode where the CAN Transceiver is disabled. The bus wake-up (low power receiver) circuit, LDO1, and over-temperature monitor circuit are enabled. Both LDO2 and LDO3 can be enabled or disabled (default state) using the host command. The AS8650 can enter normal mode, sleep mode or receive only mode through host command.
7.1.4 Sleep Mode
Sleep mode is the current saving mode that is entered by host command or by over-temperature condition. The DCDC converter, the three voltage regulators, CAN Transceiver, the reset, and window watchdog unit are all switched off. The bus wake-up (low power receiver) circuit, oscillator, and over-temperature monitor circuit are active. The bus is in recessive state (high). The only wake-up possible is through remote wake-up (through the bus lines) or local wake up (through the WAKE pin) as described in the WAKE specification. In the case of entering sleep mode due to over-temperature condition (T > Tjshut), the device can come out of sleep only after the temperature falls back below the return temperature Tjrecv and any one of the wake up events mentioned above.
7.2 Power Management Strategy
The detailed block diagram and the power management strategy are shown in Figure 4. Internal Regulator. This module is powered externally by the VSUP. All the critical modules that needs to be kept always on, work on this supply. Some of the important modules among them are Over-temperature monitor, Local Wake block, Internal Power-on Reset module, Internal Oscillator, complete mode-control unit, Undervoltage comparators of three external LDOs. DCDC Converter. This is the main supply regulator for all the internal blocks. A step-down hysteretic buck converter is used to generate 5V output from VSUP. This 5V output is then used to generate all the three LDOs. This high-efficiency step-down DCDC converter contains the following features: Current limited operation Thermal shutdown LDO1. This is the main I/O supply. This is generated internally from the 5V DCDC converter output and gives a regulated 3.3V output to power- up the external micro-controller. All the I/Os that interface with the micro-controller work on this supply. LDO2 and LDO3. These are two regulators that are generated from the 5V DCDC converter output. Both the LDOs can be programmed via I2C or SPI settings in the range from 3.3V to 1.8V.
Figure 4. Power Management Strategy
Table 13. Power Management Strategy for AS8650
- Can be turned ON using Device configuration register
- Can be turned OFF using Device Configuration register
7.3 State Diagram
Figure 5. State Machine Model
7.4 Initialization Sequence
VSUP of the order of 0.5V/min.
The power initialization sequence diagram is shown in Figure 6. be activated with the V5V_POK set. register setting for the LDO1 is read. Consequently the output voltage will be regulated to the actual OTP settings. After entering Stand-by mode the host controller can switch the device in any operation mode through the I2C or SPI interface. Figure 6. Initialization Sequence
6 Cycles of
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7.5 DCDC Converter
The high-efficiency, high-voltage, hysteretic step-down DCDC converter, operates in asynchronous mode and delivers 500mA of output load to drive the three internal LDOs and the CAN Transceiver. The low-power architecture extends hold-up time in battery-backed and critical applications where maximum up-time over a wide input supply voltage range is needed, while still providing for high efficiencies of up to 90% during peak current demands.
7.6 Voltage Regulator LDO1
The stability of the voltage output is below ±2.5% over the full input range and temperature for load current up to 100 mA at 3.3V. Power Input to this LDO is the V5V_LDO1 pin. This LDO is activated in Normal, Receive only or Standby mode. It is switched OFF in Sleep mode.
7.7 Voltage Regulator LDO2
The stability of the voltage output is below ±2.5% over input range and temperature for load current up to 100 mA. The voltage regulator is programmable between 3.3V and 1.8V via I2C or SPI interface. Power Input to this LDO is the V5V_LDO2 pin. LDO2 is activated in Normal and Receive Only mode.
7.8 Voltage Regulator LDO3
The stability of the voltage output is below ±2.5% over input range and temperature for load current up to 100 mA. The voltage regulator is programmable between 3.3V and 1.8V via I2C or SPI interface. Power Input to this LDO is the V5V_LDO3 pin. LDO3 is activated in Normal and Receive Only mode.
7.9 Over-Temperature Monitor
In Normal mode, if the junction temperature reaches the over-temperature threshold Tjwarn, a warning flag is set in the diagnostic register which can be accessed via the I2C and the SPI interface and an interrupt is signalled on INTN pin. The CAN transmitter is disabled and the device remains in Normal mode. If the junction temperature falls below Tjrecv, the CAN transmitter is enabled. The warning flag is cleared in the diagnostic register and an interrupt is signalled at the INTN pin. If the junction temperature exceeds the over-temperature threshold Tjshut, the device enters sleep mode irrespective of the current mode and bus wake receiver (Low power receiver) is disabled. As soon as the temperature falls below Tjrecv, the bus wake receiver (Low power receiver) is switched on.
7.10 Undervoltage Reset
Undervoltage on VSUP (Brown out Indication). If VSUP voltage falls below VSUP_UVTH threshold, the VSUP_UV_flag is set and an interrupt at INTN is generated. In this case the device enters into the Stand-by mode. The LDO1 voltage regulator remains activated. Two scenarios are possible at this stage: VSUP is recovering: If VSUP exceeds the VSUP_POKTH threshold, the VSUP_POK_flag is set and the device remains in Stand-by mode. VSUP is still falling: In this case the device continues to stay in Stand-by mode. If voltage falls below VSUP_RESET threshold, then the device enters Power-Off and the logic is reset. Undervoltage on V5V. If the V5V falls below V5V_UVTH threshold, the V5V_UV_flag is set. Once V5V returns to V5V_POKTH threshold value, V5V_POK_flag is set. In case a flag is set, an interrupt is generated at the INTN pin. If undervoltage on V5V occurs in Normal or Receive only modes then CAN Transceiver is disabled and the device remains in its operation mode. Undervoltage on LDO1. If the voltage level of LDO1 falls below the VLDO1_UVTH threshold value and device is not in Sleep mode, the device enters into power-up state while RESET signal is asserted and the voltage regulator is still active. Once the VLDO1_POKTH threshold is reached, RESET signal is de-asserted after reset timeout period and device enters into Standby mode. Undervoltage on LDO2. If the voltage level of the LDO2 falls below the VLDO2_UVTH threshold value a VLDO2_UV_flag is set. An indication is given to microcontroller by setting a bit in interrupt register and giving interrupt on INTN pin. Once VLDO2 returns to VLDO2_POKTH threshold value, VLDO2_POK_flag is set. An indication is given to microcontroller by setting a bit in interrupt register and giving interrupt on INTN pin. Undervoltage on LDO3. If the voltage level of the LDO3 falls below the VLDO3_UVTH threshold value a VLDO3_UV_flag is set. An indication is given to microcontroller by setting a bit in interrupt register and giving interrupt on INTN pin. Once VLDO3 returns to VLDO3_POKTH threshold value, VLDO3_POK_flag is set. An indication is given to microcontroller by setting a bit in interrupt register and giving interrupt on INTN pin.
Figure 7. Power-up and Undervoltage Sequence
7.11 Reset Block
reset unit which in-turn generates a reset signal. Figure 8. Reset Block Functional Waveform
7.12 CAN Transceiver
7.12.1 BUS Driver
7.12.2 Normal Receiver
It relays the data from the CAN bus to the microcontroller in Normal mode.
7.12.3 Low Power Receiver
It relays the data from the CAN bus to the microcontroller in low power mode state.
7.12.4 Operating Modes
Normal Mode. In this mode the Transceiver is able to send and receive data signals on the bus. RxD reflects the bus data. Receive Only Mode. In this mode the Transceiver has the same behavior as in normal mode but the transmitter is disabled. the remote wake up detector output; WAKE_LOCAL reflects the input signal on WAKE pin.
7.12.5 Local Wake-up Event
ground using external resistor on power up. For valid wake-up, the WAKE pin needs a rising edge. Table 14. Operating Modes
Figure 9. Wake Input Pin Behavior
7.12.6 Remote Wake-up
differential voltage on the bus becomes dominant for longer than t_BUS_WR, WAKE_REMOTE falls down as shown in Figure 10. Figure 10. Remote Wake-up Event wake detection circuit is active in sleep and standby modes. The wake message pattern is shown in Figure 11.
Figure 11. Wake Message Pattern
7.13 Internal Flags
The AS8650 supports internal flags to indicate the failures in the system. If any of these flag is set an interrupt is generated on INTN pin.
7.13.1 VSUP_UV_flag
7.13.2 VSUP_POK_flag
threshold, this flag is set. This indicates the microcontroller that undervoltage condition on battery is cleared.
7.13.3 V5V_UV_flag
7.13.4 V5V_POK_flag
this flag is set. This indicates the microcontroller that undervoltage condition on DCDC converter is cleared.
7.13.5 VLDO2_UV_flag
above VLDO2_POKTH threshold the VLDO2_UV_flag is reset.
7.13.6 VLDO2_POK_flag
threshold this flag is set. This indicates the microcontroller that undervoltage condition on LDO2 is cleared.
7.13.7 VLDO3_UV_flag
above VLDO3_POKTH threshold the VLDO3_UV_flag is reset.
7.13.8 VLDO3_POK_flag
threshold this flag is set. This indicates the microcontroller that undervoltage condition on LDO3 is cleared.
7.13.9 BUS Wake_up Flag
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7.13.10 Local Wake_up Flag
The Local Wake_up flag is set when the device detects a local wake-up request on WAKE pin. A local wake-up request is detected when a logic state change on pin WAKE as shown in Figure 9. This indicates the microcontroller about the local wake event.
7.13.11 OVT_Warning Flag
The OVT_Warning flag is set when temperature exceeds Tjwarn. This indicates the microcontroller about temperature exceeding warning levels.
7.13.12 OVT_Recover Flag
The OVT_Recover flag is set when temperature falls back below Tjrecv. This indicates the microcontroller about temperature falling back below recovery levels.
7.13.13 Bus Failure Flags
The bus failure flag is set if the CAN Transceiver detects a bus line short-circuit condition to VSUP, V5V_LDO1 or GND. Such possible conditions are indicated to microcontroller through these flags. All these flags are cleared on microcontroller read. If the fault condition still exist after microcontroller read, the particular flag is set again. The device still be working in the current state. The microcontroller takes appropriate action on reading of these flags. CANH_short_GND. This flag indicates Over Current condition on pin CANH. For example short to ground on pin CANH. When the output current on pin CANH exceeds the threshold OC_CANH_th then the output OC_CANH switches on high level after a filter time t_OC_CANH. CANH_short_VSUP . This flag indicates Low Current on pin CANH. For example open load or short to VSUP on pin CANH. When the output current on pin CANH falls below the threshold LC_CANH_th then the output LC_CANH switches on high level after a filter time t_LC_CANH. CANL_short_VSUP . This flag indicates Over Current on pin CANL. For example short to VSUP on pin CANL. When the output current on pin CANL exceeds the threshold OC_CANL_th, then the output OC_CANL switches on high level after a filter time t_OC_CANL. CANL_short_GND. This flag indicates Low Current on pin CANL. For example open load or short to ground on pin CANL. When the output current on pin CANL falls the threshold LC_CANL_th then the output LC_CANL switches on high level after a filter time t_LC_CANL.
7.13.14 Local Failure Flags
The AS8650 prevents the system from four kinds of local failures without disturbing the BUS network. The four failures are TxD dominant clamping, RxD recessive clamping, TxD & RxD short, and bus dominant clamping. All these failures are indicated to microcontroller through flags. TxD_Dom_Clamp flag. A permanent LOW-level on pin TxD (due to a hardware or software application failure) would drive the BUS into a permanent dominant state, blocking BUS network communication. If pin TxD remains at a LOW level for longer than the TxD dominant time-out period TTxDC(dom), the device disables the transmitter of BUS Transceiver and TxD_Dom_Clamp flag is set. The device prevents such BUS network lock-up by disabling the transmitter of the Transceiver. The device will not change the functional state. The transmitter remains disabled until the local failure flag is cleared by host command. The flag is cleared on microcontroller read. RxD_Rec_Clamp flag. If pin RxD is shorted to VLDO1, the RxD pin is permanently clamped to recessive state. The BUS controller can not see the bus dominant state and start sending message thinking bus is idle. This disturbs the BUS. This RxD recessive clamping is detected by the device when BUS is at dominant state. On detection of this a failure RxD_Rec_Clamp flag is set and the transmitter is disabled. The flag is cleared on microcontroller read. The transmitter is enabled by host command. TxD_RxD_Short flag. The TxD_RxD short circuit would result in a dead-lock situation clamping the bus dominant. For example the Transceiver receives a dominant signal, RxD outputs a dominant level. Because of the short circuit, TxD reflects a dominant signal, retaining the dominant bus state. As a result TxD and the bus are clamped continuously dominant. The resulting effect is the same as for the continuously clamped dominant TxD signal. The TxD dominant timeout interrupts the deadlock situation by disabling the transmitter and the TxD_RxD short condition is differentiated. The bus becomes recessive again and TxD will be recessive if it is not driven by microcontroller. However, the failure scenario may still exist and with the next dominant signal on the bus the described procedure will start again. The device keeps the transmitter off after detection of TxD_RxD short fault and keeps updating this flag status. The microcontroller has to send 2 consecutive low pulses of duration 500ns with high period of 500ns in-between, in regular intervals to check short circuit recovery. This way a local TxD/RxD short circuit will not disturb the communication of the remaining bus system. BUS_Dom_Clamp flag. In the case of a short circuit from BUS to GND, the circuit for the BUS receiver senses dominant signal continuously even if there is no dominant transmitting node. The result may be a permanently dominant clamped bus. The device detects and reports a Bus Dominant Clamping situation to microcontroller through BUS_Dom_Clamp flag. If the receiver detects a bus dominant phase of longer than the bus dominant time out TBUSC(dom) BUS_Dom_Clamp flag is set. The flag is cleared on microcontroller read.
7.14 Watchdog (WD)
Start-up watchdog: Gives opportunity to microcontroller to initialize the system. Window watchdog: Detects too early or too late microcontroller software response (loops and hangs). Time-out watchdog: Detects too very long response from microcontroller.
7.14.1 Start-up Wa tchdog Behavior
not properly served for three times, then the system enters into sleep mode.
7.14.2 Window Watchdog Behavior
Figure 12. Window Watchdog Triggering within any valid trigger window. Whenever the watchdog is triggered within the window time Twd_trig, the timer will be reset to start a new period. mode. During undervoltage condition on VLDO1 the watchdog timer is disabled.
7.14.3 Time-out Watchdog Behavior
enters into Start-up watchdog mode. The time-out watchdog function is illustrated in Figure 13. Figure 13. Time-out Watchdog Triggering
7.15 Interrupt Generation
position. Without further interrupts within TINTN pin INTN stays HIGH, otherwise it will revert to LOW again. hardware ensures no interrupt event is lost in case there is a new interrupt forced while reading the register.
Figure 14. Interrupt Register Structure
7.16 Status Registers
space description in subsequent sections. register space description table.
8 Application Information
interface. Since I2C_EN is a digital input pin, it has to be connected either to VLDO1 or GND. Note: I2C_EN should not be changed during a I2C/SPI Read/Write operation. Maximum switching delay between I2C and SPI is 8µs.
8.1 Serial Peripheral Interface
The Serial Peripheral Interface (SPI) provides the communication link with the microcontroller. The SPI is configured for half-duplex data transfer. interface and only master can initiate SPI operation. edge of CS if SCLK is “1” then the SPI is positive edge triggered and if the SCLK is “0” then SPI is negative edge triggered logic (see Table 16). phase MSB is sent first and LSB is sent last. Figure 15. SPI Frame Format Table 15. Device Interface Selection Table 16. SPI Clock Polarity
8.1.1 SPI Write Operation
byte is shown in Figure 16 and Figure 17. Figure 16. SPI Write Operation with Negative Clock Polarity and 1 Byte of Data Field Figure 17. SPI Write Operation with Positive Clock Polarity and 1 Byte of Data Field
8.1.2 SPI Read Operation
with single data byte is shown in Figure 18 and Figure 19. Figure 18. SPI Read Operation with Negative Clock Polarity and 1 Byte of Data Field Figure 19. SPI Read Operation with Positive Clock Polarity and 1 Byte of Data Field
8.1.3 SPI Timing Diagram
Figure 20. Timing Diagram for SPI Write Operation Figure 21. Timing Diagram for SPI Read Operation
8.2 Inter-Integrated Circuit (I2C) Interface
general call address, START byte and high-speed mode. Figure 22. I2C Bus Protocol
8.2.1 I2C Write Operation
condition. For details, see Figure 24. Figure 23. I2C Write Operation
Figure 24. I2C Auto-increment Write Operation
8.2.2 I2C Read Operation
byte that was sent by the AS8650 and generates STOP or repeated START condition after the 9th clock pulse. Figure 25. I2C Read Operation
Figure 26. I2C Auto-increment Read Operation
8.3 Digital Timing Specification
Table 17. SPI Timing Parameters
- Cb = capacitance of one bus line in pF.
- The maximum tf for the SDA and SCLK bus lines quoted in Table 19 (300ns) is longer than the specified maximum tof for the output
lines without exceeding the maximum specified tf.
- I/O pins of Fast-mode devices must not obstruct the SDA and SCLK lines if VLDO1 is switched off.
Characteristics of the SDA and SCLK Bus Lines for F/S Mode I2C Bus. Table 18. I2C Electrical Parameters Table 19. I2C Timing Parameters Hold time (repeated) START condition.
- All values referred to VIHmin and VIlmax levels (see Table 18).
- A fast mode I2C bus device can be used in Standard mode I2C bus system, but the requirement tSU_DAT ≥ 250ns must then be met.
standard mode I2C bus specification) before the SCLK line released.
- The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCLK signal.
- Cb = total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster fall-times according toTable 18 allowed.
- This device internally provides a hold time of at least 300ns for the SDA signal to bridge the undefined region of the falling edge of the
Figure 27. Definition of I2C Timing Parameters
8.3.1 System Specification and Timings
Table 20. System Timing Parameters
8.4 Register Space
through SPI or I2C commands. Table 21. Configuration Registers
01 WD disabled
Time-out Watchdog mode Window period Twd_tout_period. reset and this bit is cleared internally.
0 LDO3 disable in Standby mode
1 LDO3 enable in Standby mode
0 LDO3 disable in Receive only mode
1 LDO3 enable in Receive only mode
0 LDO3 disable in Normal mode
1 LDO3 enable in Normal mode
0 LDO2 disable in Standby mode
1 LDO2 enable in Standby mode
0 LDO2 disable in Receive only mode
1 LDO2 enable in Receive only mode
0 LDO2 disable in Normal mode
1 LDO2 enable in Normal mode
0 DCDC disable in sleep mode
1 DCDC enable in sleep mode
0 BUS with low slew rate
1 BUS with high slew rate
0 Device in STAND BY Mode
1 Device in NORMAL Mode
10 Device in RECEIVE ONLY Mode
00 STAND BY Mode
01 NORMAL Mode
10 RECEIVE ONLY Mode
11 SLEEP Mode
0 No Interrupt
1 Interrupt due to BUS clamped to dominant
1 Interrupt due to short TxD & RxD pins
1 Interrupt due to RxD pin clamped to Recessive
1 Interrupt due to TxD pin clamped to Dominant
1 Interrupt due to CANL pin shorted to VCC
1 Interrupt due to CANL pin shorted to GND
1 Interrupt due to CANH pin shorted to GND
1 Interrupt due to CANH pin shorted to VCC
1 Interrupt due to junction temperature falling back
1 Interrupt due to junction temperature exceeding
1 Interrupt due to Local Wake up event on WAKE pin
1 Interrupt due to Wake up by BUS message (remote
1 Interrupt due to VLDO3_POK_flag set
1 Interrupt due to VLDO3_UV_flag set
1 Interrupt due to VLDO2_POK_flag set
1 Interrupt due to VLDO2_UV_flag set
1 Interrupt due to V5V_POK_flag set
1 Interrupt due to V5V_UV_flag set
1 Interrupt due to VSUP_POK_flag set
1 Interrupt due to VSUP_UV_flag set
9 Package Drawings and Markings
The device is available in a 36-pin QFN (6x6x0.9) package. Figure 28. Drawings and Dimensions
- Dimensions and tolerancing conform to ASME Y14.5M-1994.
- All dimensions are in millimeters, angle is in degrees.
- Dimension b applies to metallized terminal and is measured between 0.25 and
0.30mm from terminal tip. Dimension L1 represents terminal full back from package edge up to 0.15mm is acceptable.
- Coplanarity applies to the exposed heat slug as well as the terminal.
- Radius on terminal is optional.
- N is the total number of terminals.
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Revision History
Note: Typos may not be explicitly mentioned under revision history. Revision Date Owner Description 1.0 29 Nov, 2010 hgl Initial release
The devices are available as the standard products shown in Table 22. Note: All products are RoHS compliant and austriamicrosystems green. Table 22. Ordering Information1
- The AS8650 provides various configuration options during production. For more information, please contact our sales office.
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