AS8530_1 AMSCO | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 32
Technical content
Datasheet sections
- 1 General Description
- 2 Key Features
- 3 Applications
- 4 Pin Assignments
- 4.1 Pin Descriptions
- 5 Absolute Maximum Ratings
- 6 Electrical Characteristics
- 6.1 Operating Conditions
- 6.2 Digital Inputs and Outputs
- 6.3 Detailed System and Block Specifications
- 6.3.1 Electrical System Specifications
- 6.4 Low Dropout Regulator
- 6.5 LIN Transceiver
- 6.5.1 DC Electrical Characteristics
- 6.5.2 AC Electrical Characteristics
- 6.5.3 Temperature Limiter
- 6.5.4 TX Timeout Watchdog
- 6.6 VCC Undervoltage Reset and Window Watchdog
- 6.7 Two Port Serial Interface
- 7 Detailed Description
- 7.1 Voltage Regulator (LDO)
- 7.2 Temperature Limiter
- 7.3 VSUP Undervoltage Reset
- 7.3.1 VSUP Undervoltage in Normal Mode
- 7.3.2 VSUP Undervoltage in Standby Mode / Sleep Mode
- 7.3.3 VSUP Undervoltage in Low Slew Mode
- 7.4 RESET
- 7.5 VCC Undervoltage Reset
- 7.6 Window Watchdog (WWD)
- 7.7 LIN Transceiver
- 7.8 Operating Modes and States
- 7.8.1 Normal Mode
- 7.8.2 Standby Mode
- 7.8.3 Sleep Mode
- 7.8.4 Temporary Shutdown Mode
- 7.8.5 Thermal Shutdown State
- 7.9 State Diagram
- 8 Application Information
- 8.1 Initialization
- 8.2 Wake-Up
- 8.3 Over-Temperature Shutdown
- 8.4 LIN BUS Transceiver
- 8.4.1 Transmit Mode
- 8.4.2 Receive Mode
1 General Description
registers, backup registers and monitoring information. able to withstand voltages up to 42V. The product is available in ep-SOIC8 package.
2 Key Features
3 Applications
Figure 1. AS8530 LIN Transceiver Block Diagram
www.austriamicrosystems.com/Lin_CompanionIC/AS8530 Revision 1.0 3 - 32 AS8530 Datasheet - Contents
4 Pin Assignments
Figure 2. Pin Assignments (T op View)
4.1 Pin Descriptions
Table 1. Pin Descriptions to VSS and ½ VCC trigger level, active high.
4 VSS Supply pad
7 RESET Digital output Digital output referenced to VCC, active low
8 VCC Supply pad Regulated 5V / 3.3V supply for loads up to 50mA.
5 Absolute Maximum Ratings
maximum rating conditions for extended periods may affect device reliability. Table 2. Absolute Maximum Ratings
0.25 W epSOIC8 in still air, soldered on JEDEC standard
www.austriamicrosystems.com/Lin_CompanionIC/AS8530 Revision 1.0 6 - 32 AS8530 Datasheet - Electrical Characteristics
6 Electrical Characteristics
6.1 Operating Conditions
6.2 Digital Inputs and Outputs
All pull-up, pull-downs have been implemented with active devices. RESET and RX have been measured with 100pF load. Symbol Parameter Conditions Min Typ Max Units VSUP Positive Supply Voltage Normal operating condition 6 18 V VSS Negative Supply Voltage 0 V TAMB Ambient temperature Maximum junction temperature (T J) 150ºC -40 +125 ºC Isupp Supply Current 65 mA Symbol Parameter Conditions Min Typ Max Units EN Input VIH High level input voltage High Voltage Pin which can also be connected to VSUP 0.8VCC V VIL Low level input voltage 0.2V CC V ILEAK Input leakage current EN = L -1 +1 µA Ipd_en Pull down current EN = V CC 20 40 µA TX VIH High level input voltage 0.8V CC V VIL Low level input voltage 0.2V CC V ILEAK Input leakage current TX = V CC -1 +1 µA Ipu Pull up current TX pulled to VSS -30 -10 µA RESET VOH High level output voltage I OUT = 1 mA, VSUP ≥ 6V VCC - 0.5 V VOL Low level output voltage V SUP ≥ 6V VSS + 0.4 V RX VOH High level output voltage VCC - 0.5 V VOL Low level output voltage IOUT = 1 mA, VSUP ≥ 6V VSS + 0.4 V
www.austriamicrosystems.com/Lin_CompanionIC/AS8530 Revision 1.0 7 - 32 AS8530 Datasheet - Electrical Characteristics
6.3 Detailed System and Block Specifications
6.3.1 Electrical System Specifications
6.4 Low Dropout Regulator
The LDO block is a linear voltage regulator, which provides a regulated (band-gap stabilized) output voltage (VCC) from the battery supply voltage (VSUP). (6V < VSUP < 18V for option 1, 6V <VSUP <18V option2; -40°C < TJ < 150°C; all voltages are with respect to ground (VSS); positive current flows into the pin), normal operating mode if not otherwise mentioned. Symbol Parameter Conditions Min Typ Max Units IDDnom 1. No external load on the LIN bus Current consumption Normal mode No load on VCC, LIN recessive, VSUP= 12V 300 µA No load on VCC, LIN dominant, VSUP = 12V 700 µA Stand-by mode Up to 125°C ambient (no load), V SUP= 12V 45 µA Sleep mode Up to 125°C ambient (no load), V SUP=12V 35 µA Symbol Parameter Conditions Min Typ Max Units VCC Regulated supply voltage ILOAD 0mA to 50mA Option 1 4.75 5.25 V Option 2 3.135 3.465 TJ Junction Temperature -40 150 ºC VSUP Supply Voltage Range 61 2 1 8V VCC Output Voltage Range Option 1 Load < 50mA 4.75 5.0 5.25 V 50mA to 65mA 4.5 5.5 Standby mode @ ICC < 5mA 4.5 5.5 Load-dump condition, ILOAD < 50mA 5.5 Option 2 Load < 50mA 3.135 3.3 3.465 50mA to 65mA 2.97 3.3 3.63 Standby mode @ ICC < 5mA 2.97 3.63 Load-dump condition, ILOAD < 50mA 3.63 ICC_SH Output Short Circuit Current Normal mode 50 250 mA Standby mode 5 250 dVCC1 Line Regulation ΔVCC / ΔVSUP 8m V / V LOREG_SM Load Regulation (Standby mode) ΔVCC / ΔICCn (for ILOAD > 500µA) 10 mV/mA LOREG_NM Load Regulation (Normal mode) ΔVCC / ΔICCn (for ILOAD > 500µA) 1 mV/mA CL1 Output Capacitor (Electrolytic) 2.2 10 µF ESR1 11 0 Ω CL2 Output Capacitor (Ceramic) 100 220 nF ESR2 0.02 1 Ω CSUP1E Input capacitor (Electrolytic) For EMC suppression 10 100 µF ESR1_CSUP 11 0 Ω CSUP2C Input capacitor (Ceramic) 100 220 nF ESR2_CSUP 0.02 1 Ω
www.austriamicrosystems.com/Lin_CompanionIC/AS8530 Revision 1.0 8 - 32 AS8530 Datasheet - Electrical Characteristics
6.5 LIN Transceiver
6.5.1 DC Electrical Characteristics
(4.5V < VCC < 5.5V; 6V < VSUP < 18V; -40°C < TJ < 150°C, VBUS is the voltage on the LIN node. All voltages are with respect to ground (VSS); positive current flows into the pin. Symbol Parameter Conditions Min Typ Max Units Driver Ibus_lim Current limitation in Dominant State 1 LIN = VSUP_max 1. This failure condition triggers thermal shut down when shut down temperature threshold is exceeded. 40 120 200 mA LIN_VOL Output Voltage BUS (dominant state), ILIN = 40mA (short-circuit condition tested at VOL = 2.5V) Pull-up resistor Normal mode (recessive BUS level on TX pin) 20 40 60 k Ω Ibus_leak_rec Driver OFF; VSUP = 7.0V, 8V < VBUS < 18 20 µA Receiver Ibus_leak_dom Input Leakage current at receiver Input Leakage current at receiver Driver OFF; Vbus = 0V; VSUP = 12V; VCC = 5V -1 mA Ibus_no_GND VSS = VSUP; VSUP = 12V; 0V < VBUS < 18V, VCC = 5V 2 -1 1 mA Ibus_no_bat VSUP = VSS; 0V < VBUS < 18V, VCC = VSS 2 2. Not production tested. 100 µA Vbus_dom 0.4 V SUP Vbus_rec 0.6 V SUP Vbus_cnt Vbus_cnt = (Vth_dom + Vth_rec)/2 3 3. Vth_dom: Receiver threshold of the recessive to dominant LIN bus edge Vth_rec : Receiver threshold of the dominant to recessive LIN bus edge 0.475 0.525 V SUP Vhys Vhys = (Vth_dom – Vth_rec) 3 0.05 0.175 V SUP
www.austriamicrosystems.com/Lin_CompanionIC/AS8530 Revision 1.0 9 - 32 AS8530 Datasheet - Electrical Characteristics
6.5.2 AC Electrical Characteristics
LIN Driver, Bus load conditions (CBUS ; RBUS): 1nF; 1kΩ / 6,8nF; 660Ω / 10nF; 500Ω Note: Sleep-mode to Normal mode transition is identical to the Power-ON sequence after the remote wakeup event on LIN bus. The transition time will include the tRes (RESET time) and start-up time for the LDO. Symbol Conditions Min Typ Max Units (worst case 20Kbps transmission) Vth_rec(max) = 0.744 x VSUP; Vth_dom(max) = 0.581 x VSUP; VSUP = 6.0V to 18V; tbit = 50μs; D1 = tbus_rec(min) / (2 x tbit) 0.369 (worst case 20kbps transmission) Vth_rec (min) = 0.422 x VSUP; Vth_dom (min) = 0.284 x VSUP; VSUP = 6V to 18V; tbit = 50μs; D2 = tbus_rec(max) / (2 x tbit) 0.581 (worst case 10.4kbps transmission) Vth_rec (max) = 0.778 x VSUP; Vth_dom (max) = 0.616 x VSUP; VSUP = 6.0V to 18V; tbit = 96μs; D3 = tbus_rec(min) / (2 x tbit) 0.417 (worst case 10.4kbps transmission) Vth_rec (min) = 0.389 x VSUP; Vth_dom (min) = 0.251 x VSUP; VSUP = 6V to18V; tbit = 96μs; D4 = tbus_rec(max) / (2 x tbit) 0.59 tdLR VCC = 5V; Propagation delay bus dominant to RX LOW 6µ s tdHR VCC = 5V; Propagation delay bus dominant to RX HIGH 6µ s tRS Receiver Delay symmetry -2 2 µs twake Wake-up delay time 30 150 µs tsln Transition from standby mode to normal mode (clock frequency is 128kHz ± 25%) 4 Clock cycles tnsl Transition from normal mode to standby mode (clock frequency is 128kHz ± 25%) 6 Clock cycles trec_deb Receiver De-bounce time 1 3 µs Cint Guaranteed by design 220 250 pF
Figure 3. LIN Timing
6.5.3 Temperature Limiter
6.5.4 TX Timeout Watchdog
www.austriamicrosystems.com/Lin_CompanionIC/AS8530 Revision 1.0 11 - 32 AS8530 Datasheet - Electrical Characteristics
6.6 V CC Undervoltage Reset and Window Watchdog
The values in this table are valid for normal and standby modes. All parameters are tested, unless mentioned otherwise. Symbol Parameter Conditions Min Typ Max Units Vuvr_off VCC under-voltage threshold off (Default) Rising edge of VCC 2.55 2.95 V Vuvr_on VCC under voltage threshold on (Default) Falling edge of VCC 2.3 2.7 V Vuvr1_off VCC under voltage threshold off (Factory Option) Rising edge of VCC 1 1. These are factory options which could be made available on specific request. 3.0 3.4 V Vuvr1_on VCC under voltage threshold on (Factory Option) Falling edge of VCC 1 2.75 3.15 V Vuvr2_off VCC under voltage threshold off (Factory Option) Rising edge of VCC 1 3.5 3.9 V Vuvr2_on VCC under voltage threshold on (Factory Option) Falling edge of VCC 1 3.25 3.65 V Vuvr3_off VCC under-voltage threshold off (Factory Option) Rising edge of VCC 1 4.0 4.4 V Vuvr3_on VCC under voltage threshold on (Factory Option) Falling edge of VCC 1 3.75 4.15 V Vhyst_vcc Hysteresis of under-voltage threshold on/off VCC Default and all other factory options 0.1 0.25 0.4 V trr Spike filter on VCC To remove disturbance 4 µs Vsuvr_off V SUP under-voltage threshold off 3.85 V Vsuvr_on V SUP under-voltage threshold on BOR level (considered to be the Master Reset for AS8530) 3.25 V WD_TCL WWD non-service time (if factory enabled) RESET will be generated 1 2 2. -40%, -20%, +20%, +60%, and +100% timings are available as factory options. 0-75 0 -100 0-125 ms WD_TSV WWD Service – time (if factory enabled) RESET will not be generated 1 75-150 100-200 125-250 ms tRes Reset delay time 4ms, 16ms, 32ms (typ) are factory options (min = -25% and max = +50% of typical) 68 1 2 m s Tshd Temporary shutdown reset active time 0.1 1 s
www.austriamicrosystems.com/Lin_CompanionIC/AS8530 Revision 1.0 12 - 32 AS8530 Datasheet - Electrical Characteristics
6.7 Two Port Serial Interface
Symbol Parameter Conditions Min Typ Max Units General BR2WIRE_SPI Bit rate 250 Kbps TENSCLK_H Clock high time 2 µs TENSCLK_L Clock low time 2 µs Write timing tDI_SU Data in setup time 20 ns tDI_HD Data in hold time 10 ns Read timing tDO_S Data out setup time 130 ns tDO_HD Data out hold time 135 ns tDO_D Data out delay 80 ns tDI_HZ Data in to high impedance delay Time for the Microcontroller to release the TX bus 80 ns Timing parameters when entering 2-Wire SP mode Ttx_su TX setup time before EN goes Low 20 ns Ttx_hd TX hold time after EN goes High 20 ns Ttx_SP_trigger EN falling edge to TX falling edge To enter into 2-Wire SP mode 2 10 µs TSTNDY_trigger TX high time from EN falling edge To enter into Sleep/Standby mode 5 cycles Ten_ENSCLK EN falling edge to start of 2-wire serial port clock 5 cycles
www.austriamicrosystems.com/Lin_CompanionIC/AS8530 Revision 1.0 13 - 32 AS8530 Datasheet - Detailed Description
7 Detailed Description
The AS8530 chip consists of a low drop-out regulator and a LIN bus transceiver, which is a bi-directional bus interface for data transfer between LIN bus and the LIN protocol controller. Additionally integrated is a RESET unit with a power-on-reset delay and a programmable window watchdog. It also includes a watchdog time-out on LIN TX node to indicate if the microcontroller is stuck in a loop and to release unintentional LIN bus dominant state.
7.1 Voltage Regulator (LDO)
The voltage regulator has three operating modes. The features of the operating modes are given below: Normal mode: Stability to be better ±0.25V over input range and temperature for load current up to 50mA. The LDO Output provides a voltage of 5V or 3.3V as OTP option. Standby mode: The Standby mode is a low quiescent current mode used in car applications that are always switched on. The load current in standby mode is 5mA. Quiescent current (no load) is less than 45mA typically at room temperature. Sleep mode: Power down or temporary shutdown of the regulator can be set by a register bit. This bit can be written through 2-wire MCU interface. The LDO takes the input from bandgap and scales it up to the required voltage. The LDO starts charging only after the POR-VSUP event occurs (RESET_VSUP_N switched from low to high). The LDO can be powered-down by a control signal (temporary shutdown register) for the temporary shutdown mode.
7.2 Temperature Limiter
Temperature limiter produces a power down when temperature exceeds 155ºC ±10%. It powers up and generates a reset when it returns to 135ºC ±10% junction temperature. During thermal shut down, temperature sensor is supplied by VSUP. During the temperature ramp-up phase, as soon as the temperature exceeds 135ºC ±10%, a warning signal is issued and is written into the diagnostic register, which can be read through the SP interface.
7.3 V SUP Undervoltage Reset
VSUP undervoltage reset generates a reset RESET_VSUP_N, switched from low to high when VSUP ramps up above VSUVR_OFF. This is used to enable proper initialization of mode control and diagnostic registers. If VSUP < VSUVR_ON, then RESET_VSUP_N switches from high level to low level (active). This is considered to be the master reset and will have the highest priority over all other signals. As soon as VSUP < VSUVR_ON, the LDO, LIN Transceiver is completely shut off and system comes to a complete stop. AS8530 enters into the normal operating mode only after VSUP > VSUVR_OFF.
7.3.1 VSUP Undervoltage in Normal Mode
Supply Voltages below VSUVR_OFF and above VSUVR_ON do not influence the voltage regulator. The output voltage VCC follows VSUP.
7.3.2 VSUP Undervoltage in Standby Mode / Sleep Mode
No exit from the sleep mode or standby mode take place if the VSUP voltage drops down to VSUVR_OFF. If VSUP goes below VSUVR_ON, RESET_VSUP_N is active and resets the mode control and diagnostic register. The voltage regulator, LIN Transceiver modules are turned off. If VSUP rises again above VSUVR_OFF, RESET_VSUP_N is switched from low to high. The system enters normal mode where LIN Transceiver and LDO are switched on.
7.3.3 VSUP Undervoltage in Low Slew Mode
The behavior of AS8530 at low VSUP voltages is equal to the sleep mode. The low slew mode (set by control register through serial interface as an option) will be cancelled, if VSUP drops below VSUVR_ON in this mode. The AS8530 enters the normal mode, if VSUP rises again above VSUVR_OFF.
7.4 RESET
Figure 4. Reset consists of a digital buffer at the output. RESET signal can be affected by RESET_VCC_N (which is the under-voltage reset on Figure 4. Reset Functionality
7.5 V CC Undervoltage Reset
under-voltage reset threshold voltage level adjustment can be made by 2 bit OTP as explained in OTP interface.
7.6 Window Watchdog (WWD)
enabled, there is a 3-bit factory programming available to set the trigger window.
Figure 5. Window Watchdog Trigger
7.7 LIN Transceiver
available to protect it from back supply from bus line. performance across different loading conditions conforming to the LIN 2.1 standards. The wake-up detects a wake up event on the LIN.
7.8 Operating Modes and States
7.8.1 Normal Mode
than Totset, a warning flag is set in the diagnostic register, which can be read through the 2-wire interface.
7.8.2 Standby Mode
in recessive state (high). CS is pulled to VCC while SDI and SCLK outputs are pulled to VSS.
7.8.3 Sleep Mode
up possible is through remote wake-up, through LIN pin, pulling it to dominant state for 100µs typical (low), can change the state of the system.
7.8.4 Temporary Shutdown Mode
transition will be controller by register bit in configuration register.
7.8.5 Thermal Shutdown State
Table 3. Transition T able
- Chosen by factory programming option
7.9 State Diagram
other “wait” states have been included for the sake of completeness. Figure 6. Finite State Machine Model for the AS8530 System
8 Application Information
8.1 Initialization
contents of OTP latch onto the pre-regulator domain register. This register gives actual settings of LDO, Vuvr_off and Reset Timeout period TRes. ramp on VSUP (of the order of 0.5V/min). Figure 7. Initialization Sequence for AS8530
6 Cycles of
8.2 Wake-Up
predefined low time (twake) puts the regulator into normal mode.
8.3 Over-Temperature Shutdown
If the junction temperature increases beyond Tsd the over-temperature recognition will be activated and the regulator voltage will be switched off.
8.4 LIN BUS Transceiver
8.4.1 Transmit Mode
emission of the bus line, the BUS driver has an integrated slew rate control and wave shaping unit. series with a diode to VBAT. Table 4. VSUP>Vsuvr_on and VCC<Vuvr_on Table 5. VSUP<Vsuvr_on
8.4.2 Receive Mode
Figure 8. Receive Mode Impulse Diagram
8.5 RX and TX Interface
generates a recessive BUS level. Figure 9. TX Input Circuitry
This output is a push-pull driver between VCC and GND with an output current of 1mA. Figure 10. RX Output Circuitry
8.6 MODE Input EN
The AS8530 is switched from normal mode to the standby/sleep mode with a falling edge on EN and keeping TX high for TSTNDY_trigger time. within Ttx_SP_trigger time after EN forced to low. This ensures the direct control of device to enter into Standby/Sleep mode by microcontroller using EN pin. Figure 11. EN Pin Functionality The EN input has an internal active pull down to secure that if this pin is not connected, a low level will be generated.
0 A4 D3 D2 D1 D0
8.7 Serial Port Interface
description of this interface and the protocol is explained below. Information on block status and errors can be displayed by diagnosis registers.
8.7.1 Device Configuration using 2-Wire Serial Port
figures two examples of write command (without and with address self-increment). Figure 14. Protocol for Serial Data Write with Length = 1 Table 6. Command Bits 0 WRITE ADDRESS Writes data byte on the given starting address. 1 READ ADDRESS Read data byte from the given starting address. Table 7. Transfer Length 012 Transfer consist of two Data phase. 104 Transfer consist of four Data phase. 118 Transfer consist of eight Data phase.
8.8 Control and Diagnosis Registers
diagnostic options. Refer to Table 8 for details on the configuration registers.
8.8.1 Definition of Cont rol and Status Registers
of all control and status registers. Table 8. Configuration Registers
0 Disabled
1 Enabled
0 No Temporary shutdown
1 Enter into Temporary shutdown
will be cleared internally within 2 cycles of 128KHz clock.
temperature warning. This is because 125ºC is within the limits for the OVTEMP140. shutdown state and cleared after µC read.
9 Package Drawings and Markings
The device is available in a ep-SOIC8 package. Figure 20. Drawings and Dimensions
- The device marking for the VCC=5V option will change to AS85305.
www.austriamicrosystems.com/Lin_CompanionIC/AS8530 Revision 1.0 29 - 32 AS8530 Datasheet - Package Drawings and Markings Notes: 1. Dimensions and tolerancing conform to ASME Y14.5M -1994. 2. All dimensions are in miilimeters. Angles are in degrees. 3. Datums A and B to be determined at datum H. 4. Extrusion of exposed area in bottom side is 0.20mm typical. Marking: YYWWIZZ. YY WW I ZZ Last two digits of the manufacturing year Manufacturing Week Plant Identifier Traceability Code Symbol Min Nom Max A- -1 . 7 0 A1 0.00 - 0.15 A2 1.25 - - b0 . 3 1 - 0 . 5 1 c0 . 1 7 - 0 . 2 5 D - 4.90 BSC - D1 2.24 3.10 3.20 E - 6.00 BSC - E1 - 3.90 BSC - E2 1.55 2.41 2.51 e - 1.27 BSC - L 0.41 0.64 0.89 Symbol Min Nom Max L1 - 1.04 REF - L2 - 0.25 BSC - h0 . 2 5 - 0 . 5 0 θ 0º - 8º aaa - 0.10 - bbb - 0.20 - ccc - 0.10 - ddd - 0.25 - eee - 0.10 - fff - 0.15 -
www.austriamicrosystems.com/Lin_CompanionIC/AS8530 Revision 1.0 30 - 32 AS8530 Datasheet - Revision History
Revision History
Note: Typos may not be explicitly mentioned under revision history. Revision Date Owner Description 1.0
26 Nov, 2010 mbl Initial release
29 Nov, 2010 kpt Marking details updated under Ordering Information.
The devices are available as the standard products shown in Table 9. Note: All products are RoHS compliant and austriamicrosystems green. Table 9. Ordering Information1
- For both product versions , the RESET delay time tRes as well as undervoltage threshold are set to default value and window watchdog
is disabled. On special request, optional factory settings can be made available on specific vendor addendum.
www.austriamicrosystems.com/Lin_CompanionIC/AS8530 Revision 1.0 32 - 32 AS8530 Datasheet - Copyrights Copyrights Copyright © 1997-2010, austriamicrosystems AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies. Disclaimer Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services. Contact Information Headquarters austriamicrosystems AG Tobelbaderstrasse 30 A-8141 Unterpremstaetten, Austria Tel: +43 (0) 3136 500 0 Fax: +43 (0) 3136 525 01 For Sales Offices, Distributors and Representatives, please visit: http://www.austriamicrosystems.com/contact