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Technical content
Datasheet sections
- 1 General Description
- 2 Key Features
- 3 Applications
- 4 Pin Assignments
- 4.1 Pin Descriptions
- 5 Absolute Maximum Ratings
- 6 Electrical Characteristics
- 6.1 Operating Conditions
- 6.2 DC/AC Characteristics for Digital Inputs and Outputs
- 6.3 System Specifications
- 7 AS8515 Top Die Overview
- 7.1 Voltage Attenuator
- 7.2 Voltage Regulators (LDO)
- 7.3 LIN Transceiver
- 7.4 Temperature Monitor/Limiter
- 7.5 VSUP Under-voltage Reset
- 7.6 Reset
- 7.7 VCC Under-voltage Reset
- 7.8 Window Watchdog (WWD)
- 7.9 Timeout Watchdog (TWD)
- 7.10 Modes of Operation
- 7.10.1 Normal Mode
- 7.10.2 Standby Mode
- 7.10.3 Temporary Shutdown Mode
- 7.10.4 Thermal Shutdown Mode
- 7.11 Initialization
- 7.12 Wake-up
- 7.12.1 Remote Wake-up Event
- 7.13 LIN BUS Transceiver
- 7.13.1 Transmit Mode
- 7.13.2 Receive Mode
- 7.14 Rx and Tx Interface
- 7.14.1 Input Tx
- 7.14.2 Output Rx
- 7.15 MODE Input EN
- 7.16 Top Die Block Specifications
- 7.16.1 Voltage Attenuator
- 7.16.2 Voltage Regulator (LDO)
- 7.16.3 VCC Power-on-Reset
- 7.16.4 VSUP Power-on-Reset
- 7.16.5 Window Watchdog Timer
- 7.16.6 LIN Transceiver
- 7.17 Timing Diagrams
Data Acquisition System with Power Management and LIN Transceiver for 12V Battery Sensor Applications www.ams.com Revision 0.7 1 - 65
1 General Description
The AS8515 is designed for simultaneous measurement of shunt current sensor signal and battery voltage by two independent ADC channels. Both channels can measure small signals up to ±219 mV versus ground through programmable gain amplifier or larger signals in the 1V range without amplifier. After analog to digital conversion and digital filtering, the resulting digital values are accessible through 4-wire serial interface. The device is powered directly from the battery through LDO and provides a 3.3V supply for an external microcontroller. For communication with the next level ECU, the device offers a LIN 2.1 transceiver. Measurement of battery voltage is supported through resistive attenuator with disable for power saving in standby. The device is a stacked die system providing a high voltage CMOS IC for power management and transceiver functions as a Top die and low voltage sensor interface functions as a Bottom die inside a 32-pin MLF (5x5 mm) package.
2 Key Features
A precision voltage attenuator with power down facility LIN 2.1 transceiver Power-On Reset with programmable reset timeout and brown- out detection through factory setting A window Watchdog function in the normal mode and a timeout Watchdog in the device standby mode as a factory option Load dump protection (42V) for all battery supplied pins and Enable pin Internal reverse polarity protection (up to -27V) for all battery- sensing pins, and LIN bus pin Over temperature warning & shutdown functions Two independent high resolution A/D converters with programmable over sampling ratio Programmable sampling rate up to 4kHz throughput Programmable gain, low noise amplifier for current channel with gain stages 5, 25, 40, 100 Internal temperature sensor Synchronous acquisition for both ADC channels Reference-voltage source (high precision and high stability) Offset auto zero architecture on both channels Current monitoring comparator with interrupt signal generation and µC clock enable. Timer with 2 related outputs for single shot sampling of current and voltage channel in low power mode. Precision on chip RC oscillator or external clock. Low slew, low EMC clock output which can be used by external microcontroller which is enabled respectively disabled by mode control through SPI and interrupt from current monitor in low power mode. The integrated circuit can execute measurements with internal and external sensors and sources for the voltage channel and with external sensor for the current channel. External Sensors: Current measurement via Shunt resistor (4 ranges) Battery voltage (internal voltage divider to battery) ETR and ETS for external temperature sensor (with switchable current source) Internal Sensors: On chip temperature sensor Internal current sources for functional test of measurement path and the connection of shunt resistor
3 Applications
The AS8515 is suitable for battery sensors, having shunt current sensor at minus pole. For lead acid, Li-Ion batteries up to 18V nominal, 42V over voltage capability. The device is also ideal as a general purpose sensor interface for automotive LIN slaves.
Figure 1. AS8515 Block Diagram
www.ams.com Revision 0.7 4 - 65 AS8515 Datasheet - Contents
4 Pin Assignments
Figure 2. Pin Assignments (T op View)
4.1 Pin Descriptions
Table 1. Pin Descriptions Connect 100nF to AVSS from this pin. Connect 100nF to AVSS from this pin. Should be shorted to pin 21 (VCC) externally.
Connect 100nF to VSS from this pin. Should be shorted to pin 21(VCC) externally.
- Pin #4, pin #20 and pin #15 needs to be shorted externally on the board. Pin #21 is the LDO output that supplies pin #4 and pin #20.
- Pin #5, pin #11 and pin #19 needs to be shorted externally on the board as they are the grounds.
5 Absolute Maximum Ratings
maximum rating conditions for extended periods may affect device reliability. Table 2. Absolute Maximum Ratings current externally, which is not greater than 17mA at 18V VSUP and 20mA at 16V VSUP. Solid State Surface Mount Devices”.
6 Electrical Characteristics
6.1 Operating Conditions
6.2 DC/AC Characteristics for Digital Inputs and Outputs
All pull-up, pull-downs have been implemented with active devices. SDO have been measured with 10pF load. Table 3. Operating Conditions current externally, which is not greater than 17mA at 18V VSUP and 20mA at 16V VSUP. Table 4. INT Table 5. CST, CSB
Table 6. SDI, SCLK Table 7. SDO Table 9. EN Table 10. CLK I/O
6.3 System Specifications
period of 2s (NOM1 time of device is low in Standby mode). Table 11. MEN Table 12. Rx Table 13. RESET Table 14. System Specifications
7 AS8515 Top Die Overview
7.1 Voltage Attenuator
device standby mode, we additionally need logic high on MEN pin for enabling. Internal reverse polarity protection is provided for VSENSE pin. Figure 3. Attenuator Implementation
7.2 Voltage Regulators (LDO)
except when the device enters the over-temperature shutdown. by configuring the device to temporary shutdown mode through SPI. there is an under voltage on VCC, that is, when RESET_VCC_N switches back to low.
7.3 LIN Transceiver
the data on the bus to the controller (Rx pin). The transceiver conforms to the LIN 2.1 standard. The LIN transceiver has a timeout watchdog for Tx. After the timeout, the LIN bus will be released to the recessive state from the dominant state. the LIN bus to bring the device to normal mode.
7.4 Temperature Monitor/Limiter
temperature warning flag is also cleared at this temperature. The temperature limiter circuit can be optionally disabled through SPI.
7.5 VSUP Under-voltage Reset
7.6 Reset
detail in the subsequent sections. The reset period can be one-time programmed to 4, 16 and 32 ms with a default value of 8 ms. Figure 4. Reset Functionality
7.7 VCC Under-voltage Reset
shutdown and temporary shutdown only through VCC under voltage.
7.8 Window Watchdog (WWD)
or after WD_TSV, a reset output is generated. programmed through factory setting and enabled as a factory option. Figure 5. Window Watchdog Functionality
7.9 Timeout Watchdog (TWD)
started upon a rising edge on INT and will generate a reset output if the Microcontroller doesn’t send a trigger before the timeout. can be programmed through SPI.
7.10 Modes of Operation
states like “TxWD Wait”, “Standby Wait”, and other wait states have also been included in the state diagram for completeness. Figure 6. Finite State Machine Model of AS8515 T op Die
Rwake = Remote wake, X = don’t care.
7.10.1 Normal Mode
enabled through SPI. LIN transceiver is capable of sending the Tx data from microcontroller to the LIN bus at a maximum rate of 20Kbps.
7.10.2 Standby Mode
sure that the Microcontroller is active.
7.10.3 Temporary Shutdown Mode
this mode to normal mode after the timeout of an internal timer.
7.10.4 Thermal Shutdown Mode
Table 15. Transition T able
7.11 Initialization
Figure 7. Initialization Sequence Table 16. VSUP>Vsuvr_on and VCC<Vuvr_on
6 Cycles of
7.12 Wake-up
25) will result in the device wake-up which is termed as remote wake.
7.12.1 Remote Wake-up Event
Figure 8. Remote Wake-up Event Table 17. VSUP<Vsuvr_on
7.13 LIN BUS Transceiver
7.13.1 Transmit Mode
emission of the bus line, the BUS driver has an integrated slew rate control and wave shaping unit. series with a diode to VSENSE.
7.13.2 Receive Mode
Figure 9. Receive Mode Impulse Diagram
7.14 Rx and Tx Interface
7.14.1 Input Tx
pin generates a recessive BUS level. Figure 10. Tx Interface
7.14.2 Output Rx
Figure 11. Rx Interface
7.15 MODE Input EN
The AS8515 Top die is switched from normal mode to the standby mode with a falling edge on EN and keeping Tx high for TSTNDY_trigger time. microcontroller using EN pin. Figure 12. EN Pin Functionality The EN input has an internal active pull down to secure that if this pin is not connected, a low level will be generated. Figure 13. Enable Interface
Figure 14. EN Connection for Permanent Normal Mode
7.16 Top Die Block Specifications
This section provides specification of design related key parameters.
7.16.1 Voltage Attenuator
Table 18. Voltage Attenuator
7.16.2 Voltage Regulator (LDO)
7.16.3 VCC Power-on-Reset
7.16.4 VSUP Power-on-Reset
Table 19. Voltage Regulator Table 20. VCC Table 21. VSUP
7.16.5 Window Watchdog Timer
7.16.6 LIN Transceiver
Table 22. WWD Table 23. Driver Table 24. Receiver
- V th_dom : Receiver threshold of the recessive to dominant LIN bus edge
7.17 Timing Diagrams
Figure 15. Timing Diagram for Propagation Delays Table 25. LIN Driver
Figure 16. Timing Diagram for Duty Cycle According to LIN 2.1 and J2602
7.17.1 Tx Timeout Watchdog
7.17.2 Temperature Limiter
7.18 Top Die Registers
information can be read out from the diagnostic registers. Pin CST is used as chip select for SPI communication. 4-wire serial interface. Table 28 provides a description of all AS8515 Top die registers. Table 26. Tx Timeout Watchdog Table 27. T emperature Limiter Table 28. AS8515 Top Die Registers D1 Voltage Attenuator Enable Bit.
0 Disabled, 1 Enabled
1 High-slew, 0 Low-slew
1 Enter temporary shutdown
Upon a trigger, the bit will be cleared within 2 internal clock cycles.
D7-D0 = DR[7:0], 8-LSB bits of the 24-bit Diagnostic Register. D7-D0 = DR[15:8], Next 8-LSB bits of the 24-bit Diagnostic Register. This bit is set on entering temporary shutdown state and cleared after µC read.
www.ams.com Revision 0.7 28 - 65 AS8515 Datasheet - AS8515 Bottom Die Overview
8 AS8515 Bottom Die Overview
The AS8515 Bottom die consists of two independent high resolution 16-bit SD analog to digital conversion channels. The measurement path of these two channels integrates a programmable gain amplifier, chopper and de-chopper, sigma-delta modulator, decimator and a digital filter for simultaneous measurement of Current and Voltage/Temperature. The two measurement channels, namely the Current and Voltage/Temperature measurement channels have identical data path. The input signal is amplified in the Programmable Gain Amplifier (PGA) with any of the selected gains of 1, 5, 25, 40 and 100 facilitating measurement of a wide range of Current, voltage and temperature levels. Gain Settings for different input ranges and any associated restrictions are explained in the Table 30. Offset in the measurement path is minimized with the use of a chopper and a de-chopper at appropriate stages in the data path. By default the chopper/de-chopper is ON in the measurement path. It may be disabled by programming the appropriate register. The amplified input signal is converted into a single-bit pulse-density modulated stream by the Σ-Δ Modulator. A decimator acting as a low-pass filter filters out the quantization noise and generates 16-bit data corresponding to the input signal. The decimation ratios of 64, 128 may be selected in the first filter stage. For reducing data rate further, the second stage decimation can be used. An optional FIR Filter is provided to offer matched low pass filter response typically required in lead acid battery sensor systems.
8.1 Current Measurement Channel
The voltage across a Shunt Resistor, connected in series with the Battery negative terminal, forms the input signal to the Current Measurement channel. RSHH and RSHL are the Current measurement input pins. Offset in the input signal is nullified with the use of a chopper and a de- chopper at appropriate stages in the data path. The programmable gain amplifier in the data path with programmable settings of 1, 5, 25, 40 and 100 enables measurement of current ranges from ±1A to ±1500A on a 100µΩ shunt. The sampled input signal is converted into a single-bit pulse-density modulated stream by the Σ-Δ Modulator. A decimator acting as a low-pass filter filters out the quantization noise and generates 16- bit data equivalent to the input current signal. The programmable input sampling rate and the decimation ratio determine the output data rates. The data path can be programmed to provide sub 1Hz to 4kHz rates in the various modes available. An optional FIR filter specifically designed for 1KHz sample rate is provided to offer matched low pass filter response typically required in lead acid battery sensor systems. After enabling the current measurement channel, the delay for the availability of the first sample is two conversion cycles.
8.2 Voltage/Temperature Measurement Channel
The other two parameters of the Battery for measurement are Voltage and its Temperature. The second channel accepts signals from four independent sources through a Multiplexer as listed below: An attenuator battery voltage obtained through internal resistor divider from Top die, (or) A signal from the external temperature sensor, (or) A signal from external reference, (or) A signal from the internal temperature sensor. Apart from this difference in the multiplexing of four input signals, the rest of the data path is identical to the Current measurement channel. RSHH and RSHL are the Current measurement input pins. The Battery Voltage which can go up to 18V is attenuated through a Resistor Divider externally and is applied to the Voltage Channel. For Automotive Battery measurement, the PGA is to be bypassed to connect battery voltage attenuated by a factor of 21 directly to the ADC input. The latency for the first result from the voltage measurement channel is two conversion cycles. A second option on this measurement channel is to measure Temperature. Internally generated constant current is pumped through the Temperature Sensor with positive temperature coefficient, and, a high- precision resistor. The voltages across the sensor and the resistor form the inputs to the measurement channel one at a time. The difference between the two voltages which is independent of the magnitude of the current is used to determine the temperature accurately. The voltage across the sensor is applied between the ETS and VSS pins and, the voltage across the high-precision resistor is applied between ETR and VSS. External temperature measurement involves the acquisition of two signals one after the other using the same constant current source. The latency for the first result from the temperature measurement channel is two conversion cycles. A third option on the measurement channel is to measure the internal temperature. Hence, one of the three options for measurement of Battery Voltage, External Temperature and, internal temperature may be carried out by selection of appropriate inputs through the internal multiplexer selection. ETR and ETS inputs can optionally be used to measure other signal sources like external resistive attenuators for battery voltages different to 12V nominal. ETR and ETS are single ended inputs and referenced to AVSS. Voltage drop on internal bond wire causes ~100 digits of offset with systematic temperature dependency of another 50 LSB’s over temperature.
8.3 Digital Implementati on of Measurement Path
Figure 17. Block Diagram of Digital Implementation CIC2 filter with a decimation ratio of 1to 32768 in steps of power of 2. This output is then processed through a FIR or Moving Average (MA) filter. averaged output and the number of samples for averaging can be any integer value from 1 to 15.
8.4 Reference-Voltage
Band gap-reference voltage is used for the ADC as a reference and for the generation of the current for external temperature measurement.
8.5 Oscillators
8.6 Power-On Reset
happens and the system status is shown in state diagram (see Figure 18). AS8515 can be programmed and by giving start command it starts working following the state machine.
8.7 Modes of Operation
is increased to a higher rate only when a measured input signal level crosses the programmed threshold in the current measurement channel. four Modes. The State transition Diagram involving the state of Stop and the four Modes is illustrated in the Figure 18. Figure 18. Finite State Machine Model of AS8515 Bottom Die
- Device soft reset can be written in any of the following states STOP, A_STB, SBM_ON, SBM_OFF by writing “0” into D[7] of the RESET
- Measurement path of soft reset should be written in any the states, STOP, SBM_OFF by writing “0” into D[6] of the RESET _REG (Address
- When soft reset is used for the measurement path or for the device, external clock needs to be disabled if the system clock is external
8.7.1 Normal Mode 1 (NOM1)
On Power-on-reset of the device, AS8515 goes into STOP State. Figure 19. When the device is configured to NORMAL Mode1 from any mode the configuration should be through the STOP state only. Figure 19. Normal Mode 1
8.7.2 Normal Mode 2 (NOM2)
threshold, the data rate is changed to the rate of NOM1 mode. illustrated in the waveform Figure 20.
Figure 20. Normal Mode 2
8.7.3 Standby Mode1 (SBM1)
consumption of the data acquisition and processing system. Figure 21. Standby Mode 1
8.7.4 Standby Mode2 (SBM2)
microcontroller only when the data sample exceeds the set current threshold. The Standby Mode can be entered only through the STOP state. Registers D,E. It should be noted here that the data is stable for Ta seconds. The functionality is illustrated in Figure 22. Figure 22. Standby Mode 2
8.8 Initialization Se quence at Power ON
Figure 23. Bottom Die Device Initialization Sequence at Power ON ignored in the system. Device configuration and activation should be carried out only after the initialization period. first interrupt will occur after a time period of TADC.
registers and status registers are not read during the TDATA_INVALID duration. CHOP_CLK and POR_N are internal signals of the device.
8.8.1 Soft-reset of Device Using Bit D[7] of Reset Register 0x09
Table 29. Valid Combinations of Modulator Clock, Chopper Clock and Decimation Ratio R1
Figure 24. Bottom Die Device Initialization Sequence at Soft-reset
8.8.2 Soft-reset of the Measurement Path Using Bit D[7] of Reset Register 0x09
8.8.3 Reconfiguring Gain Setting of PGA
sample from the ADC is invalid. Ignore the first interrupt after the gain re-configuration. Valid data starts from the second interrupt onwards. Figure 25. Bottom Die - Re-configuration of Gain Setting of PGA
8.8.4 Configuring the De vice During Normal Mode
Following registers can be programmed dynamically when the device is in operational mode (Normal mode).
8.8.5 Standby Mode - Power Consumption
microcontroller through an interrupt signal on INT and goes into STOP state. started. Any measurements performed during Tsett produce invalid results. Tmeas =Tsett +T1 is the total active time needed to get a valid result. DRSBM = Tmeas/Tsbm ≈ 5ms/10s. This is the ratio of repetition time versus the active time (Device in NOM mode).
8.9 Bottom Die Bl ock Specifications
This section provides specification of design related key parameters.
8.9.1 Current Measurement Ranges (across 100µ Ω (±5%) shunt resistor)
Table 30. Current Measurement Ranges
- V INADC = Vsh * Gain, gain deviations to be considered according to Table 32 and Table 33.
- AVDD, DVDD of 3.3V with ±5% variation.
Table 31. Valid Combinations of the Chopper Clock, Oversampling Clock and Decimation Ratios
Differential Input Amplifier for Current Channel.
- Leakage test accuracy is limited by tester resource accuracy and tester hardware.
- For gain 100 PGA input common mode is 0V and the minimum supply is 3.15V.
- The measurement ranges are referred only by the gain of input amplifier, while other parameters such as bandwidth etc. are pro-
- This parameter is not measured directly in production. It is measured indirectly via gain measurements of the whole path. It is guaran-
- Pole frequency of input amplifier changes with GAIN. The number is valid for the gain at G1, while the bandwidth will be higher for other
ranges. This parameter is not measured in production.
- Based on device evaluation. Not tested.
- These offsets are cancelled if chopping enabled (default).
- Noise density calculated by taking system bandwidth as 150Hz.
- Refer to Measurement Ranges shown in Table 30.
- No impact on the measurement path. If the chopping is enabled, both the offset and offset drift will be eliminated.
- For negative input voltages up to -160mV below ground, Input leakage is typically -20nA @ 65ºC due to forward conductance of
Table 32. Differential Input Amplifier for Current Channel
Differential Input Amplifier for Voltage Channel.
- Input for the voltage channel can be as high as 1220mV, in this high input case PGA will be bypassed.
- Leakage test accuracy is limited by tester resource accuracy and tester hardware, especially at low temperatures due to condensing
- For gain 100 PGA input common mode is 0V and the minimum supply is 3.15V.
- The measurement ranges are referred only by the gain of input amplifier, while other parameters such as bandwidth etc. are pro-
- This parameter is not measured directly in production. It is measured indirectly via gain measurements of the whole path. It is guaran-
- Pole frequency of input amplifier changes with changing the GAIN. The number is valid for the gain at G1, while the bandwidth will be
higher for other ranges. This parameter is not measured in production.
- Noise density calculated by taking system bandwidth as 150Hz.
- Based on device evaluation. Not tested.
- No impact on the measurement path. If the chopping is enabled, both the offset and offset drift will be eliminated.
- For negative input voltages up to -160mV below ground, Input leakage is typically -20nA @ 65ºC due to forward conductance of
Table 33. Differential Input Amplifier for Voltage Channel
Sigma Delta Analog to Digital Converter.
- Programmable. It is defined with respect to the first decimator in the ΣΔ ADC.
- Programmable: Internal clock is 1024/2048 kHz; external clock max is 8192 kHz.
- Dependent on fovs, R1 and R2. The bandwidth is calculated according to the formula:
BW=fovs/(2*R1*R2); the sampling frequency at the output of the A/D converter is 2*BW.
- Defined at maximum input signal, BW=500 Hz (1Hz to 500 Hz), fovs=1024 kHz, R1=64, fchop=2 kHz and R2=2.
- Reference voltage might be forced from external.
- Accuracy at 65ºC. No DC current is allowed from this pin.
- Specification does not include solder shift and life time drift.
- Please refer Figure 26 for typical life time drift based on system level measurements.
- This is a design parameter and not production tested.
Table 34. Sigma Delta Analog to Digital Converter Table 35. Bandgap Reference Voltage
Figure 26. Typical System-level VREF Drift
Internal (Programmable) Current Source for External Temperature Measurement.
- Current value can be programmed through stop mode in steps of 8μA from 0 to 256μA with a process error of 30%.
- Temperature coefficient is not important since external temperature measurement is a 2 step measurement. The value specified is
guaranteed by design and will not be tested in production.
- Maximum voltage on pin ETR (reference) can be calculated by given formula, where G is the gain of PGA (G=100).
- Maximum voltage on pin ETR, if PGA is bypassed.
- Maximum voltage on pin ETS, if PGA is bypassed.
Internal AVDD Power-on Reset. Table 36. External T emperature Measurement Table 37. CMREF Circuit Table 38. Internal AVDD Power-on Reset
- POR pulse is always longer than t PORA whatever the slope of the supply.
- I PORA can not be switched off.
Internal DVDD Power-on Reset. Table 39. Internal DVDD Power-on Reset
- V PORLO = VPORHI - VHYST where VPORLO is the lower threshold of POR.
- V PORLO = VPORHI - VHYST where VPORLO is the lower threshold of POR.
- I PORD can not be switched off.
Table 40. Low Speed Oscillator Table 41. High Speed Oscillator Table 42. External Clock
Internal Temperature Sensor.
8.9.2 System Specifications
System Measurement Error Budget for Voltage and Current Channel. Temperature Range: -20ºC to +65ºC; Output data rate is 1kHz, VCC = 3.3V, chopping enabled.
- These specifications are defined by taking one channel as reference and measured on the other channel.
- System measurement error due to noise, individual block parameter drifts and non linearity. Based on evaluation, not tested.
- System error due to offset is neglected because of chopper architecture.
Table 43. Internal T emperature Sensor internal temperature measurement.
27 Digits/C
Table 44. System Specifications Table 45. System Measurement Error Budget for Gains 5 and 25
on SCLK signal decide setting of the active SPI clock edge for data transfer (see Table 46).
9.1 SPI Timing Parameters
Table 46. CS and SCLK
- Pin CST is used to program top device and pin CSB is used to program bottom device.
FALL LOW Serial data transferred on rising edge of SPI clock. Sampled at falling edge of SPI clock. FALL HIGH Serial data transferred on falling edge of SPI clock. Sampled at rising edge of SPI clock. ANY ANY Serial data transfer edge is unchanged. Table 47. 4-Wire Serial Port Interface
9.1.1 SPI Frame
bytes. Command is coded on the 1 first bit, while address is given on LSB 5 bits (see Table 48). the SPI interface increments the address of the previous data byte and writes/reads data to/from consecutive addresses.
9.1.2 Write Command
examples of write command (without and with address self-increment. Figure 27. Protocol for Serial Data Write with Length = 1 Table 48. Command Bits
0 WRITE ADDRESS Writes data byte on the given starting address
1 READ ADDRESS Reads data byte from the given starting address
0 RES1 RES0 A4 A0 A1A2A3 D0D1D2D3D4D5D7 D6
Figure 28. Protocol for Serial Data Write with Length = 4
9.1.3 Read Command
read command (without and with address self-increment) have been shown. Figure 29. Protocol for Serial Data Read with Length = 1
1 RES1 RES0 A4 A0 A1A2A3
Figure 30. Protocol for Serial Data Read with Length = 4
9.1.4 Timing
In the following figures timing waveforms and parameters are exposed. Figure 31. Timing for Writing
Figure 32. Timing for Reading
9.2 Bottom Die Registers
This section describes the control registers used in AS8515 Bottom die. Registers can be broadly classified into the following categories. Table 49. Control Registers
00 DREG_I1
01 DREG_I2
02 DREG_V1
03 DREG_V2
04 STATUS_REG 0000_0000 R
05 DEC_REG_R1_I 0100_ 0101 R/W
0 Down Sampling Rate is 64
1 Down Sampling Rate is 128
00 Chopper Clock Always High
01 Divide by 256
10 Divide by 512
11 Divide by 1024
CIC1 Saturation Interrupt Mask Control.
06 DEC_REG_R2_I 1100_0101 R/W
0 Active high
1 Active low
00 FIR / MA Output
01 CIC2 Output
10 Dechop/Demod Output
11 CIC1 Output
07 FIR CTL_REG_I 0000_0100 R/W
This bit selects FIR / MA Filter in Current channel. averaging in MA filter in Current channel. architecture in both Current and Voltage channels.
00 Demodulator after CIC1
01 Demodulator before CIC1
10 Dechopper after CIC1
11 Demodulator before CIC1 with settled
08 CLK_REG
00 Internal HS Clock with No Clock Output
01 Internal HS Clock with Clock Output
10 External Clock
00 No division
01 Divide by 2
10 Divide by 4
11 Divide by 8
0 LS _CLK undivided (Low Speed clock)
1 LS _CLK divide by 2
09 RESET_REG
These two bits select the operating mode of the Device.
00 Normal Mode 1
01 Normal Mode 2
10 Standby Mode 1
11 Standby Mode 2
0 Disabled
1 Enabled
0 Retain in STOP state
1 Enables transition to Normal or Standby
0 Unit is in milliseconds
1 Unit is in seconds
10 MOD_TMC_REG2
11 NOM_I TH_REG1 0000_0000 R/W D[7:0] Eight MSB bits of NOM2 current threshold register
12 NOM_I TH_REG2 0000_0000 R/W D[7:0] Eight LSB bits of NOM2 current threshold register
13 PGA_CTL_REG
14 PD_CTL_REG_1
0 Disable Chopper clock to Current channel
1 Enable Chopper clock to Current channel
0 Disable Chopper clock to Voltage channel
1 Enable Chopper clock to Voltage channel
0 Disable Current channel PGA
1 Enable Current channel PGA
0 Disable Current channel ΣΔ Modulator
1 Enable Current channel ΣΔ Modulator
0 Disable Voltage channel PGA
1 Enable Voltage channel PGA
0 Disable Voltage channel ΣΔ Modulator
1 Enable Voltage channel ΣΔ Modulator
15 PD_CTL_REG_2
0 Disable CIC1 of both channels
1 Enable CIC1 of both channels
0 Disable CIC2 of both channels
1 Enable CIC2 of both channels
0 Disable Dechopper in both channels
1 Enable Dechopper in both channels
0 Disable FIR in both channels
1 Enable FIR in both channels
0 Do not bypass PGA in Current Channel
1 Bypass PGA in Current Channel
0 Do not bypass PGA in Voltage Channel
0 Disable Current Channel Chopper
1 Enable Current Channel Chopper
0 Disable Voltage Channel Chopper
1 Enable Voltage Channel Chopper
16 PD_CTL_REG_3
0 Disable Common Mode Reference
1 Enable Common Mode Reference
0 Disable Internal Current Source
1 Enable Internal Current Source
0 Disable Internal temperature sensor
1 Enable Internal temperature sensor
0 Data Output in binary numbering system
1 Data Output in 2’s complement numbering
00 Voltage Channel
01 External Temperature Channel ETR
10 External Temperature Channel ETS
11 Internal Temperature Channel
18 ISC_CTL_REG
19 OTP_EN_REG 0000_0000 R/W
44 STATUS_REG_2 0000_0000 R
45 DEC_REG_R1_V 0100_ 0101 R/W
CIC1 Saturation Interrupt Mask Control.
Note: All the registers from address 0x19 to 0x2C are read-only.
46 DEC_REG_R2_V 0000_0100 R/W
11 CIC Output
47 FIR CTL_REG_V 0000_0000 R/W
This bit selects FIR / MA Filter in Voltage channel. averaging in MA filter in Voltage channel.
Figure 33. Application Diagram consider Eddy currents for fast changes in shunt current and related parasitic signal / ground shift generation. Note: VSENSE_IN, VSENSE_GND, MEN, and CHOP_CLK should be left unconnected.
The devices are available in a 32-pin MLF (5x5 mm) package. Figure 34. Package Drawings and Dimensions
www.ams.com Revision 0.7 62 - 65 AS8515 Datasheet - Package Drawings and Markings Notes: 1. Dimensions and tolerancing conform to ASME Y14.5M -1994. 2. All dimensions are in millimeters. Angles are in degrees. 3. Bilateral coplanarity zone applies to the exposed pad as well as the terminal. 4. Radius on terminal is optional. 5. N is the total number of terminals. Marking: YYWWVZZ. YY WW V ZZ @ Last two digits of the manufacturing year Manufacturing Week Plant Identifier Traceability Code Sublot identifier Symbol Min Nom Max A 0.80 0.90 1.00 A1 0 0.02 0.05 A2 - 0.65 1.00 A3 0.20 REF L 0.30 0.40 0.50 θ 0º - 14º b 0.18 0.25 0.30 D 5.00 BSC E 5.00 BSC e 0.50 BSC D1 4.75 BSC E1 4.75 BSC Symbol Min Nom Max D2 3.40 3.50 3.60 E2 3.40 3.50 3.60 aaa - 0.15 - bbb - 0.10 - ccc - 0.10 - ddd - 0.05 - eee - 0.08 - fff - 0.10 - N3 2
www.ams.com Revision 0.7 63 - 65 AS8515 Datasheet - Revision History
Revision History
Note: Typos may not be explicitly mentioned under revision history. Revision Date Owner Description
0.1 Dec 16, 2011 zmo/mbr Initial draft
0.2 Jan 25, 2012
Updated table information on LIN Driver (page 24) Pins 10, 11 updated in the file (Pin Assignments, Figure 33)
0.3 Mar 07, 2012 Updated power dissipation info in Absolute Maximum Ratings (page 7)
0.4 Aug 14, 2012 Updated Table 14, Figure 33.
0.5 Nov 22, 2012 zmo/mbr Updated Operating Conditions, Electrical Characteristics, Ordering
Information, Figure 12. Table 30, Table 32, Table 33, Table 45.
0.6 Mar 22, 2013
Table 1 and Table 6 updated. 0.7 Jul 26, 2013 Updated Table 30, added Figure 26 and notes to Table 35, modified Table 30, updated information in Figure 26. Jul 31, 2013 mbr Updated AS8515 Block Diagram Figure 1.
The devices are available as the standard products shown in Table 50. Note: All products are RoHS compliant and ams green. Table 50. Ordering Information
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