AS8510-ASSP

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Technical content

Datasheet sections

• 1 General Description
• 2 Key Features
• 3 Applications
• 4 Pin Assignments
• 4.1 Pin Descriptions
• 5 Absolute Maximum Ratings
• 6 Electrical Characteristics
• 6.1 Operating Conditions
• 6.2 DC/AC Characteristics for Digital Inputs and Outputs
• 6.3 Detailed System and Block Specifications
• 6.3.1 Electrical System Specifications
• 6.4 Current Measurement Ranges (across 100µΩ shunt resistor)
• 6.4.1 Differential Input Amplifier for Current Channel
• 6.4.2 Differential Input Amplifier for Voltage Channel
• 6.4.3 Sigma Delta Analog to Digital Converter
• 6.4.4 Bandgap Reference Voltage
• 6.4.5 Internal (Programmable) Current Source for External Temperature Measurement
• 6.4.6 CMREF Circuit (VCM)
• 6.4.7 Internal AVDD Power-on Reset
• 6.4.8 Internal DVDD Power-on Reset
• 6.4.9 Low Speed Oscillator
• 6.4.10 High Speed Oscillator
• 6.4.11 External Clock
• 6.4.12 Internal Temperature Sensor
• 6.5 System Specifications
• 7 Detailed Description
• 7.1 Current Measurement Channel
• 7.2 Voltage/Temperature Measurement Channel
• 7.3 Digital Implementation of Measurement Path
• 7.4 Modes of Operation
• 7.4.1 Normal Mode 1 (NOM1)
• 7.4.2 Normal Mode 2 (NOM2)
• 7.4.3 Standby Mode1 (SBM1)
• 7.4.4 Standby Mode2 (SBM2)
• 7.5 Reference-Voltage
• 7.6 Oscillators
• 7.7 Power-On Reset
• 7.8.1 SPI Frame
• 7.8.2 Write Command
• 7.8.3 Read Command
• 7.8.4 Timing
• 7.8.5 SPI Interface Timing

www.ams.com high performance needs great design. Datasheet: AS8510 Data Acquisition Device for Battery Sensors Please be patient while we update our brand image as austriamicrosystems and TAOS are now ams.

1 General Description

signals in the 0 to 1V range without the amplifier. explained in the next section.

2 Key Features

3 Applications

device AS8525 before applying to this device. Figure 1. AS8510 Block Diagram

www.ams.com/AS8510 Revision 3.5 3 - 46 AS8510 Datasheet - Contents

4 Pin Assignments

Figure 2. Pin Assignments (T op View)

4.1 Pin Descriptions

Table 1. Pin Descriptions connect 100nF to AVSS from this pin.

6 AVSS 0V Power-supply analog

9 VBAT_IN Battery voltage (high) input

10 VBAT_GND Battery voltage (low) input

11 CS Digital input with pull-up Chip select with an internal pull-up resistor (SPI Interface)

12 SCLK Digital input Clock signal (SPI Interface)

13 SDO Digital output Serial Data Input (SPI Interface)

14 DVSS

16 CHOP_CLK

17 MEN

case of a High Side Measurement application.

18 SDI Digital input Data signal (SPI Interface)

19 CLK Digital I/O

Register 08 has to be programmed.

20 INT Digital output Active High Interrupt to indicate data is ready

5 Absolute Maximum Ratings

maximum rating conditions for extended periods may affect device reliability. Table 2. Absolute Maximum Ratings

6 Electrical Characteristics

6.1 Operating Conditions

6.2 DC/AC Characteristics for Digital Inputs and Outputs

All pull-up and pull-down have been implemented with active devices. SDO has been measured with 10pF load. Table 3. Operating Conditions

1. Nominal clock frequency from external or internal oscillator.

4.096 MHz

Table 4. INT Table 5. CS Input Table 6. SDI

Table 7. SDO Output Table 9. CLK I/O with Input Schmitt Trigger and Output Buffer Table 10. SCLK with Input Schmitt Trigger

6.3 Detailed System and Block Specifications

6.3.1 Electrical System Specifications

6.4 Current Measurement Ranges (across 100µΩ shunt resistor)

Table 12. Electrical System Specifications Table 13. Current Measurement Ranges

1. V INADC = Vsh * Gain, gain deviations to be considered according to Table 15 and Table 16.
2. AVDD, DVDD of 3.3V with ±5% variation.
3. For low power current monitoring, single shot measurement is performed with internal oscillator.

Table 14. Valid Combinations of the Chopper Clock, Oversampling Clock and Decimation Ratios

6.4.1 Differential Input Am plifier for Current Channel

1. Leakage test accuracy is limited by tester resource accuracy and tester hardware.
2. For gain 100 PGA input common mode is 0V and the minimum supply is 3.15V.
3. The measurement ranges are referred only by the gain of input amplifier, while other parameters such as bandwidth etc. are pro-
4. This parameter is not measured directly in production. It is measured indirectly via gain measurements of the whole path. It is guaran-
5. Pole frequency of input amplifier changes with GAIN. The number is valid for the gain at G1, while the bandwidth will be higher for other

ranges. This parameter is not measured in production.

1. Based on device evaluation. Not tested.
2. These offsets are cancelled if chopping enabled (default).
3. Noise density calculated by taking system bandwidth as 150Hz.
4. Refer to Measurement Ranges shown in Table 13.
5. No impact on the measurement path. If the chopping is enabled, both the offset and offset drift will be eliminated.
6. For negative input voltages up to -160mV below ground, Input leakage is typically -20nA @ 65ºC due to forward conductance of

Table 15. Differential Input Amplifier for Current Channel

6.4.2 Differential Input Amplifier for Voltage Channel

1. Input for the voltage channel can be as high as 1220mV, in this high input case PGA will be bypassed.
2. Leakage test accuracy is limited by tester resource accuracy and tester hardware, especially at low temperatures due to condensing
3. For gain 100 PGA input common mode is 0V and the minimum supply is 3.15V.
4. The measurement ranges are referred only by the gain of input amplifier, while other parameters such as bandwidth etc. are pro-
5. This parameter is not measured directly in production. It is measured indirectly via gain measurements of the whole path. It is guaran-
6. Pole frequency of input amplifier changes with changing the GAIN. The number is valid for the gain at G1, while the bandwidth will be

higher for other ranges. This parameter is not measured in production.

1. Noise density calculated by taking system bandwidth as 150Hz.
2. Based on device evaluation. Not tested.
3. No impact on the measurement path. If the chopping is enabled, both the offset and offset drift will be eliminated.
4. For negative input voltages up to -160mV below ground, Input leakage is typically -20nA @ 65ºC due to forward conductance of

Table 16. Differential Input Amplifier for Voltage Channel

6.4.3 Sigma Delta Analog to Digital Converter

1. Programmable. It is defined with respect to the first decimator in the ΣΔ ADC.
2. Programmable: Internal clock is 1024/2048 kHz; external clock max is 8192 kHz.
3. Dependent on fovs, R1 and R2. The bandwidth is calculated according to the formula:

BW=fovs/(2*R1*R2); the sampling frequency at the output of the A/D converter is 2*BW.

1. Defined at maximum input signal, BW=500 Hz (1Hz to 500 Hz), fovs=1024 kHz, R1=64, fchop=2 kHz and R2=2.
2. Reference voltage might be forced from external.

6.4.4 Bandgap Reference Voltage

1. No DC current is allowed from this pin.
2. This is a design parameter and not production tested.

Table 17. Sigma Delta Analog to Digital Converter Table 18. Bandgap Reference Voltage

6.4.5 Internal (Programmable) Current So urce for External Temperature Measurement

1. Current value can be programmed in steps of 8μA from 0 to 256μA with a process error of 30%.
2. Temperature coefficient is not important since external temperature measurement is a 2 step measurement. The value specified is

guaranteed by design and will not be tested in production.

1. Maximum voltage on pin ETR (reference) can be calculated by given formula, where G is the gain of PGA (G=100).
2. Maximum voltage on pin ETR, if PGA is bypassed.
3. Maximum voltage on pin ETS, if PGA is bypassed.

6.4.6 CMREF Circuit (VCM)

6.4.7 Internal AVDD Power-on Reset

Table 19. External T emperature Measurement Table 20. CMREF Circuit Table 21. Internal AVDD Power-on Reset

1. POR pulse is always longer than t PORA whatever the slope of the supply.
2. I PORA can not be switched off.

6.4.8 Internal DVDD Power-on Reset

6.4.9 Low Speed Oscillator

6.4.10 High Speed Oscillator

1. Accuracy for limited temperature range of -20 to 65 ºC.

6.4.11 External Clock

Table 22. Internal DVDD Power-on Reset

1. V PORLO = VPORHI - VHYST where VPORLO is the lower threshold of POR.
2. V PORLO = VPORHI - VHYST where VPORLO is the lower threshold of POR.
3. I PORD can not be switched off.

Table 23. Low Speed Oscillator Table 24. High Speed Oscillator Table 25. External Clock

6.4.12 Internal Temperature Sensor

6.5 System Specifications

System Measurement Error Budget for Voltage and Current Channel. Temperature Range: -20ºC to +65ºC; Output data rate is 1kHz, VCC = 3.3V, chopping enabled.

1. These specifications are defined by taking one channel as reference and measured on the other channel.
2. System measurement error due to noise, individual block parameter drifts and non linearity. Based on evaluation, not tested.
3. System error due to offset is neglected because of chopper architecture.

Table 26. Internal T emperature Sensor internal temperature measurement.

27 Digits/C

Table 27. System Specifications Table 28. System Measurement Error Budget for Gains 5 and 25

www.ams.com/AS8510 Revision 3.5 16 - 46 AS8510 Datasheet - Detailed Description

7 Detailed Description

The AS8510 consists of two independent high resolution 16-bit SD analog to digital conversion channels. The measurement path of these two channels integrates a programmable gain amplifier, chopper and de-chopper, sigma-delta modulator, decimator and a digital filter for simultaneous measurement of Current and Voltage/Temperature. The two measurement channels, namely the Current and Voltage/Temperature measurement channels have identical data path. The input signal is amplified in the Programmable Gain Amplifier (PGA) with any of the selected gains of 1, 5, 25, 40 and 100 facilitating measurement of a wide range of Current, voltage and temperature levels. Gain Settings for different input ranges and any associated restrictions are explained in the Table 13. Offset in the measurement path is minimized with the use of a chopper and a de-chopper at appropriate stages in the data path. By default the chopper/de-chopper is ON in the measurement path. It may be disabled by programming the appropriate register. The amplified input signal is converted into a single-bit pulse-density modulated stream by the Σ-Δ Modulator. A decimator acting as a low-pass filter filters out the quantization noise and generates 16-bit data corresponding to the input signal. The decimation ratios of 64, 128 may be selected in the first filter stage. For reducing data rate further, the second stage decimation can be used. An optional FIR Filter is provided to offer matched low pass filter response typically required in lead acid battery sensor systems.

7.1 Current Measurement Channel

The voltage across a Shunt Resistor, connected in series with the Battery negative terminal, forms the input signal to the Current Measurement channel. RSHH and RSHL are the Current measurement input pins. Offset in the input signal is nullified with the use of a chopper and a de- chopper at appropriate stages in the data path. The programmable gain amplifier in the data path with programmable settings of 1, 5, 25, 40 and 100 enables measurement of current ranges from ±1A to ±1500A. The sampled input signal is converted into a single-bit pulse-density modulated stream by the Σ-Δ Modulator. A decimator acting as a low-pass filter filters out the quantization noise and generates 16-bit data equivalent to the input current signal. The programmable input sampling rate and the decimation ratio determine the output data rates. The data path can be programmed to provide 1Hz to 2 kHz rates in the various modes available. An optional FIR filter is provided to offer matched low pass filter response typically required in lead acid battery sensor systems. After enabling the current measurement channel, the delay for the availability of the first sample is two conversion cycles.

7.2 Voltage/Temperature Measurement Channel

The other two parameters of the Battery for measurement are Voltage and its Temperature. The second channel accepts signals from four independent sources through a Multiplexer as listed below: An attenuated battery voltage obtained through appropriate external resistor divider, (or) A signal from the external temperature sensor, (or) A signal from external reference, (or) A signal from the internal temperature sensor. Apart from this difference in the multiplexing of four input signals, the rest of the data path is identical to the Current measurement channel. RSHH and RSHL are the Current measurement input pins The Battery Voltage which can go up to 18V is attenuated through a Resistor Divider externally and is applied to the Voltage Channel. For Automotive Battery measurement, the Gain of the PGA should be restricted to 5 and 25. The latency for the first result from the voltage measurement channel is two conversion cycles. A second option on this measurement channel is to measure Temperature. Internally generated constant current is pumped through the Temperature Sensor with positive temperature coefficient, and, a high- precision resistor. The voltages across the sensor and the resistor form the inputs to the measurement channel one at a time. The difference between the two voltages which is independent of the magnitude of the current is used to determine the temperature accurately. The Voltage across the sensor is applied between the ETS and VSS pins and, the voltage across the high-precision resistor is applied between ETR and VSS. External Temperature measurement involves the acquisition of two signals one after the other using the same constant current source. The latency for the first result from the temperature measurement channel is two conversion cycles. A third option on the measurement channel is to measure the internal temperature. Hence, one of the three options for measurement of Battery Voltage, External Temperature and, internal temperature may be carried out by selection of appropriate inputs through the internal multiplexer selection.

7.3 Digital Implementati on of Measurement Path

Figure 3. Block Diagram of Digital Implementation density modulated output (MOD_IN) from the second order sigma delta modulator along with the oversampling frequency clock (MOD_CLK). first phase, the R1 down sampling rate can be obtained by selecting either 64 or 128 in Registers DECREG_R1_I, DECREG_R1_V in Table 33. number of samples for averaging can be any integer value from 1 to 15.

7.4 Modes of Operation

is increased to a higher rate only when a measured input signal level crosses the programmed threshold in the current measurement channel. four Modes. The State transition Diagram involving the state of Stop and the four Modes is illustrated in the Figure 4.

Figure 4. State Transition Diagram

1. Device soft reset can be written in any of the following states STOP, A_STB, SBM_ON, SBM_OFF by writing “0” into D[7] of the RESET
2. Measurement path of soft reset should be written in any the states, STOP, SBM_OFF by writing “0” into D[6] of the RESET _REG (Address
3. When soft reset is used for the measurement path or for the device, external clock needs to be disabled if the system clock is external

7.4.1 Normal Mode 1 (NOM1)

On Power-on-reset of the device, AS8510 goes into STOP State. Figure 5. When the device is configured to NORMAL Mode1 from any mode the configuration should be through the STOP state only. Figure 5. Normal Mode 1

7.4.2 Normal Mode 2 (NOM2)

threshold, the data rate is changed to the rate of NOM1 mode. illustrated in the waveform Figure 6.

Figure 6. Normal Mode 2

7.4.3 Standby Mode1 (SBM1)

consumption of the data acquisition and processing system. Figure 7. Standby Mode 1

7.4.4 Standby Mode2 (SBM2)

microcontroller only when the data sample exceeds the set current threshold. The Standby Mode can be entered only through the STOP state. Registers D,E. It should be noted here that the data is stable for Ta secs. The functionality is illustrated in Figure 8. Figure 8. Standby Mode 2

7.5 Reference-Voltage

Band gap-reference voltage is used for the ADC as a reference and for the generation of the current for external temperature measurement.

7.6 Oscillators

7.7 Power-On Reset

happens and the system status is shown in state diagram (see Figure 4). AS8510 can be programmed and by giving start command it starts working following the state machine.

Figure 9. Protocol for Serial Data Write with Length = 1

7.8.1 SPI Frame

bytes. Command is coded on the 1 first bit, while address is given on LSB 7 bits (see Table 30). the SPI interface increments the address of the previous data byte and writes/reads data to/from consecutive addresses. Table 29. CS and SCLK FALL LOW Serial data transferred on rising edge of SPI clock. Sampled at falling edge of SPI clock. FALL HIGH Serial data transferred on falling edge of SPI clock. Sampled at rising edge of SPI clock. ANY ANY Serial data transfer edge is unchanged. Table 30. Command Bits Table 31. Command Bits 0 WRITE ADDRESS Writes data byte on the given starting address. 1 READ ADDRESS Read data byte from the given starting address.

0 A6 A5 A4 A0 A1A2A3 D0 D1D2D3D4D5D7 D6

7.8.2 Write Command

For write command, C0=0. After the command code C0 is transferred, the address of register to be written is provided from MSB to LSB. are examples of write command without and with address self-increment. Figure 10. Protocol for Serial Data Write with Length = 1 Figure 11. Protocol for Serial Data Write with Length = 4

7.8.3 Read Command

frame is to be driven by the SPI master on the SPI clock transfer edge where SPI slave samples it on the next SPI clock edge. clock edge. These edges are determined as per Table 29 and examples of read command without and with address self-increment. Figure 12. Protocol for Serial Data Read with Length = 1 Figure 13. Protocol for Serial Data Read with Length = 4

1 A6 A5 A4 A0 A1A2A3

7.8.4 Timing

In the following timing waveforms and parameters are exposed. Figure 14. Write Timing for Writing Figure 15. Read Timing for Reading

7.8.5 SPI Interface Timing

Table 32. SPI Interface Timing

7.9 Control Register

This section describes the control registers used in AS8510. Registers can be broadly classified into the following categories. Table 33. Control Registers

00 DREG_I1

01 DREG_I2

02 DREG_V1

03 DREG_V2

04 STATUS_REG 0000_0000 R

05 DEC_REG_R1_I 0100_ 0101 R/W

0 Down Sampling Rate is 64

1 Down Sampling Rate is 128

00 Chopper Clock Always High

01 Divide by 256

10 Divide by 512

11 Divide by 1024

CIC1 Saturation Interrupt Mask Control.

06 DEC_REG_R2_I 1100_0101 R/W

0 Active high

1 Active low

00 FIR / MA Output

01 CIC2 Output

10 Dechop/Demod Output

11 CIC1 Output

07 FIR CTL_REG_I 0000_0100 R/W

This bit selects FIR / MA Filter in Current channel. averaging in MA filter in Current channel. architecture in both Current and Voltage channels.

00 Demodulator after CIC1

01 Demodulator before CIC1

10 Dechopper after CIC1

11 Demodulator before CIC1 with settled

08 CLK_REG

00 Internal HS Clock with No Clock Output

01 Internal HS Clock with Clock Output

10 External Clock

00 No division

01 Divide by 2

10 Divide by 4

11 Divide by 8

0 LS _CLK undivided (Low Speed clock)

1 LS _CLK divide by 2

09 RESET_REG

These two bits select the operating mode of the Device.

00 Normal Mode 1

01 Normal Mode 2

10 Standby Mode 1

11 Standby Mode 2

0 Disabled

1 Enabled

0 Retain in STOP state

1 Enables transition to Normal or Standby

0 Unit is in milliseconds

1 Unit is in seconds

10 MOD_TMC_REG2

11 NOM_I TH_REG1 0000_0000 R/W D[7:0] Eight MSB bits of NOM2 current threshold register

12 NOM_I TH_REG2 0000_0000 R/W D[7:0] Eight LSB bits of NOM2 current threshold register

13 PGA_CTL_REG

14 PD_CTL_REG_1

0 Disable Chopper clock to Current channel

1 Enable Chopper clock to Current channel

0 Disable Chopper clock to Voltage channel

1 Enable Chopper clock to Voltage channel

0 Disable Current channel PGA

1 Enable Current channel PGA

0 Disable Current channel

1 Enable Current channel ΣΔ Modulator

0 Disable Voltage channel PGA

1 Enable Voltage channel PGA

0 Disable Voltage channel ΣΔ Modulator

1 Enable Voltage channel ΣΔ Modulator

15 PD_CTL_REG_2

0 Disable CIC1 of both channels

1 Enable CIC1 of both channels

0 Disable CIC2 of both channels

1 Enable CIC2 of both channels

0 Disable Dechopper in both channels

1 Enable Dechopper in both channels

0 Disable FIR in both channels

1 Enable FIR in both channels

0 Do not bypass PGA in Current Channel

1 Bypass PGA in Current Channel

0 Do not bypass PGA in Voltage Channel

1 Bypass PGA in Voltage Channel

0 Disable Current Channel Chopper

1 Enable Current Channel Chopper

0 Disable Voltage Channel Chopper

1 Enable Voltage Channel Chopper

16 PD_CTL_REG_3

0 Disable Common Mode Reference

1 Enable Common Mode Reference

0 Disable Internal Current Source

1 Enable Internal Current Source

0 Disable Internal temperature sensor

1 Enable Internal temperature sensor

0 Data Output in binary numbering system

1 Data Output in 2’s complement numbering

00 Voltage Channel

01 External Temperature Channel ETR

10 External Temperature Channel ETS

11 Internal Temperature Channel

18 ISC_CTL_REG

19 OTP_EN_REG 0000_0000 R/W

44 STATUS_REG_2 0000_0000 R

45 DEC_REG_R1_V 0100_ 0101 R/W

CIC1 Saturation Interrupt Mask Control.

Note: All the registers from address 0x19 to 0x2C are read-only.

7.9.1 Standby Mode - Power Consumption

microcontroller through an interrupt signal on INT and goes into STOP state. started. Any measurements performed during Tsett produce invalid results. Tmeas =Tsett +T1 is the total active time needed to get a valid result. DRSBM = Tmeas/Tsbm ≈ 5ms/10s. This is the ratio of repetition time versus the active time (Device in NOM mode).

46 DEC_REG_R2_V 0000_0100 R/W

11 CIC Output

47 FIR CTL_REG_V 0000_0000 R/W

This bit selects FIR / MA Filter in Voltage channel. averaging in MA filter in Voltage channel.

7.9.2 Initialization Sequence at Power ON

Figure 16. AS8510 Device Initialization Sequence at Power ON ignored in the system. Device configuration and activation should be carried out only after the initialization period. first interrupt will occur after a time period of TADC. registers and status registers are not read during the TDATA_INVALID duration. CHOP_CLK and POR_N are internal signals of the device.

7.9.3 Soft-reset of Device Using Bit D[7] of Reset Register 0x09

Figure 17. AS8510 Device Initialization Sequence at Soft-reset

7.9.4 Soft-reset of the Measurement Path Using Bit D[7] of Reset Register 0x09

Table 34. Valid Combinations of Modulator Clock, Chopper Clock and Decimation Ratio R1

7.9.5 Reconfiguring Gain Setting of PGA

sample from the ADC is invalid. Ignore the first interrupt after the gain re-configuration. Valid data starts from the second interrupt onwards. Figure 18. AS8510 - Re-configuration of Gain Setting of PGA

7.9.6 Configuring the De vice During Normal Mode

Following registers can be programmed dynamically when the device is in operational mode (Normal mode).

7.10 Low Side Current Measurement Application

Figure 19. Application Diagram

8 Package Drawings and Markings

The product is available in a 20-pin SSOP package. Figure 20. Drawings and Dimensions

1. Dimensions & tolerancing conform to ASME Y14.5M-1994.
2. All dimensions are in millimeters. Angles are in degrees.

8.1 Recommended PCB Footprint

Figure 21. PCB Footprint

www.ams.com/AS8510 Revision 3.5 44 - 46 AS8510 Datasheet - Revision History

Revision History

Note: Typos may not be explicitly mentioned under revision history. Revision Date Owner Description

1.1 Jun 22, 2009 mbr Initial version

1.2 Dec 02, 2009 ss2, rad Updated the datasheet according to 1.8 specification Dec 08, 2009 ss2 Following modifications carried out in Table 27: 1) Deleted Max value for parameter ‘Temperature upper limit’ 2) Added Footnote 2 3) Added new parameter ‘Temperature Sensor Output (without gain calibration)

1.3 Feb 19, 2010 mbr

Updated Table 15 with PGA information Updated Voltage Measurement Updated V REFand VIN values in Table 17 and VREF in Table 18 Inserted new Table 28 - System Measurement Error Budget

2.0 June 01, 2010 mbr

Changed the pin name AGND to VCM Current source added in the block diagram Added application diagram Updated Electrical Characteristics on page 7 Updated Detailed System and Block Specifications on page 9 Updated Standby Mode - Power Consumption on page 37

3.0 Oct 29, 2010 ss2 Updates carried out across the datasheet

3.1 Nov 02, 2010 ss2 Updated Ref Voltage Offset in Table 18

3.3 Nov 26, 2010 vel Formatted figures 17, 18 in portrait mode. Index modified from page 39 Dec 03, 2010 ss2 Added Configuring the Device During Normal Mode on page 40

3.4 Mar 01, 2011 mbr /ss2

Updated General Description, Key Features, Applications, Pin Descriptions, Current Measurement Ranges, Differential Input Amplifier for Current Channel, Differential Input Amplifier for Voltage Channel, Sigma Delta Analog to Digital Converter, Bandgap Reference Voltage, System Measurement Error Budget for Gains 5 and 25, Package Drawings and Markings. Deleted Voltage Measurement. 3.5 Aug 05, 2011 mbr,ss2,vel Updated Table 14, Figure 4, Table 19, Table 18, Section 7.9.6, Figure 19. Added Section 7.9.4 Dec 31, 2012 sju Updated ordering table.

9 Ordering Information

The devices are available as the standard products shown in Table 35. Note: All products are RoHS compliant and ams green. Table 35. Ordering Information

www.ams.com/AS8510 Revision 3.5 46 - 46 AS8510 Datasheet - Copyrights Copyrights Copyright © 1997-2012, ams AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies. Disclaimer Devices sold by ams AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. ams AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. ams AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with ams AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by ams AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. The information furnished here by ams AG is believed to be correct and accurate. However, ams AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of ams AG rendering of technical or other services. Contact Information Headquarters ams AG Tobelbaderstrasse 30 A-8141 Unterpremstaetten, Austria Tel : +43 (0) 3136 500 0 Fax : +43 (0) 3136 525 01 For Sales Offices, Distributors and Representatives, please visit: http://www.ams.com/contact