AS8506

ams AG

Battery Cell Monitor and Balancer IC

Manufacturer: ams AG

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ams Datasheet, Confidential:2013-Sep [1-00] AS8506 – 1 AS8506 Battery Cell Monitor and Balancer IC The AS8506 is a battery management IC dedicated to support cell voltage measurement, monitoring, cell balancing and temperature measurement functions in Li-Ion battery stacks for electric/hybrid electric vehicles or in other industrial/consumer/PV battery applications. There are two device versions available:

The AS8506 is AEC - Q100 automotive qualified.
The AS8506C is for industri al and other applications. Ambient temperature range for both products is from -40°C to +85°C. It features cell voltage diagnosis with externally adjustable upper and lower cell voltage limits, fast cell voltage capture on request through 12-bit SAR ADC, passive cell balancing by simultaneous comparison of actual cell voltages with a reference cell voltage and temperature measurement on two external NTC sensors through 12-bit ADC. Cells that are above reference will sequentially be discharged through integrated switches and one external resistor. There is also an active balancing option through factory setting to sequentially charge cells which are below reference from an external DC-DC Flyback converter and an integrated low side driver. The device can be used flexibly for battery stacks up to 7 cells with a minimum stack voltage of 6V and a maximum stack voltage of 32V. It can be chained to support battery packs of virtually any number of cells in synchronized mode through chained clock and trigger signal. The status of the battery stack is communicated to outside world through OR’d voltage_ok signal and balance ready signal. For further understanding in regards to the contents of the datasheet, please refer to the Reference Guide located at the end of the document. General Description

AS8506 – 2 ams Datasheet, Confidential:2013-Sep [1-00] General Description Key Benefits & Features The benefits and features of AS8506, Battery Cell Monitor and Balancer IC are listed below: Figure 1: Added Value of using AS8506

Applications

The applications of AS8506 include:

The AS8506 is ideal for simultaneous cell monitoring and cell balancing in stacked energy storage systems. Current levels in the 100 mA range enables to compensate accumulative SOC mismatch over the entire cell pack.
Typical applications are - Li-Ion batteries up to 200 cells for electric vehicles, - Energy storage systems to buffer energy from PV panels or for emergency power supplies, - Battery management for e-scooters and e-bikes, - Li-Ion or ultra capacito r based board net battery management systems in the 12V/48V domain, for handheld applications like power tools, laptops and in general all Li-Ion battery powered systems. Benefits Features Reduce filter / synchronization effort. Acquired data have same time stamp to inherently generate accurate comparison results independent from load transients. Simultaneous cell voltage capture for safe operating area (SOA) monitoring and balancing. Strongly reduces data communication and data processing and thereby improves EMC robustness. Autonomous balancing and SOA monitoring. To compensate accumulative charge differences only. This mitigates cases of occasional wrong balance decisions due to flat OCV characteristic or mismatch in cell temperature Autonomous passive balancing in the 100 mA range Intrinsic inter module balancing through charge redistribution, efficiency improvement in case of leakage path due to defect induced leakage in particular cells. Option for active charge balancing with very few external components. For OCV capture, cell impedance calculation, diagnosis Absolute cell voltage read out, read out of two temperature sensors. Small form factor, low BOM 40-pin MLF (6x6) package, very low number of external components.

ams Datasheet, Confidential:2013-Sep [1-00] AS8506 – 3 General Description Block Diagram The functional blocks of this device for reference are shown below: Figure 2: AS8506 Block Diagram C_out1 C_out2 C_out3 C_out4 C_out5 C_out6 C_out7 VCELL6 LDO High Precision Reference DAC_IN[11:0] Level Shifters for Stack Communication / Status Signals EXT_RES_CTL VCELL5 VCELL4 VCELL3 VCELL2 VCELL1 VCELL7 Level Shifters DAC Pre-regulator comp1 comp2 comp3 comp4 comp5 comp6 comp7 Cnt1 Cnt2 Cnt3 Cnt4 Cnt5 Cnt6 Cnt7 Balance and VREF_H Switches Level Shifters Stack signals Stack signals VCELL[7:1] RC Oscillator & PWM Driver C-GND VCELL1 VCELL2 VCELL3 VCELL4 VCELL5 VCELL6 Cnt1H Cnt2L Cnt1L Cnt2H Cnt3L Cnt3H Cnt4L Cnt4H Cnt5L Cnt5H Cnt6L Cnt6H Cnt7L GND NC NC_T WAKE_IN BD_OUT TSECH TSECL MS_SL FD_OUT CVT_NOK_OUT VCELL7 Cnt7H Multiplexer & SAR Logic Zero Cross Detection Circuit V5V CELL_THU CELL_THL CVT_NOK_IN VREF_IN TRIG_OUT SCLK SDO SDI TEMP_IN1 TRIG_IN CS TEMP_IN2 REF_T CLK_IN Temperature Sensor / Switch Capacitor Circuit Over-temperature Monitor VREF_H CLK_OUT FD_IN WAKE_OUT V5V_IN VSUP BD_IN Reference & Threshold Generation Circuit FSM, Digital Registers, OTP Logic AS8506

AS8506 – 4 ams Datasheet, Confidential:2013-Sep [1-00] Pin Assignment Figure 3: Pin Diagram of AS8506 Pin Assignment SDO CS SCLK SDI REF_T TEMP_IN1 CELL_THL CELL_THU TEMP_IN2 V5V30 CLK_IN GND TRIG_IN NC WAKE_IN CVT_NOK_OUT BD_OUT VREF_IN FD_OUT 20NC_T CVT_NOK_IN TRIG_OUT CLK_OUT MS_SL WAKE_OUT BD_IN FD_IN VSUP VREF_H40 V5V_IN31 AS8506 MLF 6x6 GND (Exposed pad) VCELL4 VCELL3 VCELL2 VCELL7 VCELL6 VCELL5 VCELL1 TSECH TSECL C-GND

ams Datasheet, Confidential:2013-Sep [1-00] AS8506 – 5 Pin Assignment Figure 4: Pin Description Pin Number Pin Name Pin Type Description 1T S E C H Analog input / output Flyback converter transformer secondary high side

2 TSECL Flyback converter transformer secondary low side

3 VCELL7 Battery cell 7 high level pin

4 VCELL6 Battery cell 6 high level pin

5 VCELL5 Battery cell 5 high level pin

6 VCELL4 Battery cell 4 high level pin

7 VCELL3 Battery cell 3 high level pin

8 VCELL2 Battery cell 2 high level pin

9 VCELL1 Battery cell 1 high level pin

10 C-GND Power supply

input Battery cell 1 low level pin

11 NC Not connected

12 VREF_IN Analog input /

Cell voltage reference value (cell target voltage of battery)

13 GND Power supply

14 TRIG_IN

This pin triggers the cell balancing in the device. Short pulse is for receiving status and continuous ‘High’ for cell balancing. It also acts as a data line during 3-wire communication.

15 CLK_IN

Clock input pin in the Slave device. This pin also acts as a clock during 3-wire communication. Scan clock in scan mode.

16 CVT_NOK_OUT

This pin alerts when the cell voltage or the device/cell temperature is not within limits. During 3-wire communication, the CRC error is indicated on this pin. The internal device cell voltage or temperature status is ORed with CVT_NOK_IN on this pin.

17 BD_OUT

The ‘device internal balance done’ and ‘balance done from above device’ are ANDed on this pin. This pin in Master device indicates the complete system balance done. During address allocation process, this pin will be ‘High’ if BD_IN is ‘High’ .

18 FD_OUT Flyback converter gate/opto coupler drive (pad is

push-pull type) can drive up to 12mA.

AS8506 – 6 ams Datasheet, Confidential:2013-Sep [1-00] Pin Assignment

19 WAKE_IN Digital input

The wake pulse on this pin brings the IC into NORMAL mode. This pin has a pull-up resistor to the internal regulator. Should be driven with an open drain or external NMOS.

20 NC_T Analog input /

output Not connected. Only used in Test mode.

21 SDO Digital output SPI data out

22 SDI

23 SCLK SPI clock

24 CS Digital input

with pull-up SPI chip select

25 CELL_THU

Cell voltage upper threshold

26 CELL_THL Cell voltage lower threshold

27 TEMP_IN2

Temperature input2 to the IC (NTC input; if NTC is not connected, then should be connected to GND with 1K resistor).

28 TEMP_IN1

Temperature input1 to the IC (NTC input; if NTC is not connected, then should be connected to GND with 1K resistor).

29 REF_T Supply to temperature sensor (Reference voltage to

DAC and ADC).

30 V5V Power supply

LDO 5V output. 31 V5V_IN Supply to the bottom IC from the cascaded top IC.

32 WAKE_OUT Digital output

Open drain o/p on the VSUP+5V domain. WAKE_IN information will be transmitted to top device.

33 FD_IN Digital input

Flyback converter gate drive input in daisy chain connection. (If FD_IN is ‘high’ then FD_OUT will be PWM o/p in balance mode).

34 BD_IN

In cell stack system, the device gets balance done status of above device. During address allocation process if this pin is ‘High’ , then the device address is decremented by ‘1’ .

35 CVT_NOK_IN Indicates cell voltage or temperature status of above

device. Pin Number Pin Name Pin Type Description

ams Datasheet, Confidential:2013-Sep [1-00] AS8506 – 7 Pin Assignment

36 CLK_OUT

This pin propagates the clock to next device in the stack system. In case of Master device internal RC clock is transmitted on this pin to Slave device.

37 TRIG_OUT

This pin transmits the data fromTRIG_IN for balance and measurement phase. This pin is also used for propagating the data information to next device in stack system in SPI3.

38 VSUP Power supply

input Supply to the IC.

39 MS_SL Digital input

This pin informs the device whether it should act as the Master or Slave. If this pin is connected to GND, then device will act as Master. If this pin is connected to VSUP then device will act as Slave.

40 VREF_H Analog input /

High sides PMOS switch for external resistive divider. Input to VREF_IN can be taken from external resistive divider in one of the options. Pin Number Pin Name Pin Type Description

AS8506 – 8 ams Datasheet, Confidential:2013-Sep [1-00] Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under “Operating Conditions” on page 10 is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Figure 5: Absolute Maximum Ratings Symbol Parameter Min Typ Max Units Comments Electrical Parameters VVSUP Voltage at positive supply pin -0.3 42 V VSUP pin VGND Voltage at negative supply pin -0.3 0 V GND, C-GND; Reference potential VV5V_IN Voltage at high side supply -0.3 VSUP + 0.3 V MS_SL,VREF_H, TSECH and TSECL VSUP + V5V_IN High side supply from top device VSUP - 0.3 VSUP + 5.5 V TRIG_OUT, CLK_OUT, CVT_NOK_IN, FD_IN, BD_IN, WAKE_OUT VV5V Voltage at on LDO o/p pins -0.3 7 V V5V pin VESD Voltage on 5V pins -0.3 V5V+0.3 V All pins expect VSUP, VCELL1, VCELL2, VCELL3, VCELL4, VCELL5, VCELL6, VCELL7, MS_SL, WAKE_IN VCELL1 to VCELL7 Voltage on pins VCELL1, VCELL2, VCELL3, VCELL4, VCELL5, VCELL6, VCELL7 -0.3 7 V Applied cell voltages ISCR Latch-up Immunity -100 +100 mA AEC - Q100-004 Absolute Maximum Ratings

ams Datasheet, Confidential:2013-Sep [1-00] AS8506 – 9 Absolute Maximum Ratings Note(s) and/or Footnote(s): 1. Human body model: R = 1.5k Ω; C = 100pF. 2. The reflow peak soldering temperature (body temperature) is specified according IPC/JEDEC J-STD-020 “Moisture/Reflow Sensiti vity Classification for Non-hermetic Solid State Surface Mount Devices” . Electrostatic Discharge ESD Electrostatic discharge voltage AEC - Q100-002 HBM standard (1) kV VSUP, VREF_IN, SDI, SDO, CS, SCLK, CELL_THU, CELL_THL, TEMP_IN1, TEMP_IN2, REF_T, V5V, V5V_IN, MS_SL, VREF_H, NC_T GND, C-GND, CELL1 – CELL7 (Cell-voltage pins,), TSECH, TSECL, TRIG_IN, TRIG_OUT, CLK_IN, CLK_OUT, CVT_NOK_IN, CVT_NOK_OUT, WAKE_IN, WAKE_OUT, FD_IN, FD_OUT, BD_IN and BD_OUT Continuous Power Dissipation P tot Maximum power dissipation 1W Temperature Ranges and Storage Conditions Tstg Storage temperature -55 150 ºC Rthj_36 Thermal resistance package 30 ºC/W TBODY Package body temperature 260 ºC Norm: IPC/JEDEC J-STD-020 (2) MSL Moisture Sensitive Level 3 Symbol Parameter Min Typ Max Units Comments

AS8506 – 10 ams Datasheet, Confidential:2013-Sep [1-00] Typical Operating Characteristics All defined tolerances for external components in this specification need to be assured over the whole operation conditions range and also over lifetime. Figure 6: Operating Conditions Symbol Parameter Min Typ Max Unit Note VSUP Positive supply voltage 6 32 V Normal operating condition VSS Negative supply voltage -0.3 0 V With reference to all the voltages TAMB Ambient temperature -40 85 ºC Maximum junction temperature (TJ) 115ºC ISUPP , nom Supply current, NORMAL mode 23 6 m A V S U P = 3 2 V , i n NORMAL mode Supply current, NORMAL mode, With External Components 15 20 40 mA VSUP=32V, in the balancing phase with stack connection (50% PWM duty cycle) I SUPP , sleep Supply current, SLEEP mode 10 17 35 μA Typical Operating Characteristics

ams Datasheet, Confidential:2013-Sep [1-00] AS8506 – 11

Electrical Characteristics

Device Level Specifications Figure 7: Device Level Specifications Symbol Parameter Min Typ Max Unit Note Vcell_in Cell Input voltage measurement 1.8 4.5 ADC/DAC ADC/DAC Reference ±7 ±15 mV DAC_error Error of the DAC 2 mV 0.1% error because of the DAC/Guaranteed by design Com_off Error because of the comparator resolution 1 mV Guaranteed by design Sign_path_accuracy Signal path accuracy ±5 ±15 mV Typical value is from the lab evaluation data. Maximum value is from the test data. T INITIALIZATION Initialization time 50 ms After Initialization, the system will go to sleep mode and waits for wake signal. T WAKE-UP Wake up time from the Wake signal to system wait mode 75 ms After wake signal, device enters into wait mode and stays for two sec for TRIG_IN signal, if no TRIG_IN event occurs, device goes to sleep mode. Tmeas Cell voltage and Temperature measurement time 16 ms At10KHz clock time Tspi3_read5k SPI3 read time for single channel measurement 13.6 ms At 5KHz clock time Tspi3_read20k 3.4 At 20KHz clock time Tspi3_read40k 1.7 At 40KHz clock time

AS8506 – 12 ams Datasheet, Confidential:2013-Sep [1-00] Low Dropout Regulator (5V Output LDO) -40ºC < TJ < 115ºC; all voltages are with respect to ground (GND); positive current flows into the pin, NORMAL operating mode, if not otherwise mentioned. The LDO block is a linear voltage regulator, which provides a regulated 5V. Figure 8: LDO Parameters Note(s) and/or Footnote(s): 1. In NORMAL mode, maximum load current will be 50mA. After internal thermal shutdown, current limit is 20mA. 2. The LDO is disabled in SLEEP mode. Symbol Parameter Min Typ Max Unit Note VSUP Input supply voltage 6 12 32 V V5V Output voltage range 4.75 5.0 5.25 V ILOAD Load Current 50 mA ICC_SH Output short circuit current 85 250 mA NORMAL mode PSRR PSRR dB f=1kHz / No production test 35 f=1MHz / No production test CL1 LDO output Capacitor 1 2.2 10 μF Electrolytic ESR1 1 10 Ω CL2 LDO output Capacitor 2 100 220 nF Ceramic ESR2 0.02 1 Ω

ams Datasheet, Confidential:2013-Sep [1-00] AS8506 – 15 40ºC < TJ < 115ºC; all voltages are with respect to ground (GND). Figure 13: PWM Driver Symbol Parameter Min Typ Max Unit Note V5V Output voltage 4.5 5 5.5 V FPWM Frequency of PWM 25 100 200 KHz CMOS load mode, Optocoupler load modeFDuty Duty cycle 22 25 28 % 12 15 18 % 17 20 23 % 27 30 33 % 30 35 38 % 37 40 43 % 42 45 48 % 47 50 53 % F duty_error Duty cycle error 7 12 20 % trpwm Rise time 30 50 80 ns CMOS load mode, Optocoupler load mode Guaranteed by designtf pwm Fall time 30 50 80 ns Idriveopto Driver strength 10 12 mA Optocoupler load mode Cloadfd_out Driver switch load capacitance 60 100 pF

ams Datasheet, Confidential:2013-Sep [1-00] AS8506 – 17 External Temperature Thresholds -40°C < TJ < 115°C; all voltages are with respect to ground (GND). Figure 16: External Temperature Thresholds Symbol Parameter Min Typ Max Unit Note Ref_ext_warn/sutdown Code 0000 3.084 3.165 3.238 V 16 reference thresholds are with a step of 66mV. Code 0001 3.148 3.231 3.306 Code 0010 3.213 3.297 3.373 Code 0011 3.277 3.363 3.441 Code 0100 3.341 3.429 3.508 Code 0101 3.406 3.495 3.576 Code 0110 3.470 3.561 3.643 Code 0111 3.534 3.627 3.711 Code 1000 3.599 3.693 3.779 Code 1001 3.663 3.759 3.846 Code 1010 3.727 3.825 3.914 Code 0011 3.792 3.891 3.981 Code 0100 3.856 3.957 4.049 Code 0101 3.920 4.023 4.116 Code 0110 3.984 4.089 4.184 Code 0111 4.049 4.155 4.25

AS8506 – 20 ams Datasheet, Confidential:2013-Sep [1-00] Electrical Characteristics for Digital Inputs and Outputs All pull-up, pull-downs have been implemented with active devices. Figure 21: Digital Inputs and Outputs Port Type Symbol Parameter Min Typ Max Unit Note CS INPUT Schmitt Trigger Vt- Negative-going threshold 1.62 2.22 V V5V=5V Vt+ Positive-going threshold 2.27 3.42 V Ilil_cs Pull-up current -100 -30 μA In CS pad, Pulled up to V5V. (ISUP_HV) SDO OUTPUT Tristate VOH High level output voltage 2.5 V BBC4C_HV, PPTRIM_PDIO VOL Low level output voltage 0.4 V VSUP ≥ 6V VIH High level input voltage 0.7*V5V V VIL Low level input voltage 0.3*V5V V IO Output drive current 4m A SCLK, SDI IO Buffer VIH High level input voltage 0.7*V5V V SDI is ICC_HV (PPRTIM_MODE) VIL Low level input voltage 0.3*V5V V SCLK is ICC_HV (PPRTIM_PCLK)

ams Datasheet, Confidential:2013-Sep [1-00] AS8506 – 21 Note: Test limits for Iih and Iil are 1.0uA and -1.0uA for input pads. CVT_NOK_OUT, BD_OUT, TRIG_OUT, CLK_OUT OUTPUT Buffer VOH High level output voltage 2.4 V BU2SC_HV for CVT_NOK_OUT, BU1C_HV for BD_OUT, BU4SC_HV for TRIG_OUT and CLK_OUT V OL Low level output voltage 0.4 V VSUP ≥ 6V IO Output drive current 4/2/1 mA FD_OUT OUTPUT Buffer VOH High level input voltage 2.4 V BU24SC_HV for FD_OUT VOL Low level input voltage 0.4 V VSUP ≥ 6V IO Output drive current 24 mA MS_SL INPUT Buffer VIH High level input voltage VSUP V High voltage input pad VIL Low level input voltage 0.3*V5V V CLK_IN, TRIG_IN INPUT Schmitt Trigger Vt- High level input voltage 1.62 2.22 V ISC_V5_HV Vt+ Low level input voltage 2.27 0.3*V5V V FD_IN,BD_IN, CVT_NOK_IN INPUT Buffer VIH High level input voltage 0.7*V5V V ICC_V5_HV VIL Low level input voltage 3.42 V WAKE_IN Pull up current Ipull_up Pull-up current -100 -30 μA Internal pull Port Type Symbol Parameter Min Typ Max Unit Note

AS8506 – 22 ams Datasheet, Confidential:2013-Sep [1-00] Detailed Description The device consists of the following blocks:

PWM driver
LDO_5V with 5V / 50mA output
Temperature monitor block
High precision bandgap reference
DAC for the reference voltage generation
SAR ADC for cell voltage and external temperature measurement
Oscillators for PWM drive and for the digital logic
P r e - R e g u l a t o r
SC Comparator
Weak cell detection logic
PORs on different supplies Voltage Regulator (LDO_5V) Power input to the LDO is VSUP pin. It is switched ON when the device is in NORMAL mode and switched OFF in SLEEP mode. The LDO takes the input from Band gap and scales it up to the required voltage. It starts charging only after entering NORMAL mode. This LDO is the supply for DAC, the PWM driver and Cell voltage comparators.It’s additional features are as follows:
Stability is better than ±2.5% over input range.
Load current up to 50mA. High Precision Bandgap (HPBG) AS8506 has a high precision bandgap to generate accurate reference. This reference voltage is used to generate reference for DAC and ADC. HPBG is trimmed with respect to temperature. Variation of the bandgap with temperature is ±3mV in the temperature range from -40ºC to 115ºC. External Temperature Monitor and Measurement Two sensor inputs TEMP_IN1 and TEMP_IN2 with a comparator on each pin, are available. If the temperature sensor connected to TEMP_IN1 crosses its threshold, then a warning flag is set in the device (status can be read through SPI) and the device will continue balancing. If the temperature sensor connected to TEMP_IN2 crosses its threshold, then a flag is set in the device and balancing is stopped; but the device continues to stay in NORMAL mode for maintaining synchronism. In both the cases, the microcontroller will be interrupted by a pulse on CVT_NOK_OUT pin. Detailed Description

ams Datasheet, Confidential:2013-Sep [1-00] AS8506 – 23 Detailed Description In case the external temperature sensors are not being used, then both the inputs must be connected to GND pin through 1k resistor. In the measurement phase, external temperature is measured through the SAR ADC. Both channels of temperature will be measured and stored in temp_in1_lsb_reg to temp_in2_msb_reg . Internal Temperature Monitor The internal temperature monitor has two thresholds at T jwarn 125ºC and T jshut 135ºC . If the internal temperature exceeds 125ºC, then a warning flag is se t in the device (status can be read through SPI) and the de vice will continue balancing. If the internal temperature exceeds 135ºC, then a flag is set in the device and balancing is stop ped; but the device continues to stay in NORMAL mode for maintaining synchronism. In both the cases, the microcontroller will be interrupted by a pulse on CVT_NOK_OUT pin. The balance recovery temperature is 115ºC. PWM Generator In the Balance phase of the AS8506, based on the decision made during the Compare phase, some part of the cell is charged with the Flyback converter. To drive the external Flyback converter, AS8506 generates a PWM signal to drive external FET or Optocoupler or Isolation device. The frequency and of the PWM generator can be controlled by timer_cntl_reg register. PWM frequency is not used for the passive balancing. RC Oscillator The AS8506 has a trimable RC oscillator. It is designed to generate f osc-dig clock for the digital circuit and for the clocking of the IC. Each oscillator will be trimmed with the process to get the accuracy to f osc-accy with 5-bit OTP Factory trim code. DAC for the Reference Generation AS8506 has a 12-bit DAC to generate the cell reference voltage, cell threshold low and high voltage. The DAC code is written into AS8506 with SPI interface from microcontroller. The output of the DAC is given to one of th e inputs of the comparators, to compare the cell voltages synchronously. Reference for the DAC is 4.5V, which is internally generated and is available as reference for temperature inputs on REF_T.

AS8506 – 24 ams Datasheet, Confidential:2013-Sep [1-00] Detailed Description SAR ADC AS8506 has a 12-bit SAR ADC to measure the cell voltage and external temperature. The SAR ADC uses the 12-bit DAC to generate the digital code. The SAR ADC range is 1.8V to 4.5V for cell voltage measurement and 0.2V to 4.5V for the temperature measurement. Cell voltage and temperature is measured in the short trigger phase. After the trigger goes ‘high’ , compare phase starts and then all the cell voltages and external temperature are measured and stored in the digital registers. Pre-Regulator AS8506 has an internal pre-regulator, which generates supply voltages for the internal blocks. Pre-Regulator output is used as a supply for the oscillators. All the digital logic and the FSM will work on the pre-regulator supply. In SLEEP mode only the pre-regulator will be working along with the WAKE_IN detect circuit. Cell Threshold AS8506 has the potential to set the two threshold levels to the cell voltage through pins CELL_THU and CELL_THL . These values can be set externally, (or) through OTP trim bits, (or) from the external microcontroller by writing DAC code into the cell threshold registers in the register space. Weak Cell Detection AS8506 has the ability to detect the weak cell. During load conditions, if the cell reaches vo ltage of about 0.1V to -0.2V, then this variation is detected and stored in the zero cross detection register. This event is indicated to the master device by a pulse on CVT_NOK_OUT pin in Compare and Balance phase. The master device indicates the microcontroller by setting CVT_NOK_OUT ‘high’ . In WAIT mode only this will be stored in the register; there won’t be any CVT_NOK_OUT to μC. The register is cleared on μC reading. External Resister Divider Control AS8506 has the provision to enable the external divider to give the desired cell voltage to the at VREF_IN pin. External resister divider can be co nnected between VREF_H pin to ground. Calculate the external resister divider values such that the output of the divider will provide the desired reference value. When comparison is not happ ening, this divider can be disabled using SPI.

ams Datasheet, Confidential:2013-Sep [1-00] AS8506 – 25 Detailed Description PORs on Different Supplies AS8506 has power-on-reset blocks on VSUP , V5Vand V5V_IN supply pins. The values for POR and Reset thresholds are given in Figure 20 . Figure 22: Power-up Sequence of VSUP , V5V and VSUP+5V VSUP_POR VSUP_RESET VSUP_POR VSUP V5V_5V_POR V5V_5V_RESET V5V_5v_POR V5V_5V V5V_POR V5V_POR V5V_RESET V5V

AS8506 – 26 ams Datasheet, Confidential:2013-Sep [1-00] Detailed Description AS8506 System Operation The AS8506 battery stack system can be set up by configuring one AS8506 device as ‘Master’ and the rest as ‘Slave’ devices. The AS8506 Master device is connected to the microcontroller, and the Slave devices are connected to Master through a daisy-chain of 3-wire customized SPI protocol. The microcontroller can communicate to the Slave devices through the Master. On power-up of the system, the microcontroller must assign an address to al l AS8506 devices including the Master. The microcontroller can assign the address to AS8506 devices by initiating the address allocation process, by writing a top most Slave device address into dadd_for_allc_reg register of Master and then writing ‘07’ data into spi3_cmd_reg . Once the address allocation process is successful, the microcontroller can start the cell balancing. If cell balancing or check status command is not triggered by the microcontroller, after WAIT mode timeout period all devices enter into SLEEP mode. The complete system communicat ion procedure is explained below.

The microcontroller gives wake pulse on WAKE_IN to bring the Master and Slaves in NORMAL mode.
After the wake-up time period, the microcontroller (μC) sends the reference voltage digital code to the Master device through a 4-wire SPI.
After receiving the digital re ference code from μC, the Master device initiates a 3-wi re custom SPI operation to send the digital reference code to the Slave devices.
The microcontroller waits for the 3-wire SPI operation time period. After the 3-wire SPI time period, it initiates the cell balancing through TRIG_IN . The balancing will continue as long as TRIG_IN is ‘High’.
The microcontroller can change the reference value at any time by making TRIG_IN ‘Low’ and initiating a 4-wire SPI with new value of reference code. From here on, the procedure is same as from point 3.
The balance done is indicated on BD_OUT pin.
The failure in the 3-wire SPI operation is indicated on CVT_NOK_OUT pin.

ams Datasheet, Confidential:2013-Sep [1-00] AS8506 – 27 Detailed Description Figure 23: Functional Diagram of AS8506 MASTER MICRO PROCESSOR SLAVES Sleep mode Sleep mode Wake up pulse by uC Wake up pulse by uC Wake up pulse by uC 4-wire SPI write 4-wire SPI Read 3-wire CUSTOM Read 3-wire CUSTOM write CELL Balancing CELL Balancing 4-wire SPI write 4-wire SPI Read Normal mode Balance Reference voltage from uc through 4 wire SPI operation (DAC code) MASTER module initiates a 2 wire SPI operation to send the Balance Reference voltage from uc to slave modules (DAC code) Trigger from uC on TRIG_IN pin for cell balancing operation cell Balancing to reference value set by uC. based on current status of stack voltage new Balance Reference voltage from uc through 4 wire SPI operation (DAC code) MASTER module initiates a 2 wire SPI operation to send the new Balance Reference voltage from uc to slave modules (DAC code) 3-wire CUSTOM Read 3-wire CUSTOM write CELL Balancing CELL Balancing Trigger from uC on TRIG_IN pin for cell balancing operation cell Balancing to reference value set by uC. uC reference voltage calculator found change in reference (average) voltage uC reference voltage calculator found change in reference (average) voltage

AS8506 – 28 ams Datasheet, Confidential:2013-Sep [1-00] Detailed Description Functional State Diagram Figure 24: Finite State Machine Mode Initialization Phase Power ON Vsup POR V5V LDO ON V5V POR OTP Load OTP Load done long_trigger short_triggerNo trigger Timeout Wake_pulse V5V_por OSC clock ON Normal Mode Compare phase cell balance phase V5V LDO ON OSC clock ON Wake Mode V5V LDO ON OSC clock ON Sleep Mode V5V LDO OFF OSC clock OFF Pre-reg ON Wait Mode Wait for µC Trigger (X mS) V5V LDO ON OSC clock ON No trigger Normal Mode Compare phase and ADC Measurement phase V5V LDO ON OSC clock ON

ams Datasheet, Confidential:2013-Sep [1-00] AS8506 – 29 Detailed Description Operating Modes The AS8506 has two main operating modes NORMAL and SLEEP, and has two transition modes WAIT and WAKE. The transition modes are intermediate modes for switching from SLEEP to NORMAL and vice versa. The detailed operation of each mode is explained in subsequent sect ions. The initialization phase is explained in “Initialization Sequence” on page 36 . NORMAL Mode The device enters into NORMAL from WAKE when it receives a short or long trigger. The NORMAL mode is a full functional mode, where all the power supply and analog blocks are in ON-state and the digital is fully functional. The NORMAL mode has two phases of operation:

Diagnosis phase
Balance phase Diagnosis Phase In Diagnosis phase AS8506 detects the number of cells connected to the device. The connected cell voltages are then compared with upper & lower thresholds and target cell voltage of all cells connected. Upper and lower cell voltage thresholds as well as target cell voltages are provided from external in analog or digital format. The Diagnosis phase sequence of operation is explained below.
Detects number of cells connected to the device by comparing each cell terminal s to cell detect threshold voltage.
Simultaneously compares each connected cell voltage with set lower operating voltage threshold Vlimit_L. If any of the cell voltages is less than the set lower operating threshold, then an in dication is given on CVT_NOK_OUT pin stating that one/more cell voltages are not within the operating voltage threshold range. Each cell status is stored in cel_low_thsld_stat_reg register.
Simultaneously compares each connected cell voltage with set higher operating voltage threshold Vlimit_H. If any of the cell voltages is greater than the set higher operating threshold, then an indication is given on CVT_NOK_OUT pin stating that one/more cell voltages are not within the operating voltage threshold range. Each cell status is stored in cel_high_thsld_stat_reg register.
Simultaneously compares each connected cell voltage with reference value. This result is stored in cel_ref_stat_reg register and used in balance phase. Cell reference can be provided by microcontroller by writing into register or by provid ing input at external pin VREF_IN .
Enables the SAR ADC and measures each cell voltage and two temperature inputs sequentially. The 12 bits cell voltage and temperature inputs information is stored in respective registers.

AS8506 – 30 ams Datasheet, Confidential:2013-Sep [1-00] Detailed Description At the end of the Diagnosis phase, if trigger signal is ‘High’ then it enters into Balance phase. If trigger signal is ‘Low’ it enters into WAIT mode. The Diagnosis phase without the cell voltage measurement with SAR ADC is called Compare phase. Balance Phase The Balance phase is basically a charging cycle in case of active balancing and a discharging cycle in case of passive balancing. The Balance phase is divided into 7 time slots. The device will move through all 7 time slots irrespective of number of cells connected to the device. This is done to keep synchronization between each module in case of battery stack system. One time slot is assigned to each cell (sequential order) for charging or discharging. The period of ti me slots is programmable (see “Status Registers” on page 52 ). In each time slot, following operations are done.

Check CVT_NOK flag status. If CVT_NOK flag is set, then no operation is done till time slot is over. If CVT_NOK flag is not set, then move to the next step.
Based on Diagnosis phase results, shuttle switch corresponding to current time sl ot cell is switched ON for charging that cell in case of active balancing, and discharging in case of passive balancing.
The PWM generator is enabled and PWM driver start driving the Flyback converte r FET (external component) in case of active balancing. The PWM frequency and duty cycles are factory programmable and also register controllable. In case of stac k system, the bottom module PWM driver is enabled when there is a request of charging or discharging from top module on FD_OUT pin.
At the end of the current time slot, stop the PWM generator and then open the corresponding shuttle switches. The device moves to the next time slot. In the Balance phase, at any point, if the trigger input goes ‘Low’ , then the device suspends balancing operation and enters into WAIT mode. Sleep Mode This is the least power consumption mode of AS8506. In this mode only pre-reg is ON, rest all analog blocks are OFF and digital clock is disabled. Only a digital wake detection circuit is active. The device enters into this mode when there is no trigger from microcontroller for time greater than WAIT mode timeout period. Wait Mode This mode is a transition mo de, where the device waits for command on TRIG_IN pin either from microcontroller, (or) from below module in case of stack system. The device will be in this state for T WMODE_TOUT period. After the timeout, the device

ams Datasheet, Confidential:2013-Sep [1-00] AS8506 – 31 Detailed Description enters into SLEEP mode. In the WAIT period all power blocks are ON, all analog blocks are ON and digital is also functional. In this mode, power consumption is lesser than NORMAL mode because there are no charge balancing activities being carried out. Wake Mode This is also a transition mode, where the device does initialization after exiting SLEEP mode. In the SLEEP mode if AS8506 receives a wake pulse of width T WAKE, the device enters into WAKE mode. In the WAKE mode device enables the V5V LDO and waits for V5V_por_n sign al. Once V5V_por_n signal becomes ‘High’ , the device enters into WAIT mode. An example of Compare and Balance (active balance) phase sequence with respect to time is given in Figure 25 . In this example it is assumed that only 6 cells are connected to AS8506 and comparators’ outputs at Diagnosis phase is “ 010010X ”; Where: ‘0’ indicates respective cell voltage is less than target voltage and needs charging. ‘1’ indicates respective cell voltage is more than target voltage and needs charging. ‘X’ indicates no cell is connected to respective comparator and output is neglected. Figure 25: Diagnosis and Balance Phase with Time Sequence for AS8506 CELL1 TIME SLOT CELL2 TIME SLOT CELL3 TIME SLOT CELL4 TIME SLOT CELL5 TIME SLOT CELL6 TIME SLOT CELL7 TIME SLOT Cell Detection Comparision Cell Lower Threshold comparision Cell Higher Threshold comparision Cell reference comparision Cell Detection Comparision Cell Lower Threshold comparision Cell Higher Threshold comparision Cell reference comparision Balance PhaseCompare Phase Compare Phase Cell7 not connected 010010X PWM PWM PWM PWM Charging Charging Charging Charging Cell7 not connected 000000X Cell Connected Vcell1 < Vrdiv Need Charging Idle Time Idle Time Idle Time Cell Connected Vcell2 > Vrdiv Don’t Need Charging Cell Connected Vcell3 < Vrdiv Need Charging Cell Connected Vcell4 < Vrdiv Need Charging Cell Connected Vcell6 < Vrdiv Need Charging Cell Connected Vcell5 > Vrdiv Don’t Need Charging Cell Not Connected Tc_slot Tc_slot Tc_slot Tc_slot Tc_slot Tc_slot Tc_slot

AS8506 – 32 ams Datasheet, Confidential:2013-Sep [1-00] Detailed Description Wake-up Event The AS8506 device comes out of SLEEP mode by a wake pulse on the WAKE_IN pin. To avoid false wake by noises on the WAKE_IN , the wake signal (Low pulse) is taken through a low-pass filter from WAKE_IN pin. When a pulse of width Twake_pulse is given on the WAKE_IN by the microcontroller, the device wakes up and enters into WAKE mode. The low-pass filter discards all signals having width less than T filter_min and allows all signals with width greater than T filter_max . The filter is uncertain in T uncertain region. The negative edge which is passing through the filter will wake the device from SLEEP mode. In chain of AS8506 devices, to propagate the negative edge the microcontroller has to give minimum low pulse of width T wake_pulse . Before entering into SLEEP mode the wake pin must be ‘High’ . Figure 26: WAKE-UP Signaling WAKE_IN wake_in_fltrd Tfilter_min Tfilter_max Tuncertain Tuncertain Twake_pulse Tfilter_delay

ams Datasheet, Confidential:2013-Sep [1-00] AS8506 – 33 Detailed Description Trigger Event The AS8506 device enters into NORMAL mode only when a valid command is present on the TRIG_IN pin. There are two commands in the device.

Diagnosis command
Cell balance command When a high pulse of width T diag_cmd as shown in Figure 27 , is given on TRIG_IN pin, the device performs the following operations.
Compares all connected cell voltages with the set lower operating voltage threshold, and if any of the cell voltage is less than lower threshold, th en sets a corresponding flag in the cel_low_thsld_stat_reg register. This is indicated by high pulse on CVT_NOK_OUT pin.
Compares all connected cell voltages with the set higher operating voltage threshold, and if any of the cell voltage is more than higher threshold, then sets a corresponding flag in the cel_high_thsld_stat_reg register. This is indicated by high pulse on CVT_NOK_OUT pin.
Sets a corresponding flag in the temp_stat_reg register if ambient temperature or inte rnal chip temperature is higher than respective thres holds. This is indicated by high pulse on CVT_NOK_OUT pin.
It will enable SAR ADC and starts measuring each cell voltage, and then measures temperature channel measurement. The 12 bits digital value will be stored in corresponding registers. Thus, on diagnosis command the de vice gives the cell operating voltage, ambient temperature and internal temperature status with respect to its safe operating range. When the TRIG_IN pin is ‘High’ for longer than the status command, the device enters into Balance phase. Depending upon cell voltage status, the device starts balancing the cell voltages. The cell voltage balancing is continued till the high voltage on the TRIG_IN pin. As soon as TRIG_IN goes ‘Low’ , the device stops balancing and enters into WAIT mode. Thus, the microcontroller has full control over the balancing time and stop balancing whenever required.

AS8506 – 34 ams Datasheet, Confidential:2013-Sep [1-00] Detailed Description Figure 27: TRIG_IN Command Signaling WAIT MODE WAIT MODE WAIT MODE NORMAL MODE (Diagnosis phase) NORMAL MODE (Compare + Balance phase) Tstatus_cmd Tbal_cmd Diagnosis Command Cell Balance Command TRIG_IN Device State

ams Datasheet, Confidential:2013-Sep [1-00] AS8506 – 35 Detailed Description Balancing Algorithm Figure 28: Cell Balancing Algorithm compare all connected cells with reference voltage identify and store toggle of connected cell comparator outputs All connected cell comp toggle? Active – balancing Charge cells with comp o/p = 0. Passive – balancing discharge cell with comp o/p = 1

7 Time slot

Over ? NO generate Internal Balance done YES NO YES BD_OUT BD_IN Trigger

AS8506 – 36 ams Datasheet, Confidential:2013-Sep [1-00] Detailed Description Initialization Sequence The power-up initialization sequence diagram for AS8506 is shown in Figure 29 .

When the power supply is swit ched ON, initially VSUP POR output Vsup_por_n is ‘Low’; hence all the digital logic will be in reset state.
Once the VSUP crosses the Vsup_por_th, the VSUP POR output becomes ‘High’ enabling the oscillator and high-precision bandgap (HPBG) block.
The digital block is now operational. It will now enable the V5V LDO and waits for V5V_po r_n high signal from the V5V POR block.
Once the V5V crosses V5V_por_ th, the V5V_por_n will be ‘High’. The OTP auto load comma nd is generated by ‘High’ on otp_por_n sign al. Now the device waits for T auto_load period for OTP contents to load into digital local registers.
After the OTP contents are loaded into digital local registers, the device power-up sequence is completed. The device enters into SLEEP mode. In SLEEP mode, the LDO, oscillator and HPBG are disabled.
The wake-up circuit monitors the WAKE_IN pin for wake-up pulse. When a wake-up pulse is received, the oscillator and HPBG block ar e enabled and device enters into WAKE mode. In the WAKE mode, the device enables V5V LDO and waits for V5 V_por_n high signal.
Once the V5V crosses V5V_por_ th, the V5V_por_n will be ‘High’ and the device enters into WAIT mode. In WAIT mode the device waits for trigger pulse on TRIG_IN pin from microcontroller. In this state, if a short or long pulse trigger signal is received on TRIG_IN within T wmode_tout period, the AS8506 enters into NORMAL mode and performs required operatio ns based on trigger pulse.

ams Datasheet, Confidential:2013-Sep [1-00] AS8506 – 37 Detailed Description Figure 29: Power-up Initialization Sequence VSUP Vsup_por_n ldo_en V5V V5V_por_n otp_por_n Tauto_laod otp_load osc_en TRIG_IN wait_timer SLEEP MODEINITIALIZATION NORMAL Wake Pulse Continue WAKE MODE WAIT MODE Vsup_por_th V5V_por_th V5V_bor_th V5V_por_th hp_bg_en Thp_bg_stl Thp_bg_stl WAIT MODE WAKE_IN TINITIALIZATION TWAKE-UP

AS8506 – 38 ams Datasheet, Confidential:2013-Sep [1-00] Device Interface A 4-wire SPI is used to communicate with the device. Pins CS, SCLK , SDI , and SDO are used for SPI interface. Serial Peripheral Interface The Serial Peripheral Interface (SPI) provides the communication link with the microcontroller. The SPI is configured for half-duplex data transfer. The SPI in AS8506 provides access to the status registers, control registers and test registers. The SPI is also used to enter into test and OTP modes. This interface is only Slave interf ace and only Master can initiate the SPI operation. Th e SPI also supports block data transfer where sequential register data can be accessed with single SPI command. The SPI can work on both the clock polarities. The polarity of the clock is dependent on the value of SCLK at the falling edge of CS. At the falling edge of CS,

If SCLK is “1”, then the SPI is negative edge triggered.
If the SCLK is “0” , then SPI is positive edge triggered logic. see Figure 30 for more details. Figure 30: SPI Clock Polarity Table CS SCLK Description ↓ Low Serial data is transferred at rising edge and sampled at falling edge of SCLK. ↓ High Serial data is transferred at falling edge and sampled at rising edge of SCLK. Device Interface

ams Datasheet, Confidential:2013-Sep [1-00] AS8506 – 39 Device Interface The SPI protocol frame is divided into two fields.

The header field
T h e d a t a f i e l d The header field is 1 byte long; containing a read/write command bit, 1 reserved bit, and 6 address bits. The SPI frame format is shown in Figure 31 . In the data phase MSB is sent first and LSB is sent last. Figure 31: SPI Frame Format SPI Write Operation The SPI write operation begins with clock polarity selection at negative edge of CS (see Figure 30 ). Once the clock polarity is selected, the SPI write command is given by providing ‘0’ in R/W bit of the header field in first sampling edge at SDI pin. The next bit in header field is reserved and set to ‘0’ . The 6 bits address of register to be written is provided at SDI pin in next six consecutive sampling edges of SCLK. The data to be written is followed by last bit of header field. With each sampling edge a bit is sampled starting from MSB to LSB. During complete SPI write operation the SCSN has to be ‘Low’ . The SPI write operation ends with positive edge of SCSN. The waveform for SPI write operation with sing le data byte is shown in Figure 32 and Figure 33 . R/W A0A1A2A3A4 Header Field Data Field 1 byte Integer Multiple of Bytes DATA Reserved Bit 6 bits Address 0 – WRITE 1 – READ 0A 5

AS8506 – 42 ams Datasheet, Confidential:2013-Sep [1-00] Device Interface Figure 36: SPI Read Operation with Positive Clock Polarity and 1 Byte of Data Field R0 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Sampling Edge High Impedance Sate SCLK SDI SDO SCSN

ams Datasheet, Confidential:2013-Sep [1-00] AS8506 – 43 Device Interface In case of SPI block read operation, first data byte is read from addressed register same as sing le byte read operation. After first data byte read, Master can read next consecutive addressed data by keeping CS ‘Low’ and giving clock on SCLK as per clock polarity selection. At the end of every eighth data bit, the address pointer is incremented to next consecutive address location. In this way Master can continue reading from consecutive register address locations. The waveform is shown in Figure 37 . Figure 37: SPI Block Read Operation with Negative Clock Polarity Address Allocation Process During the system configuration the microcontroller has to allocate a unique address to each of the AS8506 devices including the Master to co mmunicate with SPI3. The microcontroller before initiating the address allocation process, it writes top most device address into allcd_dev_add_reg of the Master through 4-wire SPI. The microcontroller can initiate the address allocation process by writing ‘100’ command code and setting D0 to 1 in spi3_cmd_reg register. By sighting ‘1’ at spi3_cmd_reg [0], the Master init iates a SPI3 address allocation write with top most device a ddress as data. The address “000000” is reserved as broadcas t address visible to all devices. The address allocation process is explained for six AS8506 devices (including Master) stack system in Figure 38 . CS SCLK SDI SDIO 1 0 A A A A A D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D Data D7-D0 at Address A5-A0 is read here Data D7-D0 at Address A5-A0 +1 is read here Data D7-D0 at Address A5-A0 +2 is read here Data D7-D0 at Address A5-A0 +3 is read here Data D7-D0 at Address A5-A0 +4 is read here A

AS8506 – 44 ams Datasheet, Confidential:2013-Sep [1-00] Device Interface Figure 38: Address Allocation Process C1 C0 TST CLK-IN/OUT TRIG-IN/OUT Address of 6th Device Address of 5th Device Address of 4th Device Address of 3rd Device Address of 2nd Device Address of 1st Device (Master) CVT_NOK_OUT6 CVT_NOK_IN5 CVT_NOK_OUT1 (Master) New Address = 6 6 -1 = 5 6-1=5 Address = X Address = X Address = X Address = X Address = X Address = X New Address = 6 New Address = 6 New Address = 6 New Address = 6 New Address = 6 5-1=4 6-1=5 5-1=4 4-1=3 Final Address Final Address Final Address Final Address Final Address STOP Address allocation processSPI3 address allocation write operation CVT_NOK_IN CVT_NOK_OUT5 CVT_NOK_IN4 CVT_NOK_OUT4 CVT_NOK_IN3 CVT_NOK_OUT3 CVT_NOK_IN2 CVT_NOK_OUT2 CVT_NOK_IN1

ams Datasheet, Confidential:2013-Sep [1-00] AS8506 – 45 Device Interface In the address allocation process, the CVT_NOK_IN /CVT_NOK_OUT pins of AS8506 are used. After the successful SPI3 address allocation write operation, all AS8506 devices including Mast er will store the top device address (sent by Master in SPI3 address allocation write) as its address. The top device identifies itself as top most device and registers the address as its final address and at first rising edge of clock all devices force ‘High’ on its CVT_NOK_OUT pin. The concept of address allocation is: after the STOP of SPI3, at every falling edge of the clock each device will sample its CVT_NOK_IN pin. If CVT_NOK_IN pin is ‘High’ , the device will decrement the assigned address by ‘1’ and continue to force ‘High’ on its CVT_NOK_OUT pin at rising edge of clock. If CVT_NOK_IN is sampled to be ‘Low’ , then the address value at register will be stored as its final device address and it stops forcing ‘High’ on its CVT_NOK_OUT pin and makes it ‘Low’ at next rising edge of clock. In Figure 38 , top most device pins are suffixed with ‘6’ down to lower most device (Master) pins suffixed with ‘1’ in descending order. There is no device above topmost device, CVT_NOK_IN6 is always ‘Low’; therefore the address sent by Master is final address for the top device. For the fifth device the CVT_NOK_IN5 is ‘Low’ for one clock cycle, the address is decremented once. For the fourth device CVT_NOK_IN4 is ‘Low’ for two clock cycles, the address is decremented twice before registering it as final address. This procedure is continued and finally the Master device CVT_ONK_IN1 is ‘Low’ for 5 clock cycles, the address is decremented five times and finally address register will have value of “000001” as its final address. The microcontroller can identify the end of address allocation procedure in two ways:

One way is by probing CVT_NOK_OUT of Master after initiating address allocation process for a pulse.
The other method is by polling bit0 of spi3_cmd_reg register for ‘0’ (Low) and no CRC errors. During SPI3 address allocation write operation, if a CRC error occurs in the any of the Slaves, the Master indicates this failure of SPI3 transaction to all Slaves by driving TST bit ‘High’ . All Slaves should terminate the address allocation process if a ‘High’ TST bit is seen during start address allocation process SPI3 write operation. The Master will indicate the failure of address allocation process to μC by asserting a flag in the spi3_sts_reg register and sending interrupt pulse on its CVT_NOK_OUT pin.

AS8506 – 46 ams Datasheet, Confidential:2013-Sep [1-00] Device Interface Communication to Slaves There are two modes of communication between the Master and Slaves in the AS 8506 stack system:

Broadcast Communication
Communication with Individual Slave Broadcast Communication The Broadcast of communication is used to send the reference, lower, upper threshold limit co des and timer control register values for all the slaves. Reference and thresholds can be set by one of the two methods:
Through the external pins
Through the Internal DAC In case of the stacked system, reference and thresholds can be set by writing DAC values though broadcast SPI command. Write the corresponding data in the registers of timer_cntl_reg , ref_dcod_lsb_reg /ref_dcod_msb_reg , hlmt_dcod_lsb_reg /hlmt_dcod_msb_reg and llmt_dcod_lsb_reg /llmt_dcod_msb_reg and command in the Command Registers spi3_cmd_reg and spop_dadd_bcmd_reg . Example: To write DAC code of 0x0666 in the lower threshold register of all the devices, initiate a broa dcast command as given in the below sequence. Figure 39: Threshold Setting through Broadcast Command to Slaves Each broadcast write operation takes 35 clock cycles of the communication frequency. The default communication frequency is 5KHz. Broadcast slave register write is also possible other than above registers. If there any specific register of all the slaves to be written with the same content of Master then this feature is useful. Write register address in the spop_reg_add_reg . Command Register Name Address Data To set low threshold llmt_dcod_lsb_reg 0x23 0x66 llmt_dcod_msb_reg 0x24 0x06 Broadcast the cell lower limit DAC code spop_dadd_bcmd_reg 0x25 0x03 Broadcast communication command spi3_cmd_reg 0x28 0x09

AS8506 – 48 ams Datasheet, Confidential:2013-Sep [1-00] Device Interface Read operation. To perform the read operation to one of the slave device, corresponding data should be written in these registers spop_dadd_bcmd_reg , spop_reg_add_reg and spi3_cmd_reg . Data from the slave device will be written in the register rdop_data_reg . Example: To read the temperature status register of the slave device address 0x06, initiate a broadcast command as given in the below sequence. Figure 42: Read Operation to the Individual Slave Command Register Name Address Data Slave device address Slave spop_dadd_bcmd_reg 0x25 0x06 Address of the slave register spop_reg_add_reg 0x26 0x05 write command spi3_cmd_reg 0x28 0x03

AS8506 – 50 ams Datasheet, Confidential:2013-Sep [1-00] Device Interface SPI Protocol Figure 45: SPI Timing Parameters Symbol Parameter Min Typ Max Unit Note General BRSPI Bit rate 1 Mbps TSCLKH Clock high time 400 ns TSCLKL Clock low time 400 ns Write Operation Parameters tDIS Data in setup time 20 ns tDIH Data in hold time 20 ns TCSH SCSN hold time 20 ns Read Operation Parameters tDOD Data out delay 80 ns tDOHZ Data out to high impedance delay 80 ns Time for the SPI to release the SDO bus Timing Parameters for SCLK Polarity Identification tCPS Clock setup time (CLK polarity) 20 ns Setup time of SCLK with respect to SCSN falling edge. t CPHD Clock hold time (CLK polarity) 20 ns Hold time of SCLK with respect to SCSN falling edge.

ams Datasheet, Confidential:2013-Sep [1-00] AS8506 – 51 Device Interface System Timings Figure 46: System Timings Symbol Parameter Min Typ Max Unit Note Wake-up Timing Twake_pulse Wake pulse width 100 μs Tfilter_delay Time between edge on TRIG_IN pin to trig_in_fltrd signal 4μ s Tfilter WAKE_IN pin filter specification 1 4 μs Trigger Timing Tstatus_cmd Status request command pulse 500 1000 μs Tbal_cmd Cell balance command pulse 7000 μs Wait Mode Timing Twmode_tout WAIT mode timeout 2000 ms

AS8506 – 52 ams Datasheet, Confidential:2013-Sep [1-00] Device Interface Register Space Description The AS8506 register space is d ivided into control registers and test registers. All of these registers are accessed through SPI. Status Registers Figure 47: Cell Detection Status Register Address Register Name Features and Bit Description SPI SPI POR Value 0x00 cel_det_stat_reg Indicates the detected cells. RR 0000_0000 POR_V5V D0 0 → Cell 1 is not detected 1 → Cell 1 is detected D1 0 → Cell 2 is not detected 1 → Cell 2 is detected D2 0 → Cell 3 is not detected 1 → Cell 3 is detected D3 0 → Cell 4 is not detected 1→ Cell 4 is detected D4 0 → Cell 5 is not detected 1 → Cell 5 is detected D5 0 → Cell 6 is not detected 1 → Cell 6 is detected D6 0 → Cell 7 is not detected 1 → Cell 7 is detected D7 Reserved

ams Datasheet, Confidential:2013-Sep [1-00] AS8506 – 53 Device Interface Figure 48: Diagnostic Status Register Address Register Name Features and Bit Description SPI4 SPI3 POR Value 0x01 diag_sts_reg Diagnostic register. μC can read this register if pulse is detected on CVT_NOK_OUT pin, to diagnose cause of indication. RR 0000_0000 POR_V5V D0 1 → Low Threshold limit cross Indicator D1 1 → High Threshold limit cross indicator D2 1 → Over-temperature indicator D3 1 → Address allocation procedure fail D4 1 → SPI3 read operation fail D5 1 → SPI3 write operation fail D6 1 → SPI3 Broadcast operation fail D7 Reserved

AS8506 – 54 ams Datasheet, Confidential:2013-Sep [1-00] Device Interface Figure 49: Cell Lower Threshold Status Register Address Register Name Features and Bit Description SPI4 SPI3 POR Value 0x02 cel_low_thsld_stat_reg Indicates if a cell voltage crossed the lower threshold limit set by μC. RR 0000_0000 POR_V5V 0 → Cell 1 voltage is more than Low Threshold limit set 1 → Cell 1 voltage is less than Low Threshold limit set 0 → Cell 2 voltage is more than Low Threshold limit set 1 → Cell 2 voltage is less than Low Threshold limit set 0 → Cell 3 voltage is more than Low Threshold limit set 1 → Cell 3 voltage is less than Low Threshold limit set 0 → Cell 4 voltage is more than Low Threshold limit set 1 → Cell 4 voltage is less than Low Threshold limit set 0 → Cell 5 voltage is more than Low Threshold limit set 1 → Cell 5 voltage is less than Low Threshold limit set 0 → Cell 6 voltage is more than Low Threshold limit set 1 → Cell 6 voltage is less than Low Threshold limit set 0 → Cell 7 voltage is more than Low Threshold limit set 1 → Cell 7 voltage is less than Low Threshold limit set D7 Reserved

ams Datasheet, Confidential:2013-Sep [1-00] AS8506 – 55 Device Interface Figure 50: Cell Higher Threshold Status Register Address Register Name Features and Bit Description SPI4 SPI3 POR Value 0x03 cel_high_thsld_stat_reg Indicates if a cell voltage crossed the lower threshold limit set by μC. RR 0000_0000 POR_V5V 0 → Cell 1 voltage is less than High Threshold limit set 1 → Cell 1 voltage is more than High Threshold limit 0 → Cell 2 voltage is less than High Threshold limit set 1 → Cell 2 voltage is more than High Threshold limit 0 → Cell 3 voltage is less than High Threshold limit set 1 → Cell 3 voltage is more than High Threshold limit 0 → Cell 4 voltage is less than High Threshold limit set 1 → Cell 4 voltage is more than High Threshold limit 0 → Cell 5 voltage is less than High Threshold limit set 1 → Cell 5 voltage is more than High Threshold limit 0 → Cell 6 voltage is less than High Threshold limit set 1 → Cell 6 voltage is more than High Threshold limit 0 → Cell 7 voltage is less than High Threshold limit set 1 → Cell 7 voltage is more than High Threshold limit D7 Reserved

AS8506 – 56 ams Datasheet, Confidential:2013-Sep [1-00] Device Interface Figure 51: Cell Reference Status Register Address Register Name Features and Bit Description SPI4 SPI3 POR Value 0x04 cel_ref_stat_reg Indicates which cell has reached the reference value at least once. This status is cleared when new reference is selected. RR 0000_0000 POR_V5V 0 → Cell 1 voltage is less than reference voltage 1 → Cell 1 voltage is more than reference voltage 0 → Cell 2 voltage is less than reference voltage 1 → Cell 2 voltage is more than reference voltage 0 → Cell 3 voltage is less than reference voltage 1 → Cell 3 voltage is more than reference voltage 0 → Cell 4 voltage is less than reference voltage 1 → Cell 4 voltage is more than reference voltage 0 → Cell 5 voltage is less than reference voltage 1 → Cell 5 voltage is more than reference voltage 0 → Cell 6 voltage is less than reference voltage 1 → Cell 6 voltage is more than reference voltage 0 → Cell 7 voltage is less than reference voltage 1 → Cell 7 voltage is more than reference voltage D7 Reserved

ams Datasheet, Confidential:2013-Sep [1-00] AS8506 – 57 Device Interface Figure 52: Temperature Status Register Address Register Name Features and Bit Description SPI4 SPI3 POR Value 0x05 temp_stat_reg Indicates the status of temperature monitors. RR 0000_0000 POR_V5V 0 → Ambient temperature is less than warning threshold 1 → Ambient temperature is more than warning threshold 0 → Internal temperature is less than warning threshold 1 → Internal temperature is more than warning threshold 0 → Ambient temperature is less than maximum threshold 1 → Ambient temperature is more than maximum threshold 0 → Internal temperature is less than maximum threshold 1 → Internal temperature is more than maximum threshold D7:D4 Reserved

AS8506 – 58 ams Datasheet, Confidential:2013-Sep [1-00] Device Interface Figure 53: Zero Cross Status Register Address Register Name Features and Bit Description SPI4 SPI3 POR Value 0x06 zero_crs_stat_reg Indicates which cell voltage has crossed zero voltage and reached negative during sudden loading condition. This indirectly indicates the increasing status of cell internal impedance. RR 0 → Cell 1 voltage is normal 1 → Cell 1 voltage has crossed zero voltage towards negative direction 0 → Cell 2 voltage is normal 1 → Cell 2 voltage has crossed zero voltage towards negative direction 0 → Cell 3 voltage is normal 1 → Cell 3 voltage has crossed zero voltage towards negative direction 0 → Cell 4 voltage is less than reference voltage 1 → Cell 4 voltage is more than reference voltage 0 → Cell 5 voltage is normal 1 → Cell 5 voltage has crossed zero voltage towards negative direction 0 → Cell 6 voltage is normal 1 → Cell 6 voltage has crossed zero voltage towards negative direction 0 → Cell 7 voltage is normal 1 → Cell 7 voltage has crossed zero voltage towards negative direction D7 Reserved

AS8506 – 64 ams Datasheet, Confidential:2013-Sep [1-00] Device Interface Figure 72: SPI3 Status Register Address Register Name Features and Bit Description SPI4 SPI3 POR Value 0x19 spi3_sts_reg This register has status of the latest SPI3 operation. RR 0000_0000 POR_V5V 0 → No CRC error. 1 → CRC error for data from Master to Slave 0 → No CRC error. 1 → CRC error for data from Slave to Master 0 → Start address allocation process write pass 1 → Start address allocation process write fail D7:D3 Reserved

AS8506 – 66 ams Datasheet, Confidential:2013-Sep [1-00] Device Interface Figure 76: Temperature Threshold Setting Register Address Register Name Features and Bit Description SPI4 SPI3 POR Value 0x1D tflg_tshld_setg _reg Sets over-temperature warning flag and shutdown flag threshold. R/W R/W XXXX_ XXXX POR_ VSUP D3:D0 Over temperature warning flag threshold selection D7:D4 Over temperature shutdown flag threshold selection Code Value Code Value Code Value 0000 3.165 0110 3.561 1100 3.957 0001 3.231 0111 3.627 1101 4.023 0010 3.297 1000 3.693 1110 4.089 0011 3.363 1001 3.759 1111 4.155 0100 3.429 1010 3.825 - - 0101 3.495 1011 3.891 - - Code Value Code Value Code Value 0000 3.165 0110 3.561 1100 3.957 0001 3.231 0111 3.627 1101 4.023 0010 3.297 1000 3.693 1110 4.089 0011 3.363 1001 3.759 1111 4.155 0100 3.429 1010 3.825 - 0101 3.495 1011 3.891 -

ams Datasheet, Confidential:2013-Sep [1-00] AS8506 – 69 Device Interface Figure 83: Lower Limit DAC Code MSB Register Figure 84: Device Address and Broadcast Command SPI Operation Register Address Register Name Features and Bit Description SPI4 SPI3 POR Value 0x24 llmt_dcod_msb_reg Most Significant byte of 12-bit DAC code for setting low limit voltage. R/W R/W 0000_0000 POR_VSUPD3:D0 Bit11 to Bit8 of DAC code D7:D4 Reserved Address Register Name Features and Bit Description SPI4 SPI3 POR Value 0x25 spop_dadd_bcmd _reg Device address/ broadcast command register R/W - 0000_0000 POR_V5V D5:D0 If spi3_cmd_reg [D3-D1] = Address of Device to be accessed. (000000 address is broadcast address) If spi3_cmd_reg [D3-D1] = 100 Broadcast communication commands. 000000 → No operation 000001 → Timer control register write 000010 → Cell reference DAC code write

000011 Cell lower limit DAC

000100 → Cell higher limit DAC code write If spi3_cmd_reg [D3-D1] = 101 000000 → Data of register wrop_data_reg is written to address stored in spop_reg_add_reg in all devices. D7:D6 Reserved (accessible only in Master mode)

AS8506 – 72 ams Datasheet, Confidential:2013-Sep [1-00] Device Interface Figure 89: Feature Selection Register 1 Address Register Name Features and Bit Description SPI4 SPI3 POR Value 0x2A feat_sel_reg_1 Feature selection register1. R/W R/W 0000_0000 POR_VSUP D0 1 → Zero cross detection enable D2:D1 Zero cross detection filter setting 00 → 8μs 01 → 6μs 10 → 4μs 11 → 2μs D3 Reserved D4 1 → External resistor divider enable 0 → Cell reference is generated from DAC 1 → Cell reference is supplied externally on VREF_IN pin 0 → Cell Lower/Higher limit is generated from DAC 1 → Cell Lower/Higher limit is supplied externally on CELL_THL and CELL_THU pins D7 Reserved

AS8506 – 76 ams Datasheet, Confidential:2013-Sep [1-00]

Application Information

Figure 99: Application Schematic with Single Device NC_T TL1 TL2 THL TH U NTC R 1 R R2 R3 100nF 2-5uF Note: Max current on REF_T is 900uA including the Temperature sensors TSECH TSECL TRIG CLK CVT_NOK BD CS SCLK SDI SDO VSUP Microcontroller CS SCLK SDI SDO TRIG CLK CVT_NOK BD WAKE Note: Open drain on WAKE_IN pin in the µC or Transistor as shown above. RF VREF_IN Optional factory setting for Active balancing Passive balancing TSECL TSECH RLoad VREF_T VREF_T Optional fixed reference R RF TSECH TSECL 100 mA load Supply from Stack CVT_NOK_IN VCELL3 VCELL2 SDO CS SCLK SDI 34 33 3240 39 38 37 36 35 17 18 1911 12 13 14 15 16 TRIG_OUT V5V VCELL7 CLK_OUT VCELL6 VCELL5 VCELL1 C-GND TSECH TSECL MS_SL VREF_H TEMP_IN1 CELL_THL CELL_THU BD_IN BD_OUT FD_IN VSUPGND TEMP_IN2 WAKE_OUT VREF_IN

20 V5V_IN

REF_T NC VCELL4 AS8506 TRIG_IN CLK_IN CVT_NOK_OUT WAKE_IN FD_OUT

ams Datasheet, Confidential:2013-Sep [1-00] AS8506 – 77 Passive balance is to dissipate the energy from the cell with the higher cell voltage to the reference value (average of the stack e.g. max cell voltage in constant voltage charge phase or mean cell voltage as genertaed by resitor divider). Resistor value should be selected based on the cell chemistry and voltage limits. Maximum current capability of internal shuttle switch is 100mA. Intern al resistance of the shuttle switch typically is 5 Ω.. Active balance In the active balance device charge the cells which are lower than the reference voltage. This is a method of charge transfer from the stack to the cell. Flyback converter is used for this charge transfer. Active balancing mode need to be enabled by factory setting. It is not available for the default ASSP . Flyback Converter (with external Transformer) The high-efficiency, high-voltage, DC-DC Flyback converter delivers current of 100mA to the lithium ion cell when the secondary side of the Flyback tr ansformer is connected to the cell terminals. This also gives the isolation between the primary supply and the load cell. The Flyback converter is designed to charge the lithium-ion battery ce lls during the balancing mode of the IC. It consists of a PWM waveform generator with variable duty cycle and a driver. This driver can drive an external MOSFET, (or) the optocoupler, (or) an isolation device based on the requirement. During the ON -state of the PWM waveform, the primary side of the Flyback transformer conducts and stores the energy. In the other phase the stored energy in the secondary is transferred to the cell which will be connected to the secondary side of the transformer. The converter always works in discontinuous current mode (DCM). The advantages of this type of control system can be summarized as following:

High-efficiency even at light load
Intrinsically stable
Simplicity Figure 100: External Components Component Manufacturer Part Number Manufacturer Transformer WE-FLEX 74919 6111 WURTH ELECTRONICS Optocoupler ACPL-M72T-000E AVAGO TECHNOLOGIES

AS8506 – 78 ams Datasheet, Confidential:2013-Sep [1-00] Figure 101: Application with Opto-C oupler/ Isolation Device Caution: In the application it’s recommended to connect the AS8506 devices stacked first and connect the battery stack from bottom to top in sequence to avoid any possible damage of the system. While removing the battery pack its strictly recommended to remove the battery pack from the top. Removing the battery pack from bottom will damage the system. 100nF 2-5uF 100nF 2-5uF VSUP1 VSUP1 TU1 TU2 TU2 TU1 TL1 TL2TL1 TL2 V5V V5V_U VSUP1 VSUP2 Micro controller CS SCLK SDI SDO TRIG CLK CVT_NOK BD WAKE TSECL2 VSUP2 NTC NTC NTCNTC VREF_IN2 VREF_H1 VREF_IN1 VREF_H2 FD_OUT2 VSUP1 Note: If slave has to drive FD pin then SDI has to be connected local ground Note: Open drain on WAKE_IN pin in the µC or Transistor as shown above. R R CVT_NOK_IN VCELL3 VCELL2 SDO CS SCLK SDI 34 33 3240 39 38 37 36 35 17 18 1911 12 13 14 15 16 TRIG_OUT V5V VCELL7 CLK_OUT VCELL6 VCELL5 VCELL1 C-GND TSECH TSECL MS_SL VREF_H TEMP_IN1 CELL_THL CELL_THU BD_IN BD_OUT FD_IN VSUPGND TEMP_IN2 WAKE_OUT VREF_IN REF_T NC VCELL4 TRIG_IN CLK_IN CVT_NOK_OUT WAKE_IN FD_OUT CVT_NOK_IN VCELL3 VCELL2 SDO CS SCLK SDI 34 33 3240 39 38 37 36 35 17 18 1911 12 13 14 15 16 TRIG_OUT V5V VCELL7 CLK_OUT VCELL6 VCELL5 VCELL1 C-GND TSECH TSECL MS_SL VREF_H TEMP_IN1 CELL_THL CELL_THU BD_IN BD_OUT FD_IN VSUPGND TEMP_IN2 WAKE_OUT VREF_IN REF_T NC VCELL4 TRIG_IN CLK_IN CVT_NOK_OUT WAKE_IN FD_OUT NC_T NC_T AS8506 MLF 6x6 GND (Exposed Pad) AS8506 MLF 6x6 GND (Exposed Pad) Converter for active balancing

100 V device

FD_OUT2Non-inverting Optocoupler/ isolation device 100nF 2-5uF 100nF 2-5uF VSUP1 VSUP1 TU1 TU2 TU2 TU1 TL1 TL2TL1 TL2 V5V V5V_U VSUP1 VSUP2 Micro controller CS SCLK SDI SDO TRIG CLK CVT_NOK BD WAKE TSECH1 TSECL1 TSECH2 VSUP2 NTC NTC NTCNTC VREF_IN2 VREF_H1 VREF_IN1 VREF_H2 FD_OUT2 VSUP1 Note: If slave has to drive FD pin then SDI has to be connected local ground Note: Open drain on WAKE_IN pin in the µC or Transistor as shown above. R R CVT_NOK_IN VCELL3 VCELL2 SDO CS SCLK SDI 34 33 3240 39 38 37 36 35 17 18 1911 12 13 14 15 16 TRIG_OUT V5V VCELL7 CLK_OUT VCELL6 VCELL5 VCELL1 C-GND TSECH TSECL MS_SL VREF_H TEMP_IN1 CELL_THL CELL_THU BD_IN BD_OUT FD_IN VSUPGND TEMP_IN2 WAKE_OUT VREF_IN REF_T NC VCELL4 TRIG_IN CLK_IN CVT_NOK_OUT WAKE_IN FD_OUT CVT_NOK_IN VCELL3 VCELL2 SDO CS SCLK SDI 34 33 3240 39 38 37 36 35 17 18 1911 12 13 14 15 16 TRIG_OUT V5V VCELL7 CLK_OUT VCELL6 VCELL5 VCELL1 C-GND TSECH TSECL MS_SL VREF_H TEMP_IN1 CELL_THL CELL_THU BD_IN BD_OUT FD_IN VSUPGND TEMP_IN2 WAKE_OUT VREF_IN REF_T NC VCELL4 TRIG_IN CLK_IN CVT_NOK_OUT WAKE_IN FD_OUT NC_T NC_T AS8506 MLF 6x6 GND (Exposed Pad) AS8506 MLF 6x6 GND (Exposed Pad) 100 mA load Converter for active balancing FD_OUT2Non-inverting Optocoupler/ isolation device Optional Factory Setting for Active Balancing CS SCLK SDI SDO WAKE_IN BD CVT_NOK CLK TRIG

ams Datasheet, Confidential:2013-Sep [1-00] AS8506 – 79 Figure 102: Application Schematic Caution: In the application it’s recommended to connect the AS8506 devices stacked first and connect the battery stack from bottom to top in sequence to avoid any possible damage of the system. While removing the battery pack its strictly recommended to remove the battery pack from the top. Removing the battery pack from bottom will damage the system. 100nF 2-5uF 100nF 2-5uF VSUP1 NC_T VSUP1 TU1 TU2 TU2 TU1 TL1 TL2TL1 TL2 V5V V5V_U VSUP1 VSUP2 Micro Controller CS SCLK SDI SDO TRIG CLK CVT_NOK BD WAKE TSECH1 TSECL1 TSECH2 TSECL2 VSUP2 V5V_U Note: If slave has to drive FD pin then SDI has to be connected local ground NTC NTC NTCNTC VREF_IN2 VREF_H1 VREF_IN1 VREF_H2 Note: Open drain on WAKE_IN pin in the µC or Transistor as shown above. R R R R CVT_NOK_IN VCELL3 VCELL2 SDO CS SCLK SDI 34 33 3240 39 38 37 36 35 17 1811 12 13 14 15 16 TRIG_OUT V5V VCELL7 CLK_OUT VCELL6 VCELL5 VCELL1 C-GND TSECH TSECL MS_SL VREF_H TEMP_IN1 CELL_THL CELL_THU BD_IN BD_OUT FD_IN VSUPGND TEMP_IN2 WAKE_OUT VREF_IN REF_T NC VCELL4 AS8506 MLF 6x6 GND (Exposed Pad)TRIG_IN CLK_IN CVT_NOK_OUT WAKE_IN FD_OUT CVT_NOK_IN VCELL3 VCELL2 SDO CS SCLK SDI 34 33 3240 39 38 37 36 35 17 18 1911 12 13 14 15 16 TRIG_OUT V5V VCELL7 CLK_OUT VCELL6 VCELL5 VCELL1 C-GND TSECH TSECL MS_SL VREF_H TEMP_IN1 CELL_THL CELL_THU BD_IN BD_OUT FD_IN VSUPGND TEMP_IN2 WAKE_OUT VREF_IN REF_T NC VCELL4 AS8506 MLF 6x6 GND (Exposed Pad)TRIG_IN CLK_IN CVT_NOK_OUT WAKE_IN FD_OUT NC_T 100 mA load Optional Factory Setting for Active Balancing CS SCLK SDI SDO WAKE_IN BD CVT_NOK CLK TRIG

AS8506 – 80 ams Datasheet, Confidential:2013-Sep [1-00] Figure 103: Application with Opto-Coupler Device Stackable to Higher Numbers Caution:: In the application it’s recommended to connect the AS8506 devices stacked first and connect the battery stack from bottom to top in sequence to avoid any possible damage of the system. While removing the battery pack its strictly recommended to remove the battery pack from the top. Removing the battery pack from bottom will damage the system. AS8506 100KHz Optocoupler VCC Vo Vb RL Stack n Cellx of stackn AS8506 Stack1 Cellx of stack1 AS8506 Stack2 FDRIVE_OUT AS8506 Stack n+1 Stack Ground Vcc Optocoupler VCC Vo Vb RL Cellx of stack2 Stack Ground Stack Ground FDRIVE_OUT(100KHz Vcc / V Auxiliary 12V / 5V Vcc / V Auxiliary 12V / 5V

ams Datasheet, Confidential:2013-Sep [1-00] AS8506 – 81 Package Drawings & Markings The AS8506 device is available in a 40-pin MLF (6x6) package. Figure 104: Package Drawings & Markings Symbol Min Nom Max e0 . 5 0 B S C D1 5.75 BSC E1 5.75 BSC D2 4.40 4.50 4.60 E2 4.40 4.50 4.60 aaa - 0.15 - bbb - 0.10 - ccc - 0.10 - ddd - 0.05 - eee - 0.08 - fff - 0.10 - N4 0 AS8506 YYWWIZZ (A) Note: ‘A’ is for active balancing and default is Passive Balancing. Symbol Min Nom Max A 0.80 0.90 1.00 A1 0 0.02 0.05 A2 - 0.65 1.00 A3 0.20 REF L 0.30 0.40 0.50 L1 0.05 0.15 0.25 L2 0.05 0.10 0.15 Θ 0º - 14º b 0.20 0.25 0.30 b1 0.10 0.15 0.20 D6 . 0 0 B S C E6 . 0 0 B S C

AS8506 – 82 ams Datasheet, Confidential:2013-Sep [1-00] Package Drawings & Markings Note(s) and/or Footnote(s): 1. Dimensions and toleranceing conform to ASME Y14.5M. - 1994. 2. All dimensions are in mill imeters (angles in degrees). 3. Bilateral coplanarity zone applies to th e exposed pad as well as the terminal. 4. Radius on terminal is optional. 5. N is the number of terminals. Figure 105: AS8506 Packaging Code YYWWXZZ YY WW I ZZ Last two digits of the year Manufacturing we ek Plant identifier Assembly traceability code

ams Datasheet, Confidential:2013-Sep [1-00] AS8506 – 83 Package Drawings & Markings The AS8506C device is available in a 40-pin MLF (6x6) package. Figure 106: Symbol Min Nom Max e0 . 5 0 B S C D1 5.75 BSC E1 5.75 BSC D2 4.40 4.50 4.60 E2 4.40 4.50 4.60 aaa - 0.15 - bbb - 0.10 - ccc - 0.10 - ddd - 0.05 - eee - 0.08 - fff - 0.10 - N4 0 Note: ‘A’ is for active balancing and default is Passive Balancing. Symbol Min Nom Max A 0.80 0.90 1.00 A1 0 0.02 0.05 A2 - 0.65 1.00 A3 0.20 REF L 0.30 0.40 0.50 L1 0.05 0.15 0.25 L2 0.05 0.10 0.15 Θ 0º - 14º b 0.20 0.25 0.30 b1 0.10 0.15 0.20 D6 . 0 0 B S C E6 . 0 0 B S C AS8506C YYWWIZZ (A)

AS8506 – 84 ams Datasheet, Confidential:2013-Sep [1-00] Package Drawings & Markings Note(s) and/or Footnote(s): 1. Dimensions and toleranceing conform to ASME Y14.5M. - 1994. 2. All dimensions are in mill imeters (angles in degrees). 3. Bilateral coplanarity zone applies to th e exposed pad as well as the terminal. 4. Radius on terminal is optional. 5. N is the number of terminals. Figure 107: AS8506C Packaging Code YYWWXZZ YY WW I ZZ Last two digits of the year Manufacturing we ek Plant identifier Assembly traceability code

ams Datasheet, Confidential:2013-Sep [1-00] AS8506 – 85 RoHS Compliant & ams Green Statement RoHS: The term RoHS compliant means that ams products fully comply with current RoHS directives. Our semiconductor products do not contain any chemicals for all 6 substance categories, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, RoHS compliant products are suitable for use in specif ied lead-free processes. ams Green (RoHS compliant and no Sb/Br): ams Green defines that in addition to RoHS compliance, our products are free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material). Important Information: The information provided in this statement represents ams knowledge and belief as of the date that it is provided. ams bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are unde rway to better integrate information from third parties. ams has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ams and ams suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. RoHS Compliant & ams Green Statement

AS8506 – 86 ams Datasheet, Confidential:2013-Sep [1-00] Ordering & Contact Information The devices are available as the standard products shown in Ordering Information. Figure 108:

Ordering Information

Note(s) and/or Footnote(s): 1. Non-automotive Version without AECQ 100 Qualification. Buy our products or get free samples online at: www.ams.com/ICdirect Technical Support is available at: www.ams.com/Technical-Support For further information and requests, e-mail us at: ams_sales@ams.com For sales offices, distributors and representatives, please visit: www.ams.com/contact Headquarters ams AG Tobelbaderstrasse 30

8141 Unterpremstaetten

Austria, Europe Tel: +43 (0) 3136 500 0 Website: www.ams.com Ordering Code Description Delivery Form Package Reel Size AS8506-BQFP Monitor and balancer IC Tape and reel 40-pin MLF (6x6) 4000 AS8506-BQFM Monitor and Balancer IC Tape and Reel 40-Pin MLF (6x6) 1000 AS8506C-BQFP (1) Monitor and Balancer IC Tape and Reel 40-Pin MLF (6x6) 4000 AS8506C-BQFM (1) Monitor and Balancer IC Tape and Reel 40-Pin MLF (6x6) 1000 Ordering & Contact Information

ams Datasheet, Confidential:2013-Sep [1-00] AS8506 – 87 Copyrights & Disclaimer Copyright ams AG, Tobelbader Strasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. Devices sold by ams AG are covered by the warranty and patent indemnification provisions appear ing in its Term of Sale. ams AG makes no warranty, express, statutory, implied, or by description regarding the inform ation set forth herein. ams AG reserves the right to change specifications and prices at any time and without notice. Theref ore, prior to designing this product into a system, it is necessary to check with ams AG for current information. This product is intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications , such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by ams AG for each application. This Product is provided by ams “AS IS” and any express or implied warranties, including, but not limited to the implied warranties of merc hantability and fitness for a particular purpose are disclaimed. ams AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any th ird party shall arise or flow out of ams AG rendering of technical or other services. Copyrights & Disclaimer

AS8506

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Document overview

Technical content

Applications

2 TSECL Flyback converter transformer secondary low side

3 VCELL7 Battery cell 7 high level pin

4 VCELL6 Battery cell 6 high level pin

5 VCELL5 Battery cell 5 high level pin

6 VCELL4 Battery cell 4 high level pin

7 VCELL3 Battery cell 3 high level pin

8 VCELL2 Battery cell 2 high level pin

9 VCELL1 Battery cell 1 high level pin

10 C-GND Power supply

11 NC Not connected

12 VREF_IN Analog input /

13 GND Power supply

14 TRIG_IN

15 CLK_IN

16 CVT_NOK_OUT

17 BD_OUT

18 FD_OUT Flyback converter gate/opto coupler drive (pad is

19 WAKE_IN Digital input

20 NC_T Analog input /

21 SDO Digital output SPI data out

22 SDI

23 SCLK SPI clock

24 CS Digital input

25 CELL_THU

26 CELL_THL Cell voltage lower threshold

27 TEMP_IN2

28 TEMP_IN1

29 REF_T Supply to temperature sensor (Reference voltage to

30 V5V Power supply

32 WAKE_OUT Digital output

33 FD_IN Digital input

34 BD_IN

35 CVT_NOK_IN Indicates cell voltage or temperature status of above

36 CLK_OUT

37 TRIG_OUT

38 VSUP Power supply

39 MS_SL Digital input

40 VREF_H Analog input /

Electrical Characteristics

7 Time slot

000011 Cell lower limit DAC

Application Information

20 V5V_IN

100 V device

Ordering Information

8141 Unterpremstaetten

1 General Description

2 Key Benefits & Features

2 Applications

3 Block Diagram

4 Pin Assignment

10 Typical Operating Characteristics

11 Device Level Specifications

12 Low Dropout Regulator (5V Output LDO)

13 High-precision Bandgap Reference

13 Digital to Analog Converter

14 Analog to Digital Converter

14 Pre-Regulator

15 PWM Driver

16 PWM Oscillator

16 Oscillator for Digital Circuit

17 External Temper ature Thresholds

18 Ron of the Shuttle Switch es (Internal Switch for

18 Over-Temperat ure Measurement

19 Weak Cell Detection (Voltage Comparator)

19 Power on Voltage Detection

22 Detailed Description

22 Voltage Regulator (LDO_5V)

22 High Precision Bandgap (HPBG)

22 External Temperature Monitor and Measurement

23 Internal Temperature Monitor

23 PWM Generator

23 RC Oscillator

23 DAC for the Reference Generation