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[v1-12] 2018-Feb-26 Document Feedback AS7000 Biosensor The AS7000 device provides a flexible analog front end for light sensing applications. The phot odiode input ci rcuit can be configured in different ways to guarantee best tradeoff between speed and sensitivity for a large number of different sensing applications. Ordering Information and Content Guide appear at end of datasheet. Key Benefits and Features The benefits and features of AS7000, Biosensor are listed below: Figure 1: Added Value of Using AS7000
Applications
The device is suitable for optical sensor platform. Benefits Features
- Allows smallest application size e.g. narrow HRM measurement band
- Single device integrated optical solution
- Integrated 32bit Cortex-M0 processor
- Good HRM measurement quality • Low noise analog optical front end
- Additional information for end user • Analog electrical front end (e.g. for NTC or GSR)
- Long operating time • Hardware sequencer to offload processor
- Adjustable LED driver with current control
- Works reliably with ambient light • Synchronous detector General Description
Document Feedback [v1-12] 2018-Feb-26 AS7000 − General Description Block Diagram The functional blocks of this device are shown below: Figure 2: AS7000-AA GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 GPIO8 GPIO7 GPIO6 GPIO5 Electrical Frontend Optical Frontend 14 bit ADCLDO Biasing Optical barrier AGND SIGREF CSI GREF 2.2µF VDD V_LDO GNDCLDO 2.2µF VDD 2.6V-3.6V VD1 VD2 LED Supply VD4 VD3 ON=0, off by sotftware CVDD 2.2µF LED Supply Cortex M0 4kByte RAM 32kByte EEPROM UART, SPI, I2C if not used connect to GND
[v1-12] 2018-Feb-26 Document Feedback AS7000 − Pin Assignments Figure 3: Optical Module Pinout (Top View) – AS7000-AA Figure 4: Pin Description Optical Module Pinout: This drawing is not to scale Pin Number Pin Name Description
1 VD2 Supply voltage for LED D2 – connect unused current sinks to GND
2 VD4 Supply voltage for LED D4 – connect unused current sinks to GND
Analog reference output. Connect 2.2μF capacitor to GND (e.g. 0402 sized capacitor GRM153R60J225ME95 from Murata – needs to have >1μF specified for 1.0V voltage bias); do not load externally The typical operating voltage on this pin is 0.6V (sigref_en=1) 4 AGND Analog ground. Connect to low noise GND 5V _ L D O 1.9V output voltage. Connect 2.2μF capacitor to GND (e.g. 0402 sized capacitor GRM153R60J225ME95 from Murata – needs to have >1μF with 1.0V voltage bias); do not load externally
6 GPIO6 General purpose input/output
7 GPIO7 General purpose input/output
8 GPIO8 General purpose input/output
9 VDD Supply voltage. 10 GND Power supply ground. All voltages are referenced to GND. Pin Assignments
1 VD2
2 VD4
3 SIGREF
4 AGND
5 V_LDO
6 GPIO6
7 GPIO7
8 GPIO8
9 VDDGND 10
Document Feedback [v1-12] 2018-Feb-26 AS7000 − Pin Assignments
11 GPIO0 General purpose input/output
12 GPIO1 General purpose input/output
13 GPIO2 General purpose input/output
14 GPIO3 General purpose input/output
15 GPIO4 General purpose input/output
16 GPIO5 General purpose input/output
17 VD1 Supply voltage for LED D1 – connect unused current sinks to GND
18 VD3 Supply voltage for LED D3 – connect unused current sinks to GND
Pin Number Pin Name Description
[v1-12] 2018-Feb-26 Document Feedback AS7000 − Absolute Maximum Ratings Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in Electrical Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Figure 5: Absolute Maximum Ratings (1) Symbol Parameter Min Max Units Comments Electrical Parameters VDD Supply voltage to ground 3.63V V V_LDO Supply voltage to ground 1.98V max. VDD+0.3V V VIN Input pin voltage to ground, all pins except VD1/VD2/VD3/VD4 -0.3 VDD+0.3V max. 3.8V V V IN-VD1-4 Input pin voltage to ground, pins VD1/VD2/VD3/VD4 -0.3 5.5 V V INLDO Input pin voltage to ground, pin SIGREF -0.3 V_LDO+0.3V max. 1.98V V ISCR Input current (latch-up immunity) -100 100 mA JEDEC JESD78 Electrostatic Discharge ESDHBM All pins except VD1/VD2/VD3 and VD4 ±1.0 kV Electrostatic discharge HBM: JEDEC JESD22-A114F Pins VD1/VD2/VD3 and VD4 ±350 V Absolute Maximum Ratings
Document Feedback [v1-12] 2018-Feb-26 AS7000 − Absolute Maximum Ratings Note(s): 1. All optical customer designs shall be reviewed by ams before production. Temperature Ranges and Storage Conditions TAMB Operating temperature -30 70 °C TSTRG Storage temperature range -40 85 °C IPC/JEDEC J-STD-020 The reflow peak soldering temperature (body temperature) is specified according to IPC/JEDEC J-STD-020 “Moisture/Reflow Sensitivity Classification for Non-hermetic Solid State Surface Mount Devices. ” RH NC Relative humidity non-condensing 58 5 % MSL Moisture sensitivity level 3 Maximum floor life time of 168h Symbol Parameter Min Max Units Comments
[v1-12] 2018-Feb-26 Document Feedback AS7000 − Electrical Characteristics VDD=2.6 to 3.6V, typ. values are at T AMB=25°C (unless otherwise specified). All limits are guaranteed. The parameters with min and max values are guaranteed with production tests or SQC (Statistical Quality Control) methods. Figure 6: Operating Conditions Symbol Parameter Conditions Min Typ Max Unit VDD Supply voltage 2.6 3.3 3.6 V VLED LED Supply voltage VD1, VD2, VD3, VD4 if a LED is used 5.0 V VLDO LDO voltage, generated by AS7000 Pin V_LDO 1.9 V TAMB Operating free-air temperature −30 70 °C IDD Supply current CPU + EEPROM running at 16MHz; from 1.8V supply; all periphery blocks off 1.4 mA CPU in sleep mode, 16MHz oscillator running; all periphery blocks off 360 μA ADC 14bit; only during conversion 2m A Photodiode amplifier and Optical front end 430 μA Electrical front end 180 μA LED current sink per channel 25mA range 210 μA LED current sink per channel 50mA and 100mA range 340 μA Deep sleep mode (1), (2) 512Hz oscillator running, LDO operating, processor powered 25 μA Power down (3) GPIO8=VDD. 0.8 μA VOL GPIO0-8 output low voltage With 3 mA load With 6 mA load 0.4 0.8 V VOH GPIO0-8 output high voltage With 6 mA load, VDD>3.0V 2.4 VDD V
Electrical Characteristics
Document Feedback [v1-12] 2018-Feb-26 AS7000 − Electrical Characteristics VIH GPIO0-8 input high voltage 1.25 V VIL GPIO0-8 input low voltage 0.54 V RPULLUP Pullup Resistor to VDD On GPIO0…8 if bit gpioX_ pd=1 where X=0…8 75 kΩ RPULLDOWN Pulldown Resistor to GND On GPIO0…8 if bit gpioX_ pd=2 where X=0…8 75 kΩ ILEAK1 GPIO0-8 −1 1 μA ILEAK2 VD1-4 pins At 5.0 V, TAMB=25ºC 2μ A E_f16M Tolerance of internal 16MHz oscillator TAMB>0ºC -2 +2 % E_f3k2 Tolerance of internal 512Hz oscillator -35 +25 % EEPROM nCYCLES Number of write cycles 100 cycles tRETENTION Data retention time At maximum 65ºC 10 years I²C Mode Timings (SCL / SDA Programmable to GPIO Pins – See I²C Mode ) fSCLK SCL clock frequency 0 400 tBUF Bus free time between a STOP and START condition 1.3 kHz tHD:STA Hold time (repeated) START condition(3) 0.6 μs tLOW LOW period of SCL clock 1.3 μs tHIGH HIGH period of SCL clock 0.6 μs tSU:STA Setup time for a repeated START condition 0.6 μs tHD:DAT Data hold time (4) 00 . 9 μ s tSU:DAT Data Setup Time (5) 100 ns tR Rise time of both SDA and SCL signals 20 300 ns tF Fall time of both SDA and SCL signals 20 300 ns tSU:STO Setup time for STOP condition 0.6 μs CB Capacitive load for each bus Line CB — total capacitance of one bus line in pF 400 pF Symbol Parameter Conditions Min Typ Max Unit
[v1-12] 2018-Feb-26 Document Feedback AS7000 − Electrical Characteristics Note(s): 1. Deep sleep mode. Use ams SDK (software development kit) to enter deep sleep, wakeup with low on GPIO8 pin (if gpio8_wakeup_ en=1) or high on GPIO7 (if gpio7_wakeup _en=1) or 512Hz oscillator sleep_timer. 2. GPIO0-8 configured to draw minimum current (software dependent). 3. Power down mode. Entered by setting enter_powerdown=1; No oscillator running. Wakeup with low on GPIO8 pin (always) or high on GPIO7 (if gpio7_wakeup_en=1). 4. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V IHMIN of the SCL signal) to bridge the undefined region of the falling edge of SCL. 5. A fast-mode device can be used in a standard-mode system, but the requirement t SU:DAT = to 250ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW p eriod of the SCL signal, it must output the next data bit to the SDA line t R max + tSU:DAT = 1000 + 250 = 1250ns before the SCL line is released. Figure 7: I²C Mode Timing Diagram I²C Mode Timing Diagram: This figure shows the different timings required for I²C communication. Note(s): 1. SCL / SDA Programmable to GPIO Pins – See I²C Mode . CI/O I/O capacitance (SDA, SCL) 10 pF Symbol Parameter Conditions Min Typ Max Unit SCLK SDA tBUF tHD:STA tSU:STA REPEATED START tSU:STO tF tSU:DATtHIGHtHD:DAT tR tLOW tHD:STA STARTSTOP
Document Feedback [v1-12] 2018-Feb-26 AS7000 − Detailed Description Optical Analog Front End Figure 8: Optical Analog Front End – AS7000-AA Configuration Note(s): 1. Dual Green LED Configuration is shown. The number of LEDs inside the module depends on the application – Figure 8 shows 2 LEDs. If a LED is not populated, the current sink is connected directly to the pin (VD3 and VD4 in above figure). Detailed Description GPIO7 GPIO6 pd1 pd2 pd3 pd4 pdi_1 pdi_0 pd_ampcap pd_ampres pdoffx pd_amp_en ADC adc_sel=1 adc_sel=0 gain_byp sd_byp Synchronous Demodulator TIA Gain Stage hp_byp High Pass Filter sd_bwaa_freq 200Hz sd_en hp_freq hp_en gain_g gain_en Sequencer VD1VD2 -1/0/+1 sample reset VD4 VD3
[v1-12] 2018-Feb-26 Document Feedback AS7000 − Detailed Description LEDs AS7000-AA Dual Green LED Configuration Two green LEDs are used (pins VD1/VD2). The other two current sinks are available on pins VD3 and VD4. LED Characteristics Figure 9: LED Characteristics at T AMB =25°C Note(s): 1. The maximum allowed LED current (DC and peak) is specif ied for 25°C. Lower values apply for higher temperatures. 2. Add 280mV and use LED current range ≤100mA for de signing the VD1/VD2 LED supply (DC-DC converter). Symbol Parameter Conditions Min Typ Max Unit Green LED (AS7000-AA) ILED_GREEN Allowed operating LED current range (1) Continuous 50 mA 1/10 duty cycle @ 1 kHz 100 mA VFLED_GREEN Forward voltage (2) ILED=20mA 2.9 3.2 V VFLED+DRIVER _GREEN Voltage on VD1/VD2 where operation of the LED and current source is guaranteed I LED= 10mA 3.6 V ILED= 50mA 4.5 λp_GREEN Dominant wavelength 527 nm Δλ½_GREEN Spectral halfwidth 35 nm
[v1-12] 2018-Feb-26 Document Feedback AS7000 − Detailed Description LED Configuration Registers For ledX_supply_low registers see register AFE_PD_CFG. Figure 12: AFE_LED_CFG The LED_CFG register is used to configure the operating mode of the LED outputs. 0x00: AFE_LED_CFG Field Name Rst Type Description 18 sigref_en 0 RW Signal reference: Is required for all analog blocks 0...Disable signal reference 1...Enable signal reference 11 led4_en 0 RW 0...Disables LED4 output source. 1...Enables LED4 output source. 10 led3_en 0 RW 0...Disables LED3 output source. 1...Enables LED3 output source. 9 led2_en 0 RW 0...Disables LED2 output source. 1...Enables LED2 output source. 8 led1_en 0 RW 0...Disables LED1 output source. 1...Enables LED1 output source. 7:6 imax4 1 RW Defines IMAX of LED4. Setting IMAX 02 5 m A 15 0 m A 21 0 0 m A
3 Do not use
5:4 imax3 1 RW Defines IMAX of LED3. same encoding as imax4 3:2 imax2 1 RW Defines IMAX of LED2. same encoding as imax4 1:0 imax1 1 RW Defines IMAX of LED1. same encoding as imax4
Document Feedback [v1-12] 2018-Feb-26 AS7000 − Detailed Description AFE_LED_CURR Register (Addr: 0x04) The AFE_LED_CURR defines the LED output current. Figure 13: AFE_LED_CURR Register Addr: 0x04 AFE_LED_CURR Bit Bit Name Default Access Description 31:24 curr4 0x00 R/W LED4 output current – do not use code=0 (will generate no output current) ILED4 = (curr4 + 1) * imax4 / 256 23:16 curr3 0x00 R/W LED3 output current – do not use code=0 (will generate no output current) ILED3 = (curr3 + 1) * imax3 / 256 15:8 curr2 0x00 R/W LED2 output current – do not use code=0 (will generate no output current) ILED2 = (curr2 + 1) * imax2 / 256 7:0 curr1 0x00 R/W LED1 output current – do not use code=0 (will generate no output current) ILED1 = (curr1 + 1) * imax1 / 256
[v1-12] 2018-Feb-26 Document Feedback AS7000 − Detailed Description Figure 14: AFE_MAN_SEQ_CFG 0x20: AFE_MAN_SEQ_CFG Field Name Rst Type Description 26 man_mode 0 RW 0...Enables Sequencer 1...Enables Manual control of optical front end 23 man_sw_itg 0 RW If man_mode=1 0...All integrator capacitors are shorted. Integrator is reset 1...Integrator capacitors are charging up. Integrator is running 22 man_sw_led4 0 RW If man_mode=1 0...LED output D4 disabled. (High impedance) 1...LED output D4 enabled 21 man_sw_led3 0 RW If man_mode=1 0...LED output D3 disabled. (High impedance) 1...LED output D3 enabled 20 man_sw_led2 0 RW If man_mode=1 0...LED output D2 disabled. (High impedance) 1...LED output D2 enabled 19 man_sw_led1 0 RW If man_mode=1 0...LED output D1 disabled. (High impedance) 1...LED output D1 enabled 18:17 diode_ctrl 0 RW Connection of Photodiodes PD1, PD2, PD3, PD4 to the photodiode amplifier. 0...PD1-PD4 are connected 1...PD1 synchronous to LED1, PD2 sync/to LED2, PD3 sync/to LED3, PD4 sync/to LED4 2...PD1 synchronous to LED1, PD2 sync/to LED1, PD3 sync/to LED2, PD4 sync/to LED2 3...PD1 synchronous to LED1, PD2 sync/to LED1, PD3 sync/to LED4, PD4 sync/to LED4 Note that AFE_PD_CFG.pdX takes precedence - to turn OFF one photo diode, the respective bit (pd1…pd4) has to be de-asserted in the AFE_PD_CFG register. AFE_PD_ CFG.pdX diode_ ctrl Photo Diode1 Photo Diode2 Photo Diode3 Photo Diode4 0 xx OFF OFF OFF OFF 10 0 O N O N O N O N 1 01 LED1 LED2 LED3 LED4 1 10 LED1 LED1 LED2 LED2 1 11 LED1 LED1 LED4 LED4
Document Feedback [v1-12] 2018-Feb-26 AS7000 − Detailed Description 13 dma_disable 0 RW ADC DMA disable 1...ADC result has to be read from adc_data 0...ADC result(s) is/are written to memory 12:10 led4_mode 0 RW LED4 mode Setting Behavior
0 Always OFF
1 Always ON when sequencer is active
2C o n t r o l l e d b y s e q u e n c e r
3 Controlled by sequencer, only ON in even
iterations: 0, 2, 4 etc.
4 Controlled by sequencer, only ON in odd
iterations: 1, 3, 5 etc.
5 Controlled by sequencer, only ON in every
fourth iteration, starting at 3: 3, 7, 11 etc. 9:7 led3_mode 0 RW LED3 mode Setting Behavior 2C o n t r o l l e d b y s e q u e n c e r iterations: 0, 2, 4 etc. iterations: 1, 3, 5 etc. fourth iteration, starting at 2: 2, 6, 10 etc. 0x20: AFE_MAN_SEQ_CFG Field Name Rst Type Description
[v1-12] 2018-Feb-26 Document Feedback AS7000 − Detailed Description 6:4 led2_mode 0 RW LED2 mode Setting Behavior 2C o n t r o l l e d b y s e q u e n c e r iterations: 0, 2, 4 etc. iterations: 1, 3, 5 etc. fourth iteration, starting at 1: 1, 5, 9 etc. 3:1 led1_mode 0 RW LED1 mode Setting Behavior 2C o n t r o l l e d b y s e q u e n c e r iterations: 0, 2, 4 etc. iterations: 1, 3, 5 etc. fourth iteration, starting at 0: 0, 4, 8 etc. 0s e q _ e n 0 R W 0...Disables sequencer 1...Enables sequencer 0x20: AFE_MAN_SEQ_CFG Field Name Rst Type Description
Document Feedback [v1-12] 2018-Feb-26 AS7000 − Detailed Description Photodiode Selection In order to have flexible arra ngement of the use photodiodes, PD1-PD4 can be individually connected to the photodiode amplifier input. The optional offset current allows cancellation of constant light sources like sunlight. In case of an external photodiode or any other sensor with (low) current output, the pins GPIO6 and GPIO7 can be used as input. Additionally the sequencer can control the diodes – see diode_ ctrl described in register AFE_MAN_SEQ_CFG . Figure 15: Photodiode Selection GPIO7 GPIO6 pd1 pd2 pd3 pd4 pdi_1 pdi_0 pdoffx to TIA (Trans-Impedance -Amplifier)
[v1-12] 2018-Feb-26 Document Feedback AS7000 − Detailed Description AFE_PD_CFG Register (Addr: 0x08) The AFE_PD_CFG register is used to configure the input to the photo amplifier. Figure 16: AFE_PD_CFG Register Note(s): 1. SC_WS: Self clear, write sets: These registers are reset by the hardware. Set to ‘1’ before using them. Addr: 0x08 AFE_PD_CFG Bit Bit Name Default Access Description 25 sd_hld 0 R/W SD hold 0 …Output of synchronous demodulator is forced to SIGREF if not set to +1 or -1 1… Output of synchronous demodulator is tristated if not set to +1 or -1 23 led4_ supply_low 0 SC_WS (1) If this bit is cleared, LED4 current sink voltage was below its compliance voltage 22 led3_ supply_low 0 SC_WS (1) If this bit is cleared, LED3 current sink voltage was below its compliance voltage. 21 led2_ supply_low 0 SC_WS (1) If this bit is cleared, LED2 current sink voltage was below its compliance voltage. 20 led1_ supply_low 0 SC_WS (1) If this bit is cleared, LED1 current sink voltage was below its compliance voltage. 15:8 pdoffx 0x00 R/W Input offset current Ioffset = pdoffx*10nA 00000000…Offset source is turned OFF 5p d 4 0 R / W 0 …Photodiode PD4 is disconnected from photo amplifier 1 …Photodiode PD4 is connected to photo amplifier (as defined in diode_ctrl) 4p d 3 0 R / W 0 …Photodiode PD3 is disconnected from photo amplifier 1 …Photodiode PD3 is connected to photo amplifier (as defined in diode_ctrl) 3p d 2 0 R / W 0 …Photodiode PD2 is disconnected from photo amplifier 1 …Photodiode PD2 is connected to photo amplifier (as defined in diode_ctrl) 2p d 1 0 R / W 0 …Photodiode PD1 is disconnected from photo amplifier 1 …Photodiode PD1 is connected to photo amplifier (as defined in diode_ctrl) 1p d i _ 1 0 R / W 0 …GPIO7-input is disconnected from photo amplifier 1 …GPIO7-input is connected to photo amplifier 0p d i _ 0 0 R / W 0 …GPIO6-input is disconnected from photo amplifier 1 …GPIO6-input is connected to photo amplifier
[v1-12] 2018-Feb-26 Document Feedback AS7000 − Detailed Description Figure 19: Operating Characteristics of Each Photodiode, VDD=3V, T AMB=25°C (unless otherwise noted) Note(s): 1. For monochromatic light of 555nm, one lux corresponds to 0.146 μW/cm2. That is, one obtains 6.5 lux per μW/cm2 Symbol Parameter Conditions Min Typ Max Unit Re Irradiance responsivity λP=525nm, 4 photodiodes used pd1/2/3/4=1, gain_g=4x, gain_en=1, pd_ampres=7MΩ dual green LED configuration filters mV/ (μW /cm Id Dark current Ee=0 01 n A Ios Extrapolated offset current −1 1 nA
Document Feedback [v1-12] 2018-Feb-26 AS7000 − Detailed Description Photodiode Trans-Impedance Amplifier (TIA) The photodiode amplifier can be configured in three different modes:
- Photocurrent to frequency converter
- Photocurrent to voltage converter
- Photocurrent integrator Figure 20: Trans-Impedance-Amplifier (TIA) The integration time t INT is defined either by the sequencer (man_mode=0) of manually through the bit sw_itg if man_mode=1. pd_ampcap pd_ampres pd_amp_en Sequencer from photodiodes to synchronous demodulator man_mode man_sw_itg
[v1-12] 2018-Feb-26 Document Feedback AS7000 − Detailed Description Figure 21: Settings for the Programming of the TIA Note(s): 1. pd1234 … number of active photodiodes (for ex ample, pd1=1, pd2=0, pd3=1, pd4=0 -> pd1234=2) pd_ampres pd12341 pd_ampcap pd_ampcomp pd_ampvo Gain 1 1 … 4 1 311 5 1 V / μ A 2 1…4 7 1 15 2V/μA 3 1…4 5 1 15 3V/μA 1…2 2 01 5 5 V / μ A 3…4 3 1…2 2 01 5 7 V / μ A 3…4 3 01 5 1 0 V / μ A 2…4 2 1…2 1 01 5 1 5 V / μ A 3…4 2 Low Bandwidth Mode 5 1 … 4 3 131 5 7 V / μ A Integrating Mode (pd_ampres=0) 0 1 … 4 1 031 5 1 V / p Q 0 1 … 4 2 031 5 1 / 2 V / p Q 0 1 … 4 3 031 5 1 / 3 V / p Q
Document Feedback [v1-12] 2018-Feb-26 AS7000 − Detailed Description AFE_PD_AMPCFG Register (Addr: 0x0c) The AFE_PD_AMPCFG register is used to configure the operating mode of the photo-amplifier Figure 22: AFE_PD_AMPCFG Register For registers man_mode and man_sw_itg see AFE_MAN_SEQ_ CFG . Addr: 0x0c AFE_PD_AMPCFG Bit Bit Name Default Access Description 31 pd_amp_en 0 R/W 0…Activates power down mode of photo-amplifier 1…Enables photo-amplifier 13:10 pd_amp_vo 15 R/W Opamp offset. Use ams device drivers – these automatically configure this register. 9:8 pd_ ampcomp 3R / W Opamp compensation. Use ams device drivers – these automatically configure this register. 7:5 pd_ampres 0x0 R/W Feedback resistor 000…No resistor in feedback of amplifier 001…1MΩ 010…2MΩ 011…3MΩ 100…5MΩ 101…7MΩ 110…10MΩ 111…15MΩ 4:0 pd_ampcap 0x0 R/W Feedback capacitor – automatically set by ams device drivers for modes using pd_ampres not 000b. Capacitor = pd_ampcap*0.1pF
[v1-12] 2018-Feb-26 Document Feedback AS7000 − Detailed Description Voltage Mode of the Photodiode Amplifier The output voltage of the phot odiode amplifier is depending on the feedback component: Feedback resistor: Feedback capacitor: Note(s): The integration time t INT is defined either by the sequencer (man_mode=0) of manu ally through the bit sw_itg if man_mode=1. For the synchronous demodulator only use the resistive feedback. Figure 23: Difference Between Resistive and Capacitive Feedback (EQ1) Uout Iphoto Rfb⋅= (EQ2) Uout Iphoto tINT Cfb
Document Feedback [v1-12] 2018-Feb-26 AS7000 − Detailed Description Optical Front End Operating Modes Once the photodiode amplifier is configured the measurement can be done in two different wa ys. Either the LED-outputs, the photodiode amplifier and the AD C are controlled manually by means of register bits, or they are controlled by a built in sequencer. Manual Operation of The Optical Frontend: The optical front end can be manually controlled via the AFE_ MAN_SEQ_CFG register using man_mode=1. Figure 24: Manual Operation of the Optical Frontend and LED Note(s): 1. Applies only if man_mode=1. For manual operation of the LEDs and its current sinks see LED-Driver . pd_ampcap pd_ampres pd_amp_en man_sw_itgGPIO7 GPIO6 pd1 pd2 pd3 pd4 pdi_1 pdi_0 pdoffx ADC adc_sel=0 Start conversion: seq_en=1 End of conversion: seq_en returns to 0
[v1-12] 2018-Feb-26 Document Feedback AS7000 − Detailed Description Sequencer In order to synchronize the LED-currents, the integration time and the ADC-sampling time, a built in sampling Sequencers can be used. The sequencer generate s the 16 bit-timings based on a 1μs clock. The results of the an alog to digital conversion are automatically stored in a pipeline buffer or in register adc_data. The timings can be programmed with following registers (apply for man_mode=0): Figure 25: Sequencer Control Registers Overview Note(s): 1. The lowest data value of all registers except seq_count, seq_div, seq_adc_inc, seq_adc_in c_fract and seq_adc_fract is 1. Register Description seq_div Divider of the 1μs input clock seq_count Number of measurements in one sequence seq_start Writing 1 starts the se quencer, 0 stops the sequencer seq_period Time of one measurement cycle seq_led_start Start time of the LED drivers within one cycle seq_led_stop Stop time of the LED drivers within one cycle seq_itg_start Start time of the integrator seq_itg_stop Stop time of the integrator seq_sdp_start Start time of the synchro nous demodulator’s positive multiplication seq_sdp_stop Stop time of the synchronou s demodulator’s positive multiplication seq_sdm1_start Start time of the synchronou s demodulator’s negative multiplication 1 seq_sdm1_stop Stop time of the synchronous demodulator’s negative multiplication 1 seq_sdm2_start Start time of the synchronou s demodulator’s negative multiplication 2 seq_sdm2_stop Stop time of the synchronous demodulator’s negative multiplication 2 seq_adc, seq_adc_fract Sampling position of the ADC in single steps / in 1/16th steps seq_adc_inc, seq_adc_inc_fract Increment of the sampling position of the ADC after each measurement in single steps / in 1/16th steps sd_subs Subsampling ratio between sequencer frequency and ADC sampling frequency – use for adjusting the ADC sampling frequency at a lower speed than the sequencer cycle frequency
Document Feedback [v1-12] 2018-Feb-26 AS7000 − Detailed Description Figure 26: Block Diagram of Sequencer Sequencer Synchronous Demodulator control GPIO7 GPIO6 pd1 pd2 pd3 pd4 pdi_1 pdi_0 pd_ampcap pd_ampres pdoffx pd_amp_en ADC adc_sel=1 adc_sel=0 gain_byp sd_byp Synchronous Demodulator TIA Gain Stage hp_byp High Pass Filter sd_bwaa_freq 200Hz sd_en hp_freq hp_en gain_g gain_en VD1VD2 sample reset VD4 VD3 Q Q SET CL R S R seq_led_start seq_led_stop led_x_mode x=1...4 Q Q SET CL R S R seq_itg_start seq_itg_stop clk clk Q Q SET CL R S R seq_sdp_start seq_sdp_stop clk Q Q SET CL R S R seq_sdm1_start seq_sdm1_stop clk Q Q SET CL R S R seq_sdm2_start seq_sdm2_stop clk clk clk*16 + z-1 seq_adc_inc seq_adc + z-1 seq_adc_frac_inc seq_adc_frac div sd_subs adc_data div seq_div 1µs clkCounter 0...seq_period-1 Run / Stop Logic seq_count cycles seq_start Run/Reset read status init init register diode_ctrl +1 -1 ADC control
Document Feedback [v1-12] 2018-Feb-26 AS7000 − Detailed Description Optical Signal Conditioning Figure 52: Optical Signal Conditioning Synchronous Demodulator An optional synchronous demodulator can be used to detect small optical signals in the presence of large unwanted noise (ambient light) . Since the detector sy nchronizes to the LED frequency, the demodulator can only be used of the measurement sequencer is running. It includes input filer (high pass at 200Hz, adjustable low pass) and an 2nd order adjustable output low pass. The demodulator itself multiplies the signal by +1 / 0 / -1 with a timing which is controlled by the sequencer. Note(s): The optical signal conditioning stage need sigref_ en=1 for operation. High Pass Filter An optional high pass filter can be used to remove unwanted DC-components from the signal and allows further amplification. In order to guar antee fast settling times of the filter, four cutoff frequencies can be chosen. Gain Stage An optional gain stage can be used to amplify the signal after the DC-component has been removed. ADC adc_sel=1 adc_sel=0 gain_byp sd_byp Synchronous Demodulator Gain Stage hp_byp High Pass Filter sd_bwaa_freq 200Hz sd_en hp_freq hp_en gain_g gain _en from TIA Sequencer
[v1-12] 2018-Feb-26 Document Feedback AS7000 − Detailed Description Optical Signal Conditioning Registers Register bit sigref_en see register AFE_LED_CFG . Figure 53: AFE_SC_CFG 0x70: AFE_SC_CFG Field Name Rst Type Description 26 sd_pol_init 0 RW The low level driver shall ensure that this register is 0 if one of the seq_sdm pulses is first, and is 1 if the seq_sdp is first within a sequence. 25:24 aa_freq 0 RW Anti-aliasing filter cut-off frequency Setting Signal 01 0 k H z 12 0 k H z 24 0 k H z 36 0 k H z 20:13 sd_subs 0 RW Synchronous demodulator subsampling ratio between sequencer frequency and ADC sampling frequency. ADC-Fsample = Sequencyer_Frequency/(sd_subs+1) When setting to 0, then in every sequencer iteration the ADC will run. When setting to 1, then the first sequencer iteration will not trigger the ADC, but the second one will. Setting to N will make N iterations without ADC, followed by one iteration with the ADC measurement executed. It is recommended to use the ADC interrupt in this case and not the sequencer interrupt. 12:11 sd_bw 0 RW Synchronous demodulator low pass filter. Setting Frequency 01 0 H z 12 0 H z 24 0 H z 38 0 H z 10 hp_en 0 RW 0...Power down of the high pass filter 1...Enable high pass filter 9h p _ b y p 0 R W 0...HP filter is used 1...HP filter is bypassed
Document Feedback [v1-12] 2018-Feb-26 AS7000 − Detailed Description 8:7 hp_freq 0 RW High pass filter cutoff frequency Setting Cutoff frequency 00 . 3 3 H z 11 . 3 2 H z 25 . 2 8 H z 3 10.56Hz 6s d _ e n 0 R W 0...Power down of the synchronous demodulator 1...Enable synchronous demodulator 5s d _ b y p 0 R W 0...Synchronous demodulator is used 1...Synchronous demodulator is bypassed 3g a i n _ b y p 0 R W 0...Gain stage is used 1...Gain stage is bypassed 2:0 gain_g 0 RW Gain Setting Gain 41 6 53 2 66 4 7d o n ‘ t u s e 0x70: AFE_SC_CFG Field Name Rst Type Description
[v1-12] 2018-Feb-26 Document Feedback AS7000 − Detailed Description Sync Demodulator Example LED1 and LED2 should be modulated with 2kHz Demodulated signal should be sampled with 20Hz for 1 second. Calculation of sequencer values: 1. Modulation Frequency = 2kHz. Period = 500us. 2. Set sequencer period to 250us. -> seq_div=0, seq_period=500 3. Operation of LEDs between 0us and 100us (depends on LED and Amp-settings) -> seq_led_start=1, seq_led_stop=100 4. Operation of photo-amplifier and synchronous demodulator multipl. by +1 between 50us and 100us -> seq_sdp_start=50, seq_sdp_stop=100 5. Operation of photo-amplifier and synchronous demodulator multipl. by -1 between 300us and 350us -> seq_sdm1_start=300, seq_sdm1_stop=350 6. Sampling position at 495us + settling -> seq_adc=490 7. ADC should only sample at 20Hz (50ms). This means sampling at every 50ms/500us = 100th sequencer run. sd_subs=100 8. ADC values should be stor ed for 1 second. This means 1s/50ms = 20 samples must be stored. ->seq_count=20
Document Feedback [v1-12] 2018-Feb-26 AS7000 − Detailed Description Figure 54: Sync Demodulator Example Detail
[v1-12] 2018-Feb-26 Document Feedback AS7000 − Detailed Description Figure 55: Sync Demodulator Example
Document Feedback [v1-12] 2018-Feb-26 AS7000 − Detailed Description Electrical Analog Front End The electrical analog front end consists of three identical signal paths with independent settings of bias condition, gain and offset. Figure 56: Electrical Analog Front End Internal Circuit Note(s): 1. Resistor / T-gates resistance values are given as indication – do not rely on absolute values Input Pins Five general purpose pins can be used either as configurable GPIO for the processor or as anal og input pins for the electrical analog front end. The analog inputs can be configured to setup different amplifier topologies. GPIO0 GPIO1 GPIO6 GPIO5 GPIO4 VDD 00b … off 01b … 10µ A 10b … 100µA 11b … 1mA gpio_bias_current gpio_i_bias gpio_dac gpio_r_bias 160kΩ gpio_gst_in measure_dac T-gates: 50kΩ T-gates: 250Ω 50kΩ T-gates: 10kΩ gst_gain 0 … 1x 1 … 2x 2 … 4x 3 … 8x 4 … 16x 5 … 32x 6 … 64x 7 … don’t use 0AGND gst_ref SIGREF don’t use 128kΩ gpio_gst_in measure_dac on ADC Vref=1.6V AGND adc_sel=2 dac_value sigref_on_dac_buf SIGREF opamp & DAC enabled automatically 1.9V DAC
Document Feedback [v1-12] 2018-Feb-26 AS7000 − Detailed Description 15:13 gpio_r_bias 0 RW Resistive biasing Setting Meaning
0 No resistive biasing
1 Resistive biasing on GPIO4
2 Resistive biasing on GPIO5
3 Resistive biasing on GPIO6
4 Resistive biasing on GPIO1
5 Resistive biasing on GPIO0
12:10 gpio_i_bias 0 RW Current biasing Setting Meaning 0N o c u r r e n t b i a s i n g 1C u r r e n t b i a s i n g o n G P I O 4 2C u r r e n t b i a s i n g o n G P I O 5 3C u r r e n t b i a s i n g o n G P I O 6 4C u r r e n t b i a s i n g o n G P I O 1 5C u r r e n t b i a s i n g o n G P I O 0 9:8 gpio_bias_ current 0R W Current setting of gpio current bias Setting Current 0O F F 11 0 μA 21 0 0 μA 31 m A 0x90: AFE_EAF Field Name Rst Type Description
[v1-12] 2018-Feb-26 Document Feedback AS7000 − Detailed Description 7:5 gpio_gst_in 0 RW Gain stage input selection Setting Meaning
0 Not connected
4:3 gst_ref 0 RW Gain stage reference voltage Setting Meaning 0A G N D
1 DAC buffer
3 Reserved – do not use
2:0 gst_gain 0 RW Gain stage gain Setting Meaning 41 6 53 2 66 4
7 Reserved – do not use
0x90: AFE_EAF Field Name Rst Type Description
Document Feedback [v1-12] 2018-Feb-26 AS7000 − Detailed Description The AFE_EAF register is used to configure the electrical frontend Figure 59: AFE_EAF_DAC The AFE_EAF_DAC register is used to configure the dac value 0x94: AFE_EAF_DAC Field Name Rst Type Description 9:0 dac_value 0 RW DAC value (10 bit) 0x000 … 0V 0x1FF … 1.9V
Document Feedback [v1-12] 2018-Feb-26 AS7000 − Detailed Description ADC The ADC is a 14bit successive-approximation register (SAR) type. It supports 12 bit with very fast conversion time up to 1Msps and 14bit with moderate co nversion time up to 250ksps. The ADC is started by the sequence r and its timing or in manual mode (man_mode=1) by setting seq_start=1 (seq_start stays ‘1’ as long as the conversion runs). The AS7000 can be configured to trigger an interrupt upon end of conversion. Figure 66: ADC Internal Circuit and Multiplexer For best accuracy the ADC needs to recalibrate itself – use ams SDK to initiate the calibration procedure. CPU LDOenable VDD POR GPIO8 GPIO7 S R Q sleep_timer V_LDO gpio7_wakeup_en
[v1-12] 2018-Feb-26 Document Feedback AS7000 − Detailed Description Figure 67: Operating Characteristics of the ADC, VDD=3V, T AMB=25°C (unless otherwise noted) Figure 68: ADC Output Codes (12 Bit Resolution Setting Range) Symbol Parameter Conditions Min Typ Max Unit Vref Reference voltage V_ADCRef 1.6 V TCvref Reference voltage temperature coefficient ±50 ppm/°C Resolution adc_clock ≤ 1MHz Otherwise
12 Bit
INL Relative accuracy -8 8 LSB DNL Differential nonlinearity ±2 LSB Offset error ±8 LSB Gain error ±8 LSB SNR Signal-to-noise ratio Fsample = 1kHz, Fsignal=100Hz 80 dB THD Total harmonic distortion Fsample = 1kHz, Fsignal=100Hz -70 dB Tconv Conversion rate 12 bit resolution 1 μs Vin Input voltage range 0 Vref V ADC Output Codes: For 14 bit resolution the output data range is 0 to 16383, one LSB represents Vref/16384.
[v1-12] 2018-Feb-26 Document Feedback AS7000 − Detailed Description 19:17 adc_settling_ time 5R W ADC settling time: Do not use in interleaved mode. It defines the number of ADC clock cycles the sampling window is kept open additionally to its 4 ADC clock cycles. If the gain stage in the optical frontend is used (gain_ byp=0), set this to minimum 8μs. If adc_selfpd=1, set this to minimum 64μs and set adc_discharge=1. Setting Periods μs (@4MHz) μs (@2MHz) μs (@1MHz) 0 0 000 1 4 124 2 8 248 31 6 4 8 1 6 43 2 8 1 6 3 2 56 4 1 6 3 2 6 4 6 128 32 64 128 7 256 64 128 256 If adc_discharge=0 and adc_selfpd=0 and the TIA is connected directly to the ADC using following minimum settling times: pd_ampres minimum adc_settling_time 1MΩ 1μs 2MΩ-7MΩ 2μs 10MΩ-15MΩ 3μs 0xa4: AFE_ADC_CFG Field Name Rst Type Description
Document Feedback [v1-12] 2018-Feb-26 AS7000 − Detailed Description 15:12 adc_clock 7 RW ADC clock divider: The ADC clock is freely configurable. Note that values other than 4MHz, 2MHz, 1MHz and 500kHz will make the resulting timing very confusing for the human observer. Setting Periods ns kHz 021 2 5 8 0 0 0 142 5 0 4 0 0 0 263 7 5 2 6 6 6 385 0 0 2 0 0 0 41 06 2 5 1 6 0 0 51 27 5 0 1 3 3 3 61 48 7 5 1 1 4 2 71 6 1 0 0 0 1 0 0 0 81 8 1 1 2 5 8 8 8 92 0 1 2 5 0 8 0 0 10 22 1375 727 11 24 1500 666 12 26 1625 615 13 28 1750 571 14 30 1875 533 15 32 2000 500 11 adc_calibration 0 RW To activate self calibration, this bit must be asserted, and an ADC “conversion” has to be started in manual mode (man_mode=1) by asserting seq_start. It is suggested to let the CPU sleep and wait for the ADC interrupt. Also, a slow ADC clock should be used. 10 adc_interleave 0 RW Interleave mode 9a d c _ e n 0 R W 0...Reset ADC 1...Enable ADC Warning: In reset state the ADC clears its calibration data. Re-calibration is necessary next time it is enabled again. 0xa4: AFE_ADC_CFG Field Name Rst Type Description
[v1-12] 2018-Feb-26 Document Feedback AS7000 − Detailed Description 8:6 adc_sel 0 RW ADC Input Select 0… Trans impedance amplifier – see Figure 8 1… Optical frontend – see Figure 8 2… Electrical front end – see Figure 56 3… Do not use 4… Do not use 5… Temperature sensor (diode with approx. -2mV/K) 6… Do not use 7… Do not use 4a d c _ h i g h r e s 1R W ADC resolution depending on the Sampling speed Setting Selection 01 2 b i t 11 4 b i t 3:1 adc_multi_n 0 RW Defines number of samples that are taken in multimode (adc_multimode =1) Setting Sample Period 31 6 43 2 54 8 66 4 79 6 0xa4: AFE_ADC_CFG Field Name Rst Type Description
Document Feedback [v1-12] 2018-Feb-26 AS7000 − Detailed Description 0 adc_multimode 0 RW 0...If ADC is started one sample is measured 1...If ADC is started multiple samples are measured with "adc_multi_fs" interval and stored to memory by the DMA controller. The number of samples is defined with adc_ multi_n. In interleaved mode, the sampling time is 4x higher than in non-interleave mode. In non-interleave mode, if adc_multimode=0, only 1 sample is taken. In interleave mode, if adc_multimode=0, then ADC conversions are executed until the end of the sequencer period. If adc_multimode=1, then adc_multi_n is always taken into account. 0xa4: AFE_ADC_CFG Field Name Rst Type Description
[v1-12] 2018-Feb-26 Document Feedback AS7000 − Detailed Description Power Management a nd Operating Modes After the supply (VDD) is asserted the AS7000 automatically starts up. It is up to the ap plication software into which operating mode the AS7000 is changed (e.g. to power down mode). The AS7000 can operate in following modes: Figure 71: AS7000 Operating Modes Note(s): 1. Wakeup by GPIO7=high if gp io7_wakeup_en=1; applies for power down and deep sleep mode. 2. Wakeup by GPIO8=lo w if gpio8_wakeup_en=1. 3. In power down mode the AS7000 will always wakeup if GPIO8=low independent of previous setting of gpio8_wakeup_en. Mode Internal LDO (V_ LDO) 512Hz Oscillator 16MHz Oscillator CPU Wake Up CPU to Active Mode By Entered By Active Running - - Sleep mode Idle Any interrupt (any timer, GPIO) __WFI() command of CPU Deep sleep mode = reset; registers keep content 512Hz sleep_counter, GPIO7(1) and GPIO8(2) Use ams SDK for entering deep sleep Power down = reset; registers are reset GPIO7(1) and GPIO8(3) enter_ powerdown=
Document Feedback [v1-12] 2018-Feb-26 AS7000 − Detailed Description For operation of the sequencer the 16MHz oscillator is required, therefore the sequencer only operates in active or wait for interrupt mode. Clock Control Unit (CCU) for Peripheral Blocks All peripheral block have a reset bit and a clock enable bit. The purpose of these register bits is to disable clock to them when they are not used and therefore reduce power consumption. Note(s): Access to the register is not possible if the clock to the peripheral is disabled or reset is asserted. e.g. to access any register of AFE (like optical analog front end) set the register bits afe_resetn=1 and afe_enable=1. Wake-Up From Power Down Mode Figure 72: Wake-Up Logic From Power Down Mode CPU LDOenable VDD POR GPIO8 GPIO7 S R Q sleep_timer V_LDO gpio7_wakeup_en
[v1-12] 2018-Feb-26 Document Feedback AS7000 − Detailed Description MCU The MCU is a 32-bit ARM Cortex-M0-based RISC processor with 32kB of EEPROM memory and 4kB of RAM data memory. Details of the core processor can be found under infocenter.arm.com . The MCU offers the following features:
- System:
- ARM Cortex M0 processor with single cycle 32 bit multiplication instruction
- System tick timer
- Hardware protection to disable the read or read/write of the internal EEPROM and SRAM
- Unique ID for every device delivered
- Memory:
- 32kByte EEPROM memory
- 4 k B y t e R A M
- Peripherals:
- 9 general-purpose (GPIO) pins with configurable output structure
- U A R T
- I ² C M a s t e r
- I ² C S l a v e
- 1 4 b i t A D C
- W a t c h d o g t i m e r
- 2 general purpose 16 bit timer
- Clock:
- Internal 16MHz RC oscillator
- Internal 512Hz watchdog oscillator and timer
- Debug:
- Serial wire Debug
- Power control:
- Reduced power modes Sleep, Stop
- P o w e r O N r e s e t
Document Feedback [v1-12] 2018-Feb-26 AS7000 − Detailed Description Figure 86: CPU Internal Block Diagram ams delivers a SDK (Software Development Kit) for easy access of the internal digital and analog blocks. The SDK includes detailed documentation of the hardware (like I²C, UART) and includes low level drivers. For accessing of the peripheral registers, a base address needs to added. The base address depend s on the block used (see also ams provided SDK – software development kit). Base Address Function 0x40000000 CCU: Chip control unit 0x40010000 GPIO 0x40040000 I2CM: I2C Master 0x40050000 I2CS: I2C Slave 0x40060000 UART 0x40070000 Timers 0x40080000 AFE: Analog frontend controller Debug interface SWD ARM Cortex -M0 32-bit RISC EEPROM SRAM Clock generation Power control Reset AHB - APB Bridge GPIO MUX I2C Master SCL SDA I2C Slave SCL SDA UART TxD RxD GPIO0/8 SWD ADC 2x 16 bit Timer WDT Optical/electrical Front end RTC
Document Feedback [v1-12] 2018-Feb-26 AS7000 − Detailed Description GPIO Pins and Output Switch Matrix A flexible output switch matrix allows dynamic assignment of the internal digital blocks to the GPIO pins: Figure 88: Output Switch Matrix RxD GPIO UART TxD Out0 SWD Serial Wire Debug I NT, WAKE, in 0 Out2 Out3 Out4 Out5 Out6 Out7 Out8 Out0 M_S DA I2C Master M_SCL S_SDA I2C Slave S_SCL I NT, WAKE, in 1 I NT, WAKE, in 2 I NT, WAKE, in 3 I NT, WAKE, in 4 I NT, WAKE, in 5 I NT, WAKE, in 6 I NT, WAKE, in 7 I NT, WAKE, in 8 Selector Controlled by gpioX_func; X=0...9 GPIO8 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 Programming mode bit: enable_swd Wake up from deep sleep mode securitybit
[v1-12] 2018-Feb-26 Document Feedback AS7000 − Detailed Description Sequential Read is the extended form of Random Read, as more than one register-data bytes are transferred subsequently. In difference to the Random Read, for a sequential read the transferred register-data bytes are responded by an acknowledge from the master. The number of data bytes transferred in one sequence is unlimited (consider the behavior of the word-address counter). To terminate the transmission the master has to send a not-acknowledge following the last data byte and generate the STOP condition subsequently. Figure 96: I²C Current Address Read I²C Current Address Read: Shows the format of an I²C current address read access. To keep the access time as small as possible, this format allows a read access without the word address transfer in advance to the data transfer. The bus is idle and the master issues a START condition followed by the Device-Read address. Analogous to Random Read, a single byte transfer is terminated with a not-acknowledge after the 1st register byte. Analogous to Sequential Read an unlimited number of data bytes can be transferred, where the data byte s has to be responded with an acknowledge from the master. For termination of the transmission the master send s a not-acknowledge following the last data byte and a subsequent STOP condition. S DW A WA A NA read register WA++ dataSr DR P WA++
Document Feedback [v1-12] 2018-Feb-26 AS7000 − Detailed Description The CCU_IOFUNC0/1/2 gpioX_func register defines the multiplexing mode of each pin. Figure 110: gpioX_func Codings (X=0…8) The CCU_IOFUNC0/1/2 gpioX_pd fields define the pullup/pulldown configuration Figure 111: gpioX_pd Codings (X=0…8) gpioX_func Description 0G P I O 3I ² C M a s t e r 4I ² C S l a v e 5U A R T 7A n a l o g gpioX_pd Description 0N o n e
1 Weak Pull Up
2 Weak Pull Down
3 Keeper
Document Feedback [v1-12] 2018-Feb-26 AS7000 − Detailed Description Figure 114: CCU_RETENTION The CCU_RETENTION register is the only register that is not affected by powerdown, Only a power cycle will reset these bits. 0xfc: CCU_RETENTION Field Name Rst Type Description 30 enable_swd 1 RW Enable SWD interface on GPIO7/8 (overrides any gpio7_ func/gpio8_func setting). 31 securitybit 0 WS_SC securitybit, to disable access through the SWD interface in the final product. The bit can only be written to 1, not reset. If enabled by the factory or in EEPROM, the bootloader sets this bit before booting the user software. Therefore the image inside the EEPROM is protected against external access.
[v1-12] 2018-Feb-26 Document Feedback AS7000 − Application Information The AS7000 has a built-in I²C master and host device. Therefore it allows to connect an accelerometer used for motion artefact compensation in two ways: 1. Connected through the host and data provided by the host to the AS7000 via the AS7000 I²C slave 2. Connected directly to the AS7000 and the AS7000 I²C master retrieves the data from the accelerometer. Following two figures show the different configurations. Figure 115: Measurement System With Motion Artefact Compensation Note(s): 1. Accelerometer data provided by host. In above configuration the host needs to send the accelerometer data to the AS7000 via the I²C interface.
Application Information
+ RAM/ EEPROM & InterfacesGPIO4 GPIO3 GPIO2 GPIO1 GPIO0 GPIO8 GPIO7 GPIO6 GPIO5 LDO Ref Optical barrier AGND SIGREFVDD V_LDO GND VDD 2.6V-3.6V VD1 VD2 VD4 VD3 LED Supply (DCDC) Host ProcessorAccelerometer VDD LDO on ON=0 I2C to AS7000 VDD PMIC +Charger to LED Supply VBAT VBAT VBAT GPIO2=SDA GPIO3=SCL SDA SCL VDD INT VD3/VD4: if not used connect to GND on GND
Document Feedback [v1-12] 2018-Feb-26 AS7000 − Application Information Figure 116: Measurement System With Motion Artefact Compensation Using AS7000 Dedicated Accelerometer Note(s): 1. Accelerometer connected directly In above configuration, the AS7000 I²C master is used to poll the data from the accelerometer. The AS7000 has internal protection diodes on all GPIO pins connected to VDD. If VDD is switched off, all GPIO pins are clamped to this VDD supply plus one diode voltage (typically 0.6V). Therefore connect the periphery supply of these pins (example: I²C pins from host in above example connected to GPIO2/3), which are connected to the AS7000 GPIO pins to the same VDD supply as the AS7000. If this is not possible, ensure that these pins are at logic 0 if the VDD supply of AS7000 is switched off. AS7000 M0 CPU + RAM/ EEPROM & InterfacesGPIO4 GPIO3 GPIO2 GPIO1 GPIO0 GPIO8 GPIO7 GPIO6 GPIO5 LDO Ref Optical barrier AGND SIGREFVDD V_LDO GND 2.6V-3.6V VD1 VD2 VD4 VD3 LED Supply (DCDC) SCL SDA Accelerometer Host Processor LCD VDD LDO on ON=0 I2C to AS7000 VDD PMIC +Charger to LED Supply Bluetooth VBAT VBAT VBAT GPIO2 GPIO3 VDD INT on GND VD3/VD4: if not used connect to GND
Document Feedback [v1-12] 2018-Feb-26 AS7000 − Package Drawings & Markings Figure 119: Package Drawings Note(s): 1. XXXXX - Tracecode backside marking (upside down) Package Drawings & Markings GreenRoHS XXXXX
[v1-12] 2018-Feb-26 Document Feedback AS7000 − Ordering & Contact Information Figure 120:
Ordering Information
Note(s): 1. XXXXX - Tracecode backside marking Buy our products or get free samples online at: www.ams.com/ICdirect Technical Support is available at: www.ams.com/Technical-Support Provide feedback about this document at: www.ams.com/Document-Feedback For further information and requests, e-mail us at: ams_sales@ams.com For sales offices, distributors and representatives, please visit: www.ams.com/contact Headquarters ams AG Tobelbader Strasse 30
8141 Premstaetten
Austria, Europe Tel: +43 (0) 3136 500 0 Website: www.ams.com Ordering Code Type LED Configuration Marking Delivery Form Delivery Quantity AS7000-AA AS7000 Green/Green XXXXX(1) Tape & Reel 5000 pcs/reel AS7000-AAM AS7000 Green/Green XXXXX(1) Tape & Reel 500 pcs/reel Ordering & Contact Information
Document Feedback [v1-12] 2018-Feb-26 AS7000 − RoHS Compliant & ams Green Statement RoHS: The term RoHS compliant means that ams AG products fully comply with current RoHS directives. Our semiconductor products do not contain any chemicals for all 6 substance categories, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, RoHS compliant products are suitable for use in specif ied lead-free processes. ams Green (RoHS compliant and no Sb/Br): ams Green defines that in addition to RoHS compliance, our products are free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material). Important Information: The information provided in this statement represents ams AG knowledge and belief as of the date that it is provided. ams AG bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are unde rway to better integrate information from third parties. ams AG has taken and continues to take reasonable steps to prov ide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ams AG and ams AG suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. RoHS Compliant & ams Green Statement
[v1-12] 2018-Feb-26 Document Feedback AS7000 − Copyrights & Disclaimer Copyright ams AG, Tobelbader St rasse 30, 8141 Premstaetten, Austria-Europe. Trademarks Registered. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used with out the prior written consent of the copyright owner. Devices sold by ams AG are covered by the warranty and patent indemnification provisions appe aring in its General Terms of Trade. ams AG makes no warranty, express, statutory, implied, or by description regarding th e information set forth herein. ams AG reserves the right to ch ange specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with ams AG for current information. This product is intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications , such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by ams AG for each application. This product is provided by ams AG “AS IS” and any express or implied wa rranties, including, but not limited to the implied warranties of merchantability and fitness for a particular purpose are disclaimed. ams AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any th ird party shall arise or flow out of ams AG rendering of technical or other services. Copyrights & Disclaimer
Document Feedback [v1-12] 2018-Feb-26 AS7000 − Document Status Document Status Product Status Definition Product Preview Pre-Development Information in this datasheet is based on product ideas in the planning phase of development. All specifications are design goals without any warranty and are subject to change without notice Preliminary Datasheet Pre-Production Information in this datasheet is based on products in the design, validation or qualification phase of development. The performance and parameters shown in this document are preliminary without any warranty and are subject to change without notice Datasheet Production Information in this datasheet is based on products in ramp-up to full production or full production which conform to specifications in accordance with the terms of ams AG standard warranty as given in the General Terms of Trade Datasheet (discontinued) Discontinued Information in this datasheet is based on products which conform to specifications in accordance with the terms of ams AG standard warranty as given in the General Terms of Trade, but these products have been superseded and should not be used for new designs Document Status
[v1-12] 2018-Feb-26 Document Feedback AS7000 − Revision Information Note(s): 1. Page and figure numbers for the previous version may diff er from page and figure numbers in the current revision. 2. Correction of typographical er rors is not explicitly mentioned. Changes from 1-10 (2017-Feb-28) to current revision 1-12 (2018-Feb-26) Page 1-10 (2017-Feb-28) to 1-11 (2017-Sep-28) Added note under Absolute Maximum Ratings figure 5 1-11 (2017-Sep-28) to 1-12 (2018-Feb-26) Removed AS7000AB related content Revision Information
Document Feedback [v1-12] 2018-Feb-26 AS7000 − Content Guide
1 General Description
1 Key Benefits and Features
1 Applications
2 Block Diagram
3 Pin Assignments
5A b s o l u t e M a x i m u m R a t i n g s