AS5SP1M36DQR-167/IT

AS5SP1M36DQ AUSTIN | Alldatasheet

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AUSTIN SEMICONDUCTOR, INC. SSRAMSSRAMSSRAMSSRAMSSRAM AS5SP1M36DQ AS5SP1M36DQ Rev. 1.2 4/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. Austin Semiconductor, Inc. FIGURE 1: PIN ASSIGNMENT (Top View)36Mb Pipelined Sync SRAM

FEATURES

• Supports bus operation up to 200 MHz  Available speed grades are 200 and 166 MHz  Registered inputs and outputs for pipelined operation  3.3V core power supply  2.5V/3.3V I/O power supply  Fast clock-to-output times  Provide high-performance 3-1-1-1 access rate  User-selectable burst counter supporting Intel ®  Pentium ® interleaved or linear burst sequences  Separate processor and controller address strobes  Synchronous self-timed writes  Asynchronous output enable  Single Cycle Chip Deselect  Available in lead-free 100-pin TQFP package  IEEE 1149.1 JTAG-Compatible Boundary Scan  “ZZ” Sleep Mode Option OPTION MARKING Temperature Range Military Temp (-55oC to +125oC) /XT Industrial (-40oC to +85oC) /IT Enhanced (-40oC to +105oC) /ET GENERAL DESCRIPTION The AS5SP1M36DQ SRAM integrates 1M x 36/2M x 18 and 512K x 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE 1), depth- expansion Chip Enables (CE 2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWX and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent SELECTION GUIDE DQPB DQB DQB VDDQ VSSQ DQB DQB DQB DQB VSSQ VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA DQA DQA VSSQ VDDQ DQA DQA DQPA DQPC DQC DQc VDDQ VSSQ DQC DQC DQC DQC VSSQ VDDQ DQC DQC VDD NC VSS DQD DQD VDDQ VSSQ DQD DQD DQD DQD VSSQ VDDQ DQD DQD DQPD A A CE1 CE2 BWD BWC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A 30 31 100 CY7C1440AV33 (1M x 36) NC A A A A A NC/72M A VSS VDD A A A A A A A A MODE A AS5SP1M36DQ (1Mx36) burst addresses can be internally generated as controlled by the Advance pin (ADV). Address, data inputs, and write controls are registered on- chip to initiate a self-timed Write cycle.This part supports Byte Write operations (see Pin Descriptions and Truth Table for further details). Write cycles can be one to two or four bytes wide as controlled by the byte write control inputs. GW when active LOW causes all bytes to be written. The AS5SP1M36DQ operates from a +3.3V core power supply while all outputs may operate with either a +2.5 or +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. 200MHz 16 6MH Unit MaximumAccessTime 3.2 3.4 ns MaximumOperatingCurrent 425 375 mA MaximumCMOSStandbyCurrent 120 120 mA

AUSTIN SEMICONDUCTOR, INC. SSRAMSSRAMSSRAMSSRAMSSRAM AS5SP1M36DQ AS5SP1M36DQ Rev. 1.2 4/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. Austin Semiconductor, Inc. ADDRESS REGISTER ADV CLK BURST COUNTER AND LOGIC CLR ADSP ADSC MODE BWE GW CE1 CE2 CE3 OE ENABLE REGISTER OUTPUT REGISTERSSENSE AMPS OUTPUT BUFFERS E PIPELINED ENABLE INPUT REGISTERS A0, A1, A BWB BWC BWD BWA MEMORY ARRAY DQs DQPA DQPB DQPC DQPD SLEEP CONTROLZZ A[1:0]2 DQA ,DQPA BYTE WRITE REGISTER DQB ,DQPB BYTE WRITE REGISTER DQC ,DQPC BYTE WRITE REGISTER DQD ,DQPD BYTE WRITE REGISTER DQA ,DQPA BYTE WRITE DRIVER DQB ,DQPB BYTE WRITE DRIVER DQC ,DQPC BYTE WRITE DRIVER DQD ,DQPD BYTE WRITE DRIVER LOGIC BLOCK DIAGRAM PIN DEFINITIONS Name I/O Description A0, A1, A Input- Synchronous Address Inputs used to select one of the address locations. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 [2]are sampled active. A1: A0 are fed to the two-bit counter. BWA, BWC, BWE, BWG, Input- Synchronous Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled on the rising edge of CLK. GW Input- Synchronous Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global write is conducted (ALL bytes are written, regardless of the values on BWX and BWE). BWE Input- Synchronous Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted LOW to conduct a byte write. CLK Input- Clock Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation. CE1 Input- Synchronous Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a new external address is loaded.

AUSTIN SEMICONDUCTOR, INC. SSRAMSSRAMSSRAMSSRAMSSRAM AS5SP1M36DQ AS5SP1M36DQ Rev. 1.2 4/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. Austin Semiconductor, Inc. PIN DEFINITIONS (continued) CE2 Input- Synchronous Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device. CE2 is sampled only when a new external address is loaded. CE3 Input- Synchronous Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device. Not available for AJ package version. Not connected for BGA. Where referenced, CE3 is assumed active throughout this document for BGA. CE3 is sampled only when a new external address is loaded. OE Input- Asynchronous Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. ADV Input- Synchronous Advance Input signal, sampled on the rising edge of CLK, active LOW. When asserted, it automatically increments the address in a burst cycle. ADSP Input- Synchronous Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH. ADSC Input- Synchronous Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ZZ Input- Asynchronous ZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a non-time-critical “sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal pull-down. DQs, DQPX I/O- Synchronous Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled by OE . When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX are placed in a tri-state condition. VDD Power Supply Power supply inputs to the core of the device. VSS Ground Ground for the core of the device. VSSQ I/O Ground Ground for the I/O circuitry. VDDQ I/O Power Supply Power supply for the I/O circuitry. MODE Input- Static Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation. Mode Pin has an internal pull-up. TDO JTAG serial output Synchronous Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG feature is not being utilized, this pin should be disconnected. This pin is not available on TQFP packages. TDI JTAG serial input Synchronous Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being utilized, this pin can be disconnected or connected to V DD. This pin is not available on TQFP packages. TMS JTAG serial input Synchronous Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being utilized, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages. TCK JTAG- Clock Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must be connected to VSS. This pin is not available on TQFP packages. NC – No Connects. Not internally connected to the die NC/72M – No Connects. Not internally connected to the die. NC/72M are address expansion pins & are not internally connected to the die. Name I/O Description

AUSTIN SEMICONDUCTOR, INC. SSRAMSSRAMSSRAMSSRAMSSRAM AS5SP1M36DQ AS5SP1M36DQ Rev. 1.2 4/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. Austin Semiconductor, Inc. FUNCTIONAL OVERVIEW All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (t CO) is 3.2ns (200-MHz device). The AS5SP1M36DQ supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486 ∀! processors. The linear burst sequence is suited for processors that utilize a linear burst sequence. The burst order is user selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte Write operations are qualified with the Byte Write Enable (BWE) and Byte Write Select (BW X) inputs. A Global Write Enable (GW) overrides all Byte Write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self-timed Write circuitry. Three synchronous Chip Selects (CE 1, CE 2, CE 3) and an asynchronous Output Enable (OE) provide for easy bank selection and output tri-state control. ADSP is ignored if CE is HIGH. Single Read Accesses This access is initiated when the following conditions are satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2) CE 1, CE2, CE3 are all asserted active, and (3) the Write signals (GW, BWE) are all deserted HIGH. ADSP is ignored if CE 1 is HIGH. The address presented to the address inputs (A) is stored into the address advancement logic and the Address Register while being presented to the memory array. The corresponding data is allowed to propagate to the input of the Output Registers. At the rising edge of the next clock the data is allowed to propagate through the output register and onto the data bus within 3.2ns (200-MHz device) if OE is active LOW. The only exception occurs when the SRAM is emerging from a deselected state to a selected state, its outputs are always tri-stated during the first cycle of the access. After the first cycle of the access, the outputs are controlled by the OE signal. Consecutive single Read cycles are supported. Once the SRAM is deselected at clock rise by the chip select and either ADSP or ADSC signals, its output will tri-state immediately. Single Write Accesses Initiated by ADSP This access is initiated when both of the following conditions are satisfied at clock rise: (1) ADSP is asserted LOW, and (2) CE 1, CE2, CE3 are all asserted active. The address presented to A is loaded into the address register and the address advancement logic while being delivered to the memory array. The Write signals (GW, BWE, and BW X) and ADV inputs are ignored during this first cycle. ADSP-triggered Write accesses require two clock cycles to complete. If GW is asserted LOW on the second clock rise, the data presented to the DQs inputs is written into the corresponding address location in the memory array. If GW is HIGH, then the Write operation is controlled by BWE and BW X signals. The AS5SP1M36DQ provides Byte Write capability that is described in the Write Cycle Descriptions table. Asserting the Byte Write Enable input (BWE) with the selected Byte Write (BW X) input, will selectively write to only the desired bytes. Bytes not selected during a Byte Write operation will remain unaltered. A synchronous self-timed Write mechanism has been provided to simplify the Write operations. Because AS5SP1M36DQ is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQs inputs.Doing so will tri-state the output drivers. As a safety precaution, DQs are utomatically tri-stated whenever a Write cycle is detected, regardless of the state of OE. Single Write Accesses Initiated by ADSC ADSC Write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deserted HIGH, (3) CE 1, CE2, CE3 are all asserted active, and (4) the appropriate combination of the Write inputs (GW, BWE, and BW X) are asserted active to conduct a Write to the desired byte(s). ADSC-triggered Write accesses require a single clock cycle to complete. The address presented to A is loaded into the address register and the address advancement logic while being delivered to the memory array. The ADV input is ignored during this cycle. If a global Write is conducted, the data presented to the DQs is written into the corresponding address location in the memory core. If a Byte Write is conducted, only the selected bytes are written. Bytes not selected during a Byte Write operation will remain unaltered. A synchronous self-timed Write mechanism has been provided to simplify the Write operations. Because AS5SP1M36DQ is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQs inputs. Doing so will tri-state the output drivers. As a safety precaution, DQs are automatically tri-stated whenever a Write cycle is detected, regardless of the state of OE.

AUSTIN SEMICONDUCTOR, INC. SSRAMSSRAMSSRAMSSRAMSSRAM AS5SP1M36DQ AS5SP1M36DQ Rev. 1.2 4/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. Austin Semiconductor, Inc. Burst Sequences The AS5SP1M36DQ provides a two-bit wraparound counter, fed by A1: A0, that implements either an interleaved or linear burst sequence. The interleaved burst sequence is designed specifically to support Intel Pentium applications. The linear burst sequence is designed to support processors that follow a linear burst sequence. The burst sequence is user selectable through the MODE input. Asserting ADV LOW at clock rise will automatically increment the burst counter to the next address in the burst sequence. Both Read and Write burst operations are supported. Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CE 1, CE 2, CE 3, ADSP, and ADSC must remain inactive for the duration of t ZZREC after the ZZ input returns LOW. FUNCTIONAL OVERVIEW (continued) InterleavedBurstAddressTable Linear BurstAddressTable (MODE=FloatingorVDD) (MODE=GND) First Address A1:A0 Second Address A1:A0 Third Address A1:A0 Fourth Address A1:A0 First Address A1:A0 Second Address A1:A0 Third Address A1:A0 Fourth Address A1:A0 00 01 10 11 00 01 10 11 01 00 11 10 01 00 11 10 10 11 00 01 10 11 00 01 11 10 01 00 11 10 01 00 ZZModeElectricalCharacteristics Parameter Description Test Conditions Min Max Unit IDDZZ Sleepmodestandbycurrent ZZшVDDͲ0.2V mA tZZS DeviceoperationtoZZ ZZ шVDDͲ0.2V 2tCYC ns tZZREC ZZrecoverytimes ZZ ч0.2V 2tCYC ns tZZI ZZactivetosleepcurrent This parameterissamples 2tCYC ns tRZZI ZZinactivetoexitsleepcurrent This parameterissamples 0 ns

AUSTIN SEMICONDUCTOR, INC. SSRAMSSRAMSSRAMSSRAMSSRAM AS5SP1M36DQ AS5SP1M36DQ Rev. 1.2 4/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. Austin Semiconductor, Inc. TruthTable[2,3,4,5,6,7] Operation Add. Used CE1\\ CE2 CE3\\ ZZ ADSP\\ ADSC\\ ADV\\ WRITE \\ OE\\ CLK DQ DeselectCycle,PowerDown None H X X L X L X X X L ͲH TRI ͲSTATE DeselectCycle,PowerDown None L L X L L X X X X L ͲH TRI ͲSTATE DeselectCycle,PowerDown None L X H L L X X X X L ͲH TRI ͲSTATE DeselectCycle,PowerDown None L L X L H L X X X L ͲH TRI ͲSTATE DeselectCycle,PowerDown None L X H L H L X X X L ͲH TRI ͲSTATE SleepMode,PowerDown None X X X H X X X X X X TRI ͲSTATE READCycle,BeginBurst External L H L L L X X X L L ͲH Q READCycle,BeginBurst External L H L L L X X X H L ͲH TRI ͲSTATE WRITECycle,BeginBurst External L H L L H L X L X L ͲHD READCycle,BeginBurst External L H L L H L X H L L ͲH Q READCycle,BeginBurst External L H L L H L X H H L ͲH TRI ͲSTATE READCycle,ContinueBurst Next X X X L H H L H L L ͲH Q READCycle,ContinueBurst Next X X X L H H L H H L ͲH TRI ͲSTATE READCycle,ContinueBurst Next H X X L X H L H L L ͲH Q READCycle,ContinueBurst Next H X X L X H L H H L ͲH TRI ͲSTATE WRITECycle,ContinueBurst Next X X X L H H L L X L ͲHD WRITECycle,ContinueBurst Next H X X L C H L L X L ͲHD READCycle,SuspendBurst Current X X X L H H H H L L ͲH Q READCycle,SuspendBurst Current X X X L H H H H H L ͲH TRI ͲSTATE READCycle,SuspendBurst Current H X X L X H H H L L ͲH Q READCycle,SuspendBurst Current H X X L X H H H H L ͲH TRI ͲSTATE WRITECycle,SuspendBurst Current X X X L H H H L X L ͲHD WRITECycle,SuspendBurst Current H X X L X H H L X L ͲHD Notes: 2.X=Don'tCare,H=LogicHIGH,L=LogicLOW 3.WRITE\\=LwhenanyoneormoreByteWriteenablesignalsandBWE\\=LorGW\\=L.WRITE\\=HwhenallBytewriteenablesignals,BWE\\,GW\\=H. 4.TheDQpinsarecontrolledbythecurrentcycleandtheOEsignal.OEisasynchronousandisnotsampleswiththeclock. 5.CE1\\,CE2,CE3\\areavailableonlyintheTQFPpackage.BGApackagehasonly2chipselectsCE1\\andCE2. 6.TheSRAMalwaysinitiatesareadcyclewhenADSP\\isasserted,regardlessofthestateofGW\\,BWE\\,orBWX\\.Writesmayoccuronlyonsubsequentclocks aftertheADSP\\orwiththeassertionofADSC\\.Asaresult,OE\\mustbedrivenHIGHpriortothestartofthewritecycletoallowtheoutputstotriͲstate.OE\\ isadon'tcarefortheremainderofthewritecycles. 7.OE\\isasynchronousandisnotsampledwiththeclockrise.Itismaskedinternallyduringwritecycles.DuringareadcyclealldatabitsaretriͲstatewhenOE\\ isinactiveorwhenthedeviceisdeselected,andalldatabitsbehaveasoutputwhenOE\\isactive(LOW). TruthTableforRead/Write[4,8,9] Function GW\\ BWE\\ BWD\\B W C\\B W B\\B W A\\ Read H H XXXX Read H L HHHH WriteByteAͲ(DQAandDQPA) HLHHHL WriteByteBͲ(DQBandDQPB) HLHHLH WriteBytesB,AH L H H L L WriteByteCͲ(DQCandDQPC) HLHLHH WriteBytesC,A HLHLHL WriteBytesC,BH L H L L H WriteBytesC,B,A HLHLLL WriteByteDͲ(DQDandDQPD) HL LHHH WriteBytesD,AH L L H H L WriteBytesD,B H L L H L H WriteBytesD,B,AH L L H L L WriteBytesD,C HLLLH H WriteBytesD,C,A HLLLHL WriteBytesD,C,B HLLLLH WriteAllBytes H LLLLL WriteAllBytes L XXXXX Notes: 8.BWX\\representsanybytewritesignal.ToenableanybytewriteBWX\\,aLogicLOWsignalshouldbe appliedatclockrise.Anynumberofbytewritescanbeenabledatthesametimeforanygivenwrite. 9.Tableonlylistsapartiallistingofthebytewritecombinations.AnycombinationofBWX\\isvalid. Appropriatewritewillbedonebasedonwhichbytewriteisactive.

AUSTIN SEMICONDUCTOR, INC. SSRAMSSRAMSSRAMSSRAMSSRAM AS5SP1M36DQ AS5SP1M36DQ Rev. 1.2 4/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. Austin Semiconductor, Inc. IEEE 1149.1 Serial Boundary Scan (JTAG) The AS5SP1M36DQ incorporates a serial boundary scan test access port (TAP). This part is fully compliant with IEEE Standard 1149.1. The TAP operates using JEDEC-standard 3.3V or 2.5V I/O logic levels. The AS5SP1M36DQ contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW SS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to V DD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. TAP Controller State Diagramg TEST-LOGIC RESET RUN-TEST/ IDLE SELECT DR-SCAN SELECT IR-SCAN CAPTURE-DR SHIFT-DR CAPTURE-IR SHIFT-IR EXIT1-DR PAUSE-DR EXIT1-IR PAUSE-IR EXIT2-DR UPDATE-DR EXIT2-IR UPDATE-IR 1 1 0 0 1 1 0 0 0 0 11 0 The 0/1 next to each state represents the value of TMS at the rising edge of TCK. Test Access Port (TAP) Test Clock (TCK) The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test MODE SELECT (TMS) The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this ball unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See Tap Controller Block Diagram.) Test Data-Out (TDO) The TDO output ball is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See Tap Controller State Diagram.) TAP Controller Block Diagram Bypass Register Instruction Register 012 Identification Register 012293031 ... Boundary Scan Register Selection Circuitr y Selection Circuitry TCK TMS TAP CONTROLLER TDI TDO Note: The JTAG feature is not tested. GBNT.

AUSTIN SEMICONDUCTOR, INC. SSRAMSSRAMSSRAMSSRAMSSRAM AS5SP1M36DQ AS5SP1M36DQ Rev. 1.2 4/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. Austin Semiconductor, Inc. Performing a TAP Reset A RESET is performed by forcing TMS HIGH (V DD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a High-Z state. TAP Registers Registers are connected between the TDI and TDO balls and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK. Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls as shown in the Tap Controller Block Diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board-level serial test data path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between the TDI and TDO balls. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (V SS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all the input and bidirectional balls on the SRAM. The boundary scan register is loaded with the contents of the RAM I/O ring when the TAP controller is in the Capture- DR state and is then placed between the TDI and TDO balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the I/O ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table. TAP Instruction Set Overview Eight different instructions are possible with the three bit instruction register. All combinations are listed in the Instruction Codes table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail below. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO balls. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO balls and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. The SAMPLE Z command puts the output bus into a High-Z state until the next command is given during the “Update IR” state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be

AUSTIN SEMICONDUCTOR, INC. SSRAMSSRAMSSRAMSSRAMSSRAM AS5SP1M36DQ AS5SP1M36DQ Rev. 1.2 4/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. Austin Semiconductor, Inc. possible. To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller’s capture set-up plus hold times (t CS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation. The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required—that is, while data captured is shifted out, the preloaded data can be shifted in. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. EXTEST The EXTEST instruction enables the preloaded data to be driven out through the system output pins. This instruction alsoselects the boundary scan register to be connected for serial access between the TDI and TDO in the shift-DR controller state. EXTEST OUTPUT BUS TRI-STATE IEEE Standard 1149.1 mandates that the TAP controller be able to put the output bus into a tri-state mode. The boundary scan register has a special bit located at, bit #89 (for 165-FBGA package) or bit #138 (for 209-FBGA package). When this scan cell, called the “extest output bus tri-state”, is latched into the preload register during the “Update-DR” state in the TAP controller, it will directly control the state of the output (Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it will enable the output buffers to drive the output bus. When LOW, this bit will place the output bus into a High-Z condition. This bit can be set by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell, during the “Shift-DR” state. During “Update-DR”, the value loaded into that shift-register cell will latch into the preload register. When the EXTEST instruction is entered, this bit will directly control the output Q-bus pins. Note that this bit is pre-set HIGH to enable the output when the device is powered-up, and also when the TAP controller is in the “Test-Logic-Reset” state. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. Tap Timing tTL Test Clock (TCK) 123456 Test Mode Select (TMS) tTH Test Data-Out (TDO) tCYC Test Data-In (TDI) tTMSHtTMSS tTDIHtTDIS tTDOX tTDOV DON’T CARE UNDEFINED

AUSTIN SEMICONDUCTOR, INC. SSRAMSSRAMSSRAMSSRAMSSRAM AS5SP1M36DQ AS5SP1M36DQ Rev. 1.2 4/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. Austin Semiconductor, Inc. TAPACSwitchingCharacteristicsOvertheoperatingrange[10,11] Parameter Description Min Max Unit tTCYC TCKClockCycleTime 50 ns tTF TCKClockFrequency 20 MHz tTH TCKClockHIGHTime 20 ns tTL TCKClockLOWTime 20 ns tTDOV TCKClockLOWtoTDOValid 10 ns tTDOX TCKClockLOWtoTDOInvalid 0 ns tTMSS TMSSetͲuptoTCKClockRise 5 ns tTDIS TDISetͲuptoTCKClockRise 5 ns tCS CaptureSetͲupotoTCKRise 5 ns tTMSH TMSHoldafterTCKClockRise 5 ns tTDIH TDIHoldafterClockRise 5 ns tCH CaptureHoldafterClockRise 5 ns Clock SetͲupTimes OutputTimes HoldTimes 3.3V TAP AC Test Conditions 2.5 TAP AC Test Conditions 3.3V TAP AC Output Load Equivalent 2.5 TAP AC Output Load Equivalent Notes: 10. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register. 11. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 1 ns. TDO 1.5V 20pFZ = 50ΩO 50Ω TDO 1.25V 20pFZ = 50ΩO 50Ω

AUSTIN SEMICONDUCTOR, INC. SSRAMSSRAMSSRAMSSRAMSSRAM AS5SP1M36DQ AS5SP1M36DQ Rev. 1.2 4/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. Austin Semiconductor, Inc. TAODCElectricalCharacteristicsandOperatingConditons 0oC<TA<+70oC;VDD=3.135to3.6Vunlessotherwisenoted) [12] Parameter Description Min Max Unit 2.4 V 2.0 V VDDQ=3.3V 2.9 V VDDQ=2.5V 2.1 V IOL=8.0mA V DDQ=3.3V 0.4 V IOL=1.0mA V DDQ=2.5V 0.4 V VDDQ=3.3V 0.2 V VDDQ=2.5V 0.2 V VDDQ=3.3V 2.0 VDD+0.3 V VDDQ=2.5V 1.7 VDD+0.3 V VDDQ=3.3V Ͳ0.3 0.8 V VDDQ=2.5V Ͳ0.3 0.7 V IX InputLoadCurrent Ͳ55 μ A VIL InputLOWVoltage GNDчVINчVDDQ TestConditions VOL1 OutputLOWVoltage VOL2 OutputLOWVoltage IOH=100μA VIH InputHIGHVoltage VOH1 OutputHIGHVoltage VOH2 OutputHIGHVoltage IOH=Ͳ4.0mA,VDDQ=3.3V IOH=Ͳ1.0mA,VDDQ=2.5V IOH=Ͳ100μA IdentificationRegisterDefinitions InstructionField 1Mx36 Description RevisionNumber(31:29) 000 Describes theversionnumber DeviceDepth(28:24)[13] 01011 Reserved forInternalUse Architecture/MemoryType(23:18) 000000 Defines memorytypeandarchitecture BusWidth/Density(17:12) 100111 Defines widthanddensity JEDECIDCode(11:1) 00000110100 Allows uniqueidentificationofSRAMvendor IDRegisterPresenceIndicator(0) 1 Indicates thepresenceofanIDregister ScanRegisterSizes RegisterName Bit Size(x36) Instruction 3 Bypass 1 ID 32 Notes: 12. All voltages referenced to V SS (GND). 13. Bit #24 is '1' in the ID Register Definitions for both 2.5V and 3.3V versions of this device. + Austin Semiconductor uses Cypress die so this code reflects Cypress.

AUSTIN SEMICONDUCTOR, INC. SSRAMSSRAMSSRAMSSRAMSSRAM AS5SP1M36DQ AS5SP1M36DQ Rev. 1.2 4/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. Austin Semiconductor, Inc. IdentificationCodes Instruction Code Description EXTEST 000 CapturestheI/Oringcontents. IDCODE 001 LoadstheIDregisterwiththevendorIDcodeandplacestheregisterbetweenTDIandTDO. ThisoperationdoesnotaffectSRAMoperations. SAMPLEZ 010 CapturesI/Oringcontents.PlacestheboundaryscanregisterbetweenTDIandTDO.Forcesall SRAMoutputdriverstoaHighͲZstate. RESERVED 011 Donotuse:Thisinstructionisreservedforfutureuse. SAMPLE/PRELOAD 100 CapturesI/Oringcontents.PlacestheboundaryscanregisterbetweenTDIandTDO.Doesnot affectSRAMoperation. RESERVED 101 Donotuse:Thisinstructionisreservedforfutureuse. RESERVED 110 Donotuse:Thisinstructionisreservedforfutureuse. BYPASS 111 PlacesthebypassregisterbetweenTDIandTDO.ThisoperationdoesnotaffectSRAM operations. Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Ambient Temperature with Supply Voltage on V DC Voltage Applied to Outputs DDQ + 0.5V (per MIL-STD-883, Method 3015) OperatingRange Range Ambient Temperature VDD VDDQ Commercial 0oCto+70oC Industrial Ͳ40oCto+85oC Enhanced Ͳ40oCto+105oC Military Ͳ55oCto+125oC 3.3VͲ5%/+10% 2.5VͲ5%toVDD

AUSTIN SEMICONDUCTOR, INC. SSRAMSSRAMSSRAMSSRAMSSRAM AS5SP1M36DQ AS5SP1M36DQ Rev. 1.2 4/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. Austin Semiconductor, Inc. ElectricalCharacteristicsOvertheOperatingRange[17,18] DCElectricalCharacteristicsOvertheOperatingRange Parameter Description Min Max Unit VDD PowerSupplyVoltage 3.135 3.6 V

3.135 VDD V

2.375 2.625 V 2.4 V 2.0 V 0.4 V 0.4 V 2.0 V DD+0.3V V 1.7 VDD+0.3V V Ͳ0.3 0.8 V Ͳ0.3 0.7 V Ͳ30 μA 5μ A Ͳ5μ A 30 μA Ioz Output LeakCurrent GNDчV1чVDDQ,OutputDisabled Ͳ55 μ A VDD=Max,IOUT=0mA, 5Ͳnscycle,200MHz 425 mA f=fMAX=1/tCYC 6Ͳnscycle,167MHz 375 mA VDD=Max,DeviceDeselected VINшVIHorVINчVIL f=fMAX=1/tCYC VDD=Max,DeviceDeselected VINч0.3VorVINшVDDQͲ0.3V, f=0 VDD=Max,DeviceDeselected VINч0.3VorVINшVDDQͲ0.3V, f=fMAX=1/tCYC VDD=Max,DeviceDeselected VINшVIHorVINчVIL,f=0 Notes: 17.Overshoot:VIH(AC)<VDD+1.5V(PulsewidthlessthanTCYC/2),undershoot:VIL(AC)>Ͳ2V(PulsewidthlessthantCYC/2) 18.TpowerͲup:Assumesalinearrampfrom0VtoVDD(min)within200ms.DuringthistimeVIH<VDDandVDDQчVDD. IDD VDDOperatingSupply Current mA ISB3 AutomaticCE PowerDownCurrentͲ CMOSInputs AllSpeeds 200 mA ISB4 AutomaticCE PowerDownCurrentͲ TTLInputs AllSpeeds 135 225 mA ISB2 AutomaticCE PowerDownCurrentͲ CMOSInputs AllSpeeds 120 mA ISB1 AutomaticCE PowerDownCurrentͲ TTLInputs AllSpeeds TestConditions Ͳ55 InputLOWVoltage[17]VIL for3.3VI/O for2.5VI/O IX InputLeakageCurrent exceptZZandMODE InputCurrentofMODE InputCurrentofZZ OutputLOWVoltage for3.3VI/O,IOH=8.0mA for2.5VI/O,IOH=1.0ma μA Input=VSS Input=VDD Input=VSS Input=VDD GNDчV1чVDDQ for3.3VI/O for2.5VI/O VOL VIH InputHIGHVoltage[17] for3.3VI/O for2.5VI/O VOH OutputHIGHVoltage for3.3VI/O,IOH=Ͳ4.0mA for2.5VI/O,IOH=Ͳ1.0ma I/OSupplyVoltageVDDQ

AUSTIN SEMICONDUCTOR, INC. SSRAMSSRAMSSRAMSSRAMSSRAM AS5SP1M36DQ AS5SP1M36DQ Rev. 1.2 4/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. Austin Semiconductor, Inc. Capacitance[19] Parameter Description Test Conditions 100TQFP Max. Unit CIN InputCapacitance TA=25oC,f=1MHz, 6.5 pF CCLK ClockInputCapacitance VDD=3.3V 3p F CI/O Input/OutputCapacitance VDDQ=2.5V 5.5 pF ThermalResistance[19] Parameter Description Test Conditions 100TQFP Package Unit ȺJA ThermalResistance (JunctiontoAmbient) 25.21 oC/W ȺJC ThermalResistance (JunctiontoCase) 2.28 oC/W Testconditionsfollowstandardtestmethods andproceduresformeasuringthermal impedance,perEIA/JESD51 AC Test Loads and Waveforms Note: 19. Tested initially and after any design or process change that may affect these parameters. OUTPUT R = 317: R = 351: 5p F INCLUDING JIG AND SCOPE(a) (b) OUTPUT RL = 50: Z0 = 50: VT = 1.5V 3.3V ALL INPUT PULSES VDDQ GND 90%10% 90% 10% d 1ns d 1ns (c) OUTPUT R = 1667: R = 1538: 5p F INCLUDING JIG AND SCOPE(a) (b) OUTPUT RL = 50: Z0 = 50: VT = 1.25V 2.5V ALL INPUT PULSESVDDQ GND 90%10% 90% 10% d 1ns d 1ns (c) 3.3V I/O Test Load 2.5V I/O Test Load

AUSTIN SEMICONDUCTOR, INC. SSRAMSSRAMSSRAMSSRAMSSRAM AS5SP1M36DQ AS5SP1M36DQ Rev. 1.2 4/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. Austin Semiconductor, Inc. SwitchingCharacteristicsOvertheOperatingRange[24,25] Min Max Min Max tPOWER VDD(Typical)tothefirstaccess[20] 11 m s tCYC ClockCycleTime 5 6 ns tCH ClockHIGH 2.0 2.4 ns tCL ClockLOW 2.0 2.4 ns tCO DataOutputValidAfterCLKRise 3.2 3.4 ns tDOH DataOutputHoldAfterCLKRise 1.5 1.5 ns tCLZ ClocktoLowͲZ[21,22,23] 1.3 1.5 ns tCHZ ClocktoHighͲZ[21,22,23] 3.0 3.4 ns tOEV OE\\LOWtoOutputValid 3.0 3.4 ns tOELZ OE\\LOWtoOutputLowͲZ[21,22,23] 00 n s tOEHZ OE\\HIGHtoOutputLowͲZ[21,22,23] 3.0 3.4 ns tAS AddressSetͲupBeforeCLKRise 1.4 1.5 ns tADS ADSC\\,ADSP\\SetͲupBeforeCLKRise 1.4 1.5 ns tADVS ADV\\SetͲupBeforeCLKRise 1.4 1.5 ns tWES GW\\,BWE\\BWx\\SetͲupBeforeCLKRise 1.4 1.5 ns tDS DataInputSetͲupBeforeCLKRise 1.4 1.5 ns tCES ChipEnableSetͲupBeforeCLKRise 1.4 1.5 ns tAH AddressHoldAfterCLKRise 0.4 0.5 ns tADH ADSP\\,ADSC\\HoldAfterCLKRise 0.4 0.5 ns tADVH ADV\\HoldAfterCLKRise 0.4 0.5 ns tWEH GW\\,BWE\\BWx\\SetͲupAfterCLKRise 0.4 0.5 ns tDH DataInputSetͲupAfterCLKRise 0.4 0.5 ns tCEH ChipEnableSetͲupAfterCLKRise 0.4 0.5 ns OutputTimes SetͲUpTimes HoldTimes Notes: 20.Thisparthasavoltageregulatorinternally;tPOWERisthetimethatthepowerneedstobesuppliedaboveVDD(minimum)initiallybeforeareadorwrite operationcanbeinitiated. 21.tCHZ,tCLZ,tOELZ,andtOEHZarespecifiedwithACtestconditionsshownin(b)ofACTestLoads.Transitionismeasured±200mVfromsteadyͲstatevoltage. 22.Atanygivenvoltageandtemperature,tOEHZislessthantOELZandtCHZislessthantCLZtoeliminatebuscontentionbetweenSRAMswhensharingthesame databus.Thesespecificationsdonotimplyabuscontentioncondition,butreflectparametersguaranteedoverworstcaseuserconditions.Deviceisdesignedto achieveHighͲZpriortoLowͲZunderthesamesystemconditions. 23.Thisparameterissampledandnot100%tested. 25.Testconditionsshownin(a)ofACTestLoadsunlessotherwisenoted. Ͳ200 Ͳ166 UnitParameter Description [20] Clock

AUSTIN SEMICONDUCTOR, INC. SSRAMSSRAMSSRAMSSRAMSSRAM AS5SP1M36DQ AS5SP1M36DQ Rev. 1.2 4/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. Austin Semiconductor, Inc. Switching Waveforms Read Cycle Timing[26] Note: 26. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH. t CYC tCL CLK ADSP tADHtADS ADDRESS tCH OE ADSC CE tAHtAS tCEHtCES GW, BWE, BWx Data Out (Q) High-Z t CLZ tDOH tCO ADV t OEHZ t CO Single READ BURST READ tOEV t OELZ t CHZ ADV suspends burst. Burst wraps around to its initial state tADVHtADVS tWEHtWES tADHtADS Q(A2) Q(A2 + 1) Q(A2 + 2)Q(A1) Q(A2) Q(A2 + 1)Q(A2 + 3) A2 A3 Deselect cycle Burst continued with new base address DON’T CARE UNDEFINED

AUSTIN SEMICONDUCTOR, INC. SSRAMSSRAMSSRAMSSRAMSSRAM AS5SP1M36DQ AS5SP1M36DQ Rev. 1.2 4/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. Austin Semiconductor, Inc. Write Cycle Timing[26, 27] Note: 27. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW. Switching Waveforms (continued) t CYC tCL CLK ADSP tADHtADS ADDRESS tCH OE ADSC CE tAHtAS tCEHtCES BWE, BWX Data Out (Q) High-Z ADV BURST READ BURST WRITE A2 A3 Data In (D) Extended BURST WRITE D(A2 + 2) Single WRITE tADHtADS tADHtADS t OEHZ tADVHtADVS tWEHtWES tDHtDS GW tWEHtWES Byte write signals are ignored for first cycle when ADSP initiates burst ADSC extends burst ADV suspends burst DON’T CARE UNDEFINED

AUSTIN SEMICONDUCTOR, INC. SSRAMSSRAMSSRAMSSRAMSSRAM AS5SP1M36DQ AS5SP1M36DQ Rev. 1.2 4/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. Austin Semiconductor, Inc. Read/Write Cycle Timing[26, 28, 29] Notes: 28. The data bus (Q) remains in high-Z following a Write cycle, unless a new read access is initiated by ADSP or ADSC. 29. GW is HIGH. Switching Waveforms (continued) tCYC tCL CLK ADSP tADHtADS ADDRESS tCH OE ADSC CE tAHtAS tCEHtCES BWE, BWX Data Out (Q) High-Z ADV Single WRITE D(A3) A4 A5 A6 D(A5) D(A6)Data In (D) BURST READBack-to-Back READs High-Z Q(A2)Q(A1) Q(A4) Q(A4+1) Q(A4+2) tWEHtWES Q(A4+3) tOEHZ tDHtDS tOELZ tCLZ tCO Back-to-Back WRITEs DON’T CARE UNDEFINED

AUSTIN SEMICONDUCTOR, INC. SSRAMSSRAMSSRAMSSRAMSSRAM AS5SP1M36DQ AS5SP1M36DQ Rev. 1.2 4/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. Austin Semiconductor, Inc. ZZ Mode Timing[30, 31] Notes: 30. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 31. DQs are in high-Z when exiting ZZ sleep mode. Switching Waveforms (continued) t ZZ I SUPPLY CLK ZZ t ZZREC ALL INPUTS (except ZZ) DON’T CARE I DDZZ t ZZI t RZZI Outputs (Q) High-Z DESELECT or READ Only

AUSTIN SEMICONDUCTOR, INC. SSRAMSSRAMSSRAMSSRAMSSRAM AS5SP1M36DQ AS5SP1M36DQ Rev. 1.2 4/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. Austin Semiconductor, Inc. Package Diagrams NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE 3. DIMENSIONS IN MILLIMETERS BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 0.30±0.08 0.65 20.00±0.10 22.00±0.20 1.40±0.05 12° ±1° 1.60 MAX. 0.05 MIN. 0.60±0.15 0° MIN. 0.25 0° -7° (8X) STAND-OFF R 0.08 MIN. TYP. 0.20 MAX. 0.15 MAX. 0.20 MAX. R 0.08 MIN. 0.20 MAX. 14.00±0.10 16.00±0.20 0.10 SEE DETAIL A DETAIL A 100 31 50 GAUGE PLANE 1.00 REF. 0.20 MIN. SEATING PLANE 100-pin TQFP (14 x 20 x 1.4 mm) (51-85050) 51-85050-*B

AUSTIN SEMICONDUCTOR, INC. SSRAMSSRAMSSRAMSSRAMSSRAM AS5SP1M36DQ AS5SP1M36DQ Rev. 1.2 4/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. Austin Semiconductor, Inc. Temperature Range Military Temp (-55oC to +125oC) Industrial (-40oC to +85oC) Enhanced (-40oC to +105oC) ORDERINGINFORMATION PartNumber Configuration Speed (MHz) Pkg. AS5SP1M36DQͲ167/IT 1M x36PipelinedSynchSRAM 167 100 PinTQFP AS5SP1M36DQͲ200/IT 1M x36PipelinedSynchSRAM 200 100 PinTQFP AS5SP1M36DQͲ167/ET 1M x36PipelinedSynchSRAM 167 100 PinTQFP AS5SP1M36DQͲ200/ET 1M x36PipelinedSynchSRAM 200 100 PinTQFP AS5SP1M36DQͲ167/XT 1M x36PipelinedSynchSRAM 167 100 PinTQFP AS5SP1M36DQͲ200/XT 1M x36PipelinedSynchSRAM 200 100 PinTQFP PBOPTION(WHEREAVAILABLE) PartNumber Configuration Speed (MHz) Pkg. AS5SP1M36DQRͲ167/IT 1M x36PipelinedSynchSRAM 167 100 PinTQFP AS5SP1M36DQRͲ200/IT 1M x36PipelinedSynchSRAM 200 100 PinTQFP AS5SP1M36DQRͲ167/ET 1M x36PipelinedSynchSRAM 167 100 PinTQFP AS5SP1M36DQRͲ200/ET 1M x36PipelinedSynchSRAM 200 100 PinTQFP AS5SP1M36DQRͲ167/XT 1M x36PipelinedSynchSRAM 167 100 PinTQFP AS5SP1M36DQRͲ200/XT 1M x36PipelinedSynchSRAM 200 100 PinTQFP Enhanced(Ͳ40oCto+105oC) MilitaryTemp(Ͳ55oCto+125oC) Industrial(Ͳ40oCto+85oC) Enhanced(Ͳ40oCto+105oC) MilitaryTemp(Ͳ55oCto+125oC) Industrial(Ͳ40oCto+85oC)

AUSTIN SEMICONDUCTOR, INC. SSRAMSSRAMSSRAMSSRAMSSRAM AS5SP1M36DQ AS5SP1M36DQ Rev. 1.2 4/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. Austin Semiconductor, Inc. DOCUMENT TITLE 36Mb Pipelined Sync SRAM

REVISION HISTORY

Rev # History Release Date Status

1.0 Datasheet Creation + January 2009 Release

1.1 updated order chart March 2009 Release 1.2 updated speeds (pg1, 15) April 2009 Release + From baseline Cypress datasheet doc# 38-05383 Rev E