AS5LC512K8_09 AUSTIN | Alldatasheet

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Rev. 2.1 08/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. Austin Semiconductor, Inc.

FEATURES

  • Ultra High Speed Asynchronous Operation  Fully Static, No Clocks  Multiple center power and ground pins for improved noise immunity  Easy memory expansion with CE\\ and OE\\ options  All inputs and outputs are TTL-compatible  Single +3.3V Power Supply +/- 0.3V  Data Retention Functionality Testing  Cost Efficient Plastic Packaging  Extended Testing Over -55ºC to +125ºC for plastics OPTIONS MARKING  Timing 12ns access -12 15ns access -15 20ns access -20 25ns access -25  Operating Temperature Ranges Military (-55 oC to +125 oC) XT Industrial (-40oC to +85oC) IT  Package(s) Ceramic Flatpack F No. 307 Plastic SOJ (400 mils wide) DJ Ceramic LCC EC No. 210  2V data retention/low power L PIN ASSIGNMENT (Top View) 36-Pin PSOJ (DJ) 36-Pin CLCC (EC) GENERAL DESCRIPTION The AS5LC512K8 is a 3.3V high speed SRAM. It offers flexibility in high-speed memory applications, with chip enable (CE\\) and output enable (OE\\) capabilities. These features can place the outputs in High-Z for additional flexibility in system design. Writing to these devices is accomplished when write enable (WE\\) and CE\\ inputs are both LOW. Reading is accomplished when WE\\ remains HIGH and CE\\ and OE\\ go LOW. As a option, the device can be supplied offering a reduced power standby mode, allowing system designers to meet low standby power requirements. This device operates from a single +3.3V power supply and all inputs and outputs are fully TTL-compatible. The AS5LC512K8DJ offers the convenience and reliability of the AS5LC512K8 SRAM and has the cost advantage of a plastic encapsulation. 36-Pin Flat Pack (F) AVAILABLE AS MILITARY SPECIFICATIONS MIL-STD-883 for Ceramic Extended Temperature Plastic (COTS) 512K x 8 SRAM

3.3 VOLT HIGH SPEED SRAM with

For more products and information please visit our web site at www.austinsemiconductor.com

Rev. 2.1 08/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. Austin Semiconductor, Inc. FUNCTIONAL BLOCK DIAGRAM TRUTH TABLE MODE OE\\ CE\\ WE\\ I/O POWER STANDBY X H X HIGH-Z STANDBY READ L L H Q ACTIVE NOT SELECTED H L H HIGH-Z ACTIVE WRITE X L L D ACTIVE SNOITCNUFNIP 81A-0As tupnIsserddA \\EWe lbanEetirW \\ECe lbanEpihC \\EOe lbanEtuptuO O/I 0 O/I- 7 stuptuO/stupnIataD V CC rewoP V SS dnuorG CNn oitcennoCoN X = Don’t Care VCC GND INPUT BUFFER 4,194,304-BIT MEMORY ARRAY

1024 ROWS X

4096 COLUMNS

*POWER DOWN CE\\ OE\\ WE\\ DQ8 DQ1 A0-A18 *On the low voltage Data Retention option.

Rev. 2.1 08/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. Austin Semiconductor, Inc. ABSOLUTE MAXIMUM RATINGS* Voltage on Vcc Supply Relative to Vss *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. ** Junction temperature depends upon package type, cycle time, loading, ambient temperature and airflow, and humidity. ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS (-55oC < TA < +125oC & -40oC < TA < +85oC ; Vcc = 3.3V +0.3%) CAPACITANCE MAX DESCRIPTION CONDITIONS SYM -12 -15 -20 -25 UNITS NOTES Power Supply Current: Operating CE\\ < VIL; Vcc = MAX f = MAX = 1/tRC Outputs Open ICCSP 80 70 60 55 mA 3, 2 "L" Version Only ICCLP 60 50 40 35 mA Power Supply Current: Standby CE\\ > VIH, All other inputs < VIL, Vcc = MAX, f = 0, Outputs Open ISBTSP 20 20 20 20 mA "L" Version Only ISBTLP 15 15 15 15 mA CE\\ > Vcc -0.2V; Vcc = MAX VIN<Vss +0.2V or VIN>Vcc -0.2V; f = 0 ISBCSP 15 15 15 15 mA "L" Version Only ISBCLP 9999 m A /G01/G02/G03/G04/G05/G06/G07/G08/G06/G09/G0A /G04/G09/G0A/G01/G06/G08/G06/G09/G0A/G03 /G03/G0B/G0C /G0C/G06/G0A /G0C/G0D/G0E /G0F/G0A/G06/G08/G03 /G0A/G09/G08/G02/G03 /G01/G02/G03/G04/G05 /G07/G08/G09/G0A /G0B/G0C/G0D/G09/G08/G0E /G0F/G10 /G11/G0D/G12/G05/G13/G09/G14 /G11 /G01/G02 /G15/G16/G15 /G11/G0E/G0E /G17/G18/G16/G19 /G11 /G0F /G01/G02/G03/G04/G05 /G0C/G0D/G1A /G0B/G0C/G0D/G09/G08/G0E /G18/G10 /G11/G0D/G12/G05/G13/G09/G14 /G11 /G01/G03 /G1B/G18/G16/G19 /G18/G16/G1C /G11 /G0F /G01/G02/G03/G04/G05 /G0C/G14/G13/G1D/G13/G09/G14 /G1E/G04/G1F/G1F/G14/G02/G05 /G18/G11 /G20 /G11 /G01/G04 /G20 /G11/G0E/G0E /G01 /G03/G01 /G1B/G15 /G15 μ/G21 /G22/G04/G05/G03/G04/G05 /G0C/G14/G13/G1D/G13/G09/G14 /G1E/G04/G1F/G1F/G14/G02/G05 /G22/G04/G05/G03/G04/G05/G0B/G23/G10 /G24/G08/G23/G13/G25/G12/G14/G26 /G18/G11 /G20 /G11 /G05/G06/G07 /G20 /G11/G0E/G0E /G01 /G03/G05 /G1B/G15 /G15 μ/G21 /G22/G04/G05/G03/G04/G05 /G07/G08/G09/G0A /G11/G0D/G12/G05/G13/G09/G14 /G01 /G05/G02 /G27 /G1B/G28/G16/G18 /G29/G21 /G11 /G05/G02 /G15/G16/G28 /G1B/G1B/G1B /G11 /G0F /G22/G04/G05/G03/G04/G05 /G0C/G0D/G1A /G11/G0D/G12/G05/G13/G09/G14 /G01 /G05/G03 /G27/G1C/G29 /G21 /G11 /G05/G03 /G1B/G1B/G1B /G18/G16/G2A /G11 /G0F PARAMETER CONDITIONS SYMBOL MAX UNITS NOTES Input Capacitance CI 9p F4 Output Capactiance Co 6 pF 4 TA = 25oC, f = 1MHz VIN = 0

Rev. 2.1 08/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. Austin Semiconductor, Inc. ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (-55oC < TA < +125oC or -40oC to +85oC; Vcc = 3.3V +0.3%) DESCRIPTION SYM -12 -15 -20 -25 UNITS NOTESMIN MA X MIN MA X MIN MA X MIN MA X READ CYCLE Read Cycle Time tRC 12 15 20 25 ns Address Access Time tAA 12 15 20 25 ns Chip Enable Access Time tACE 12 15 20 25 ns Output Hold From Address Change tOH 2222n s Chip Enable to Output in Low-Z tLZCE 2222n s 4 , 6 , 7 Chip Disable to Output in High-Z tHZCE 6789 n s 4 , 6 , 7 Output Enable Acess Time tAOE 6789 n s Output Enable to Output in Low-Z tLZOE 0000n s 4 , 6 , 7 Output Disable to Output in High-Z tHZOE 6789 n s 4 , 6 , 7 WRITE CYCLE WRITE Cycle Time t WC 12 15 20 25 ns Chip Enable to End of Write tCW 8 1 01 21 3 n s Address Valid to End of Write tAW 8 1 01 21 3 n s Address Setup Time tAS 0000n s Address Hold From End of Write tAH 0000n s WRITE Pulse Width tWP 10 12 15 15 ns Data Setup Time tDS 6788n s Data Hold Time tDH 1111n s Write Disable to Output in Low-Z tLZWE 2222n s 4 , 6 , 7 Write Enable to Output in High-Z tHZWE 5677n s 4 , 6 , 7

Rev. 2.1 08/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. Austin Semiconductor, Inc. NOTES 1. All voltages referenced to V SS (GND). 2. I CC limit shown is for absolute worst case switching of ADDR, ADDR\\, ADDR, etc. 3. I CC is dependent on output loading and cycle rates. 4. This parameter is guaranteed but not tested. 5. Test conditions as specified with the output loading as shown in Fig. 1 unless otherwise noted. tLZCE, tLZWE, tLZOE, t HZCE, tHZOE and tHZWE are specified with CL = 5pF as in Fig. 2. Transition is measured ±200mV from steady state voltage. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE, and tHZWE is less than tLZWE. 8. WE\\ is HIGH for READ cycle. 9. Device is continuously selected. Chip enables and output enables are held in their active state. 10. Address valid prior to, or coincident with, latest occurring chip enable. 11. tRC = Read Cycle Time. 12. Chip enable and write enable can initiate and terminate a WRITE cycle. 13. Output enable (OE\\) is inactive (HIGH). 14. Output enable (OE\\) is active (LOW). 15. ASI does not warrant functionality nor reliability of any product in which the junction temperature exceeds 150°C. Care should be taken to limit power to acceptable levels. Fig. 1 Output Load Equivalent Fig. 2 Output Load Equivalent DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only) AC TEST CONDITIONS DESCRIPTION SYM MIN MAX UNITS NOTES Vcc for Retention Data VDR 2V Data Retention Current Vcc = 2.0V ICCDR 6.5 mA Chip Deselect to Data tCDR 0n s 4 Operation Recovery Time tR 20 ms 4, 11 CONDITIONS CE\\ > VCC -0.2V VIN > VCC -0.2 or 0.2V 3.3V Q 353Ω 5 pF 319Ω Q 30 pF RL = 50 Ω VL = 1.5V ZO=50Ω

Rev. 2.1 08/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. Austin Semiconductor, Inc. LOW VCC DATA RETENTION WAVEFORM READ CYCLE NO. 11, 2 (Address Controlled, CE\\ = OE\\ = VIL, WE\\ = VIH) READ CYCLE NO. 2 (WE\\ = VIH) 1234 1 23 4 1 23 4 1 23 4 1234 Don’t Care Undefined 123456 1 2345 6 1 2345 6 1 2345 6 123456 123456789012345 123456789012345 123456789012345 123456789012345 123456789012345 123456789012345 123456789012345 123456789012345 12345 1 234 5 1 234 5 1 234 5 1 234 5 1 234 5 1 234 5 12345 1234567 1 23456 7 1 23456 7 1 23456 7 1 23456 7 1 23456 7 1 23456 7 1234567 123456789012345 123456789012345 123456789012345 123456789012345 123456789012345 123456789012345 123456789012345 123456789012345 1234 1 23 4 1 23 4 1 23 4 1 23 4 1 23 4 1 23 4 1234 123456 1 2345 6 1 2345 6 1 2345 6 1 2345 6 1 2345 6 1 2345 6 123456 DATA RETENTION MODE 4.5V 4.5V VDR > 2V VDR tCDR tR VCC CE\\ VIH- VIL- ADDRESS tRC 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 12345678901 1 234567890 1 1 234567890 1 1 234567890 1 1 234567890 1 12345678901 tOH tAA Previous Data Valid Data ValidI/O, DATA IN & OUT V ALID ADDRESS tRC tAOE CE\\ tLZOE tACE 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 12345 1 234 5 1 234 5 1 234 5 1 234 5 12345 Data ValidHigh-Z tHZOE tHZCE tPD I/O, DATA IN & OUT Icc tLZCE tPU NOTES: 1. WE\\ is HIGH for READ cycle. 2. Device is continuously selected. Chip enables and output enables are held in their active state.

Rev. 2.1 08/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. Austin Semiconductor, Inc. WRITE CYCLE NO. 11 (CE Controlled) WRITE CYCLE NO. 21, 2 (Write Enabled Controlled) 1234567890 1234567890 1234567890 1234567890 123456789012345678901234 1 2345678901234567890123 4 1 2345678901234567890123 4 123456789012345678901234 12345678901234567890123456 1 234567890123456789012345 6 1 234567890123456789012345 6 12345678901234567890123456 123456 123456 123456 123456 123456789012345678 1 2345678901234567 8 1 2345678901234567 8 123456789012345678 123456789012345678 1 2345678901234567 8 1 2345678901234567 8 123456789012345678 ADDRESS tWC tCW CE\\ tAW Data Valid tAH tAS I/O, DATA OUT tWP1 tDS tDH WE\\ I/O, DATA IN High-Z High-Z ADDRESS tWC tCW CE\\ 1234567890 1234567890 1234567890 1234567890 1234567890 12345678901234567890 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 12345678901234567890 123456789012345678901 1 2345678901234567890 1 1 2345678901234567890 1 1 2345678901234567890 1 123456789012345678901 1234567 1234567 1234567 1234567 1234567 123456789012345 1 2345678901234 5 1 2345678901234 5 1 2345678901234 5 123456789012345 12345678901234567 1 234567890123456 7 1 234567890123456 7 1 234567890123456 7 12345678901234567 tAW Data Valid tAH tAS I/O, DATA OUT 123456 123456 123456 123456 123456 tWP1 tDH WE\\ I/O, DATA IN High-Z High-Z NOTES: 1. Chip enable and write enable can initiate and terminate a WRITE cycle. 2. Output enable (OE\\) is inactive (HIGH).

Rev. 2.1 08/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. Austin Semiconductor, Inc. WRITE CYCLE NO. 31, 2, 3 (WE Controlled) ADDRESS tWC tCW CE\\ 123456789 123456789 123456789 123456789 123456789012345678901 1 2345678901234567890 1 1 2345678901234567890 1 123456789012345678901 1234567890123456789012 1 23456789012345678901 2 1 23456789012345678901 2 1234567890123456789012 1234567 1234567 1234567 1234567 1234567890123456 1 23456789012345 6 1 23456789012345 6 1234567890123456 12345678901234567 1 234567890123456 7 1 234567890123456 7 12345678901234567 tAW Data Valid tAH tAS DATA OUT 123456 123456 123456 123456 Data Undefined tWP2 tDS tDH tHZWE tLZWE WE\\ DATA IN High-Z NOTES: 1. At any given temperature and voltage condition, t HZCE is less than tLZCE, and tHZWE is less than tLZWE. 2. Chip enable and write enable can initiate and terminate a WRITE cycle. 3. Output enable (OE\\) is active (LOW).

Rev. 2.1 08/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. Austin Semiconductor, Inc. MECHANICAL DEFINITIONS* ASI Case #307 (Package Designator F) Bottom View 36 1 c A Q *All measurements are in inches. D e b Top View S EL 12345678 1 234567 8 1 234567 8 1 234567 8 1 234567 8 1 234567 8 1 234567 8 12345678 Pin 1 identifier area MIN MAX A 0.096 0.125 b 0.015 0.022 c 0.003 0.009 D 0.910 0.930 D1 0.840 0.860 E 0.505 0.515 E2 0.385 0.397 e L 0.250 0.370 Q 0.020 0.045 SYMBOL ASI SPECIFICATIONS

0.050 BSC

Rev. 2.1 08/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. Austin Semiconductor, Inc. *All measurements are in inches. MECHANICAL DEFINITIONS* Package Designator DJ MIN MAX A 0.128 0.148 A1 0.025 --- A2 0.082 --- B 0.015 0.020 b 0.026 0.032 C 0.007 0.013 D 0.920 0.930 E 0.435 0.445 E1 0.395 0.405 e SYMBOL ASI SPECIFICATIONS

0.370 BSC

Rev. 2.1 08/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. Austin Semiconductor, Inc. MECHANICAL DEFINITIONS* ASI Case #210 (Package Designator EC) D E 1234567 1 23456 7 1 23456 7 1 23456 7 1 23456 7 1 23456 7 1 23456 7 1 23456 7 1 23456 7 1234567 Pin 1 identifier area L e B R *All measurements are in inches. A P MIN MAX A 0.080 0.100 A1 0.054 0.066 B 0.022 0.028 D 0.910 0.930 D1 0.840 0.860 E 0.445 0.460 e L L2 0.115 0.135 P --- 0.006 R 0.009 TYP ASI SPECIFICATIONS SYMBOL

0.100 TYP

Rev. 2.1 08/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. Austin Semiconductor, Inc.

ORDERING INFORMATION

*AVAILABLE PROCESSES IT = Industrial Temperature Range -40 oC to +85oC XT = Extended Temperature Range -55 oC to +125oC 883C = Full Military Processing1 -55oC to +125oC OPTIONS DEFINITIONS L = 2V Data Retention / Low Power NOTES: 1. 883C process available with ceramic packaging only. EXAMPLE: AS5LC512K8F-12L/XT Device Number Package Type Speed ns Options Process AS5LC512K8 F -12 L /* AS5LC512K8 F -15 L /* AS5LC512K8 F -20 L /* AS5LC512K8 F -25 L /* EXAMPLE: AS5LC512K8DJ-20L/883C Device Number Package Type Speed ns Options** Process AS5LC512K8 DJ -12 L /* AS5LC512K8 DJ -15 L /* AS5LC512K8 DJ -20 L /* AS5LC512K8 DJ -25 L /* EXAMPLE: AS5LC512K8EC-15L/IT Device Number Package T ype Speed ns Options** Process AS5LC512K8 EC -12 L /* AS5LC512K8 EC -15 L /* AS5LC512K8 EC -20 L AS5LC512K8 EC -25 L /*

Rev. 2.1 08/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. Austin Semiconductor, Inc. DOCUMENT TITLE 512K x 8 SRAM 3.3 VOLT HIGH SPEED SRAM with CENTER POWER PINOUT Rev # History Release Date Status 2.1 Pg 1: Changed 0.3% to 0.3V August 200 9 Release