AS5501 AMSCO | Alldatasheet
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M ultim ode Pow erline-M odem D ata Sheet R ev A AS5501 / AS5502 M ultim ode Pow erline M odem D ata Sheet
M ultim ode Pow erline-M odem A S5501 / A S 5502 K ey Features: A S5501/02 is an FSK -m odem device for narrow -band FSK com m unication via a Pow er-Line. The device is operated w ith a single supply voltage of 5V w hile the attached TX -driver stage is generating a 7V pp (A S5501) or a 14V pp (A S5502) FSK -signal w ith very low distortion w hich needs a supply of the external driver stage of 12V (A S5501) and 24V (A S5502) respectively. The high output-voltages w hich gets coupled to the pow er-line by using a transform er w ith proper ratios gives the advantage to low er the output im pedance of the buffer w hile the buffer supply-current gets kept sm all. Precise filtering gives an receiver perform ance w ith low B ER -figures at <13dB of S/N w hite inband-noise and <-40dB S/N w ith m onochrom atic outband-noise and a sensitivity of 1.5m V The carrier frequency is program m able in a range from 64kH z to 140kH z to support a big variety of com m unication-bands including hom e-autom ation applications. M odulation depth and B aud-R ate are program m able to 600H z/1200H z and 600, 1200, 2400B /s. There is a carrier-detect function included to support channels w ith protocoll. In addition to the m odem -function a reference voltage output is available as w ell as a supply-supervision. AS5501 / AS5502 M ultim ode Pow erline M odem D ata Sheet R ev A, M ay 2000 Page 1/25
AS5501 / AS5502 M ultim ode Pow erline M odem D ata Sheet R ev A, M ay 2000 Page 2/25
- FU N C T IO N A L D E SC R IPT IO N The A S5501/02 is a SY N C H R O N O U S H A LF D U PLEX FSK M O D EM w ith program m able FSK -frequencies, B aud-R ate and R eceiverFilter-C haracteristics w orking w ith a single +5V SU PPLY . The circuit is designed to be used w ith an external buffer-stage and transform er- coupling to transfer data over a PO W ER -LIN E. A m ask-program m ed default setting defines the state after pow er-up (reset) see chapter 1.1. W ith the serial interface the default setting can be overw ritten. A 0/C S SD -IN SC LK R ES-TH M C LK SD -O U T R ESN V R EF C K SY S SER IF R ESET TIM IN G A FC F A G N D TxFb TxO ut1 M 1M P1M contr. & clock signals TX D TxEn TR AN SM ITTER R X I,A G N D ,C K T X ,SC -C LK ... ZC R EC EIVER C D R X D C LR /T R X O ,IFI,IFO TST-IN TEST-M U X TST-O U T A V SS A V D D D V SS D V D D TxO ut2 AS5501 / AS5502 M ultim ode Pow erline M odem D ata Sheet R ev A, M ay 2000 Page 3/25
1.1 SE R IF, R E SE T , T IM IN G
C ontrol R egister O utput PO R B A N D G A P R EF. TIM IN G V R EF R ESNR ES-TH M C LK C K SY S Test1,2 SC -C LK m ux C O N TR O L R EG ISTER S D efault Setting R om TX EN ZC B D 1,2, ZC EN , M M V TX EN I C K TX IF-SC C LK Fm ixer M clk/2
1.1.1 SER IA L IN TER FA C E
There is a serial interface im plem ented for setting the control bits by a C PU . Three bytes are available w ith follow ing definitions and default contents (after reset). R eg.-N am e addr D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 8 M R K -R E G (def. value) 00H M R K 1 M R K 2 M R K 3 M R K 4 M R K 5 M R K 6 M R K 7 M R K 8 G L O B A L (def. value) 01H M R K 9 B D 1 B D 2 R xB w 1 R xB w 2 ZC EN M M V PW D T E ST 02H TEST1 TEST2 A SY N A gcH digM ix noTSTin TxSyn FC dO n (The default setting of the register "TEST" is alw ays 00h.) B it-N am e Function default val. default function M R K 1-9 defines TX M ark Frequency (63.9k-140.55kH z) 453 131.85kH z B D 1,2 defines B aud-R ate and M odulation-D epth 1, 1 2400H z/1200H z R X B W 1,2 defines R X -B andPassFilter B andw idth 1, 0 4.8kH z @ 132.45kH z Z C E N disable ZeroC rossing TX -Sync 1 ZC -disabled M M V disables transm it Tim eout 0 Tim eO ut enabled PW D enables pow er dow n m ode 0 pow ered up T E ST 1,2 enables Test M ode 1-3 0, 0 norm al m ode A SY N disable synchronized receive data R X D 0 sync. R X D A gcH hold A G C counter-state 0 A G C -loop active digM ix enables digital m ixer; analog m ixer enabled by def. 0 analog m ixer noT ST in TST-out function only for receiver debugging 0 TSTin& out availab. T xSyn enables TX D sam pling w ith C LR /T rising-edge 0 C LR /T gets synchronised by TX D -edges FC dO n enables faster C D -O N tim ing (5/B drate) 0 Tcdon=(10/B drate) AS5501 / AS5502 M ultim ode Pow erline M odem D ata Sheet R ev A, M ay 2000 Page 4/25
D efault Setting: The default values show n in the table above, are related to the standard version of this device. (D efault setting of the registers can be changed by m odification of the IC 's m etal2 layer. In this w ay special versions of this device can be defined and produced w hich are identified by different m arking (see paragr. 2). A special version w ill how ever only be installed for annual deliveries not low er than 100000 devices and against upfront funding for the special tooling required.) Serial Interface O peration: The serial interface is built to w ork in tw o different m odes. The m ode of operation is defined by the logical state of the signal SC LK sam pled (using the first rising edge of Fosc/512 signal) 46usec after a high going edge of the reset signal (R ESN ). A -M ode (standard) Features: - 2 or 3 w ire serial bus - 8 bit data form at - data gets clocked on rising edge and shifted on falling edge of SC LK - default polarity of signal SC LK is LO W (C PO L=0, C PM A =0) - single and sequential read and w rite operations possible - D 7 is first bit valid valid valid valid SC LK SD -IN A O /C S M SB LSB tcssu tdsu tdhd tcshd W R IT E O PE R A T IO N tspick SD -O U T (open drain output in high im pedance state) valid valid SC LK SD -IN A O /C S header R E A D O PE R A T IO N SD -O U T address D 7 D 0 AS5501 / AS5502 M ultim ode Pow erline M odem D ata Sheet R ev A, M ay 2000 Page 5/25
Features: - 2 w ire serial bus - 9 bit data form at - data gets clocked on rising edge and shifted on falling edge - single and sequential w rite operation possible - default polarity of signal SC LK is H IG H - acknow ledge bit (9th bit) output (0 ... data acknow ledged) - D 7 is the first bit - A 2 and A 1 chip-address bits are internally set to 1 valid acknow ledge SC LK SD -IN A O /C S 1st M SB nth LSB W R IT E O PE R A T IO N /SD -O U T start condition 1st LSB acknow ledgedata valid data valid data output output stop condition B IT SE Q U E N C E 1 0 1 0 1 1 A 0 1 0 X X X X X X A 1 A 0 0 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 H eader (8bit) R eg. A ddress (8bit) D ata (8bit) C hip A ddress bits S t a r t A C K A C K S t o p A C K
1.1.2 R ESET
V R EF: A B and G ap R eference block is included for generation of a reference-voltage V R EF w ith nom inal 2.5V needed for an external function (pow er-fail detection) and as reference for the pow er on reset. PO R : A pow er-on reset function w ith external adjustable threshold and fixed off-delay (300m s) defined by the m aster-clock is im plem ented. W hen pin R ES-TH is floating the PO R - O FF threshold is nom inal 3.75V .There is a hysteresis of typ. 100m V im plem ented to V -O N . (In Test-M ode 2 and 3 the Por-delay is reduced to 1.17m s) AS5501 / AS5502 M ultim ode Pow erline M odem D ata Sheet R ev A, M ay 2000 Page 6/25 B IT SE Q U E N C E X X X X X X X 0 X X X X X X A 1 A 0 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 H eader (8bit) R eg. A ddress (8bit) D ata (8bit) C om m and bits (available for future use) (for A -M ode)
2.5V V R EF PO R NR esTh R 1 R 2 R 3 R 1=R 2=R 3=appr.25kV D D V SSV SS V D D R a R b k=R b / (R a+R b) O ff-D elay porv V th = 2*V R EF 1+k w ith R a, R b << R 1,R 2,R 3: V D D porv PO R N300m s R hyst=appr.290k W ith V (R esTh) defined by external resistors m uch sm aller than R 1-3, the PO R - threshold can be set in the range of 2.5V to 5.0V according to the given equation.
1.1.3 TIM IN G
M C LK : The circuit gets clocked by an 11.0592M H z M A STER C LO C K from external w hich is the frequency reference for all R X and TX functions. Since this circuit is w orking as a narrow band FSK -m odem , the precision of this clock is very critical. C K SY S: The m aster-clock divided by 2 is presented at the output C K SY S. In test-m ode1 this pin is used to m easure the FSK _ZC signal. In test-m ode 2 this pin is used to m easure the PLL-output SC -C LK . In test-m ode 3 this pin is used to m easure the PLL-output Fm ixer. TxEnI: Transm ission gets initialized by setting the input signal TxEn to low . W hen ZC EN (zero-crossing TX -sync) is disabled, the internal signal TxEnI is follow ing and setting the TX -driver active im m ediately. W hen ZC EN is enabled, the signal TxEnI is set to low after the high-going edge of ZC -input after TxEn w as forced low . TxEn ZC C K R /T valid valid valid valid R X D TX D receive transm it TxEnI C K TX TX D -input gets strobed by C K R /T in TxSyn-m ode w hich can be entered w ith setting D 7 of the TST-R eg. to H . In default m ode (asynchr. TX D ) the C K R /T gets synchronised by TX D -edges w ith a clock 64 tim es the baud-rate. TX -TIM EO U T: There is a tim eout-function im plem ented w hich sets the device back to receive-m ode (TxEnI=H ) after 3 seconds of transm ission. This tim eout-function can be disabled by setting the contol-bit M M V by the serial interface. In test-m ode 2 and 3 the 3sec tim eout is divided by 256 to 11.7m s to reduce test-tim e. AS5501 / AS5502 M ultim ode Pow erline M odem D ata Sheet R ev A, M ay 2000 Page 7/25
C K TX : The transm it clock is dependent on the B aud-R ate setting B D 1,2. B D 1 B D 2 division factor fom C K SY S B aud-R ate (C K TX ) 0 0 9216dec 600H z 1 0 4608dec 1200H z 0 1 4608dec 1200H z 1 1 2304dec 2400H z IF-SC C LK : The interm ediate frequency SC -filter is settable to tw o different m odes, one for dF=600H z and the other for dF=1200H z (dF=Fspace-Fm ark). These m odes are defined by the SC -clock frequency w hich is generated in the tim ing block. B D 1 B D 2 IFcenter IFbandw division factor fom C K SY S IF-SC -C LK 0 X 2700H z 1200H z 96dec 57.6kH z 1 X 5400H z 2400H z 48dec 115.2kH z
1.2 T R A N SM IT T E R
B PFb B PFc O utStage TxO ut1 TxFb M 1M P1MB IA S FR EG -G EN B PF & O utStage Sw itched C ap Filter C lock G enerator TX -FSK / M IX ER -Fref G enerator Fm ixer A G N D C K TX FG B D 1,2 M R K -R EG (+20, +40) (+0..4, +0..8) 0..511 SM F TxO ut2 TxEnI PLL A FC F D IV n AS5501 / AS5502 M ultim ode Pow erline M odem D ata Sheet R ev A, M ay 2000 Page 8/25
There is one FR EQ U EN C Y -SY N TH ESISER used to generate the FSK -signal. W ith the input signal TX D strobed w ith the high going edge of C K TX the control input of the synthesiser gets m odified w hich results in frequency shift corresponding to the data-input. In receive-m ode, the sam e synthesiser is used to generate the M ixer reference-clock. The M ixer-Frequency Fm ixer is set to a value to fold dow n the FSK -signal to one of tw o possible IF-frequencies (2.7kH z / 5.4kH z). The SC C LK -PLL is used to filter the phase jitter of the second frequency-synthesiser generating the reference-clock for the SC -Filter. There is an external capacitor needed as low -pass filtercom ponent of the PLL-loop. The B A N D PA SS Filter is used to lim it the output-spectrum properly for pow er-line m odem applications. The O U TPU T-STA G E is designed to be connected to an external buffer arrangem ent for m inim ising the output-im pedance and increasing the output-sw ing. The interface to the external circuit is done w ith special I/O -pins allow ed to operate w ith voltages up to +24V . W ith tw o bias pins M 1M and P1M the external buffer-stage gets biased (activated). W hen these tw o pins are inactive, the buffer is in a high im pedance-m ode.
1.2.1 FR EQ -G EN
Since the FSK -signal shall be program m able in steps of 150H z, and the C K SY S clock-frequency is 5.5296M H z the follow ing structure is used for frequency generation: The SC -C LK is defined to be 16 tim es the center-frequency of the bandpass filters. For generating the FSK or M IX ER - frequency, Fsynth gets divided by 16 for generation of proper D A C input signals. This m eans for both synthesisers the frequency steps are 2400H z. To get a resolution of 2400H z a division by 2304 has to be done by subtraction of 2304 w henever the contents of the SU M -R EG exceeds 2303. SU B STR = 5529.6kH z / 2.4kH z = 2304 (=> res 2048+256) to be: N m ark = 16*Fm ark / 2.4kH z To cover the w anted frequency-range w ith a 9 bit w ord, a fixed num ber of 426 is added. M R K -R EG N m ark = M R K -R EG +426 Fout Fm ark m in 0 426 1022.4kH z 63.9kH z m ax 511 937 2248.8kH z 140.55kH z AS5501 / AS5502 M ultim ode Pow erline M odem D ata Sheet R ev A, M ay 2000 Page 9/25 A D D ER SU M -R EG & s q r 256 res2304 C K SY S 5.5296M 10N Fout FSYN TH
To establish the frequency m odulation, the output of the m ark/space up/dow n-counter gets added to N m ark. There has to be a sm ooth frequency-change from m ark to space and from space to m ark w ithin half the bit-tim e w ith 3 interm ediate frequencies. B D 1 B D 2 Fspace-Fm ark B aud-R ate (C K TX ) M /S-U D C B D clk (U D C -C LK ) 0 0 600H z 600H z 0,1,2,3,4 4800H z 1 0 1200H z 1200H z 0,2,4,6,8 9600H z 0 1 600H z 1200H z 0,1,2,3,4 9600H z 1 1 1200H z 2400H z 0,2,4,6,8 19200H z Exam ple w ith M R K -R EG =8 => Fm ark=81.75kH z; B D 1,2=0 => dF=B R ate=600H z: 545 546 547 548 549 548 547 546 545 B D R *8 TX D (H =m ark) N Fsynth / 16 81.75 81.90(kH z) 82.05 82.20 82.35 82.20 82.05 81.75 81.90 (L=space) In receive-m ode(TxEn=1), a constant num ber N m ix defined by B D 1 gets added to N m ark instead of the output of the M /S-U D C . This gives a constant frequency w hich is used as M ixer-frequency to fold the FSK -signal dow n to 2.7kH z or 5.4kH z. A ccording to the m ixer-frequency the IF-SC -C LK is defined by the tim ing-block (see 1.1.3). B D 1 B D 2 IFcenter IFbandw IF-SC -C LK N m ix B D clk (U D C -C LK ) 0 X 2700H z 1200H z 57.6kH z 20 4800H z 1 X 5400H z 2400H z 115.2kH z 40 9600H z The second frequency-synthesiser w hich is a sim ilar structure as described for generating the FSK -frequencies, is generating the target-frequency for the SC C LK -PLL. To get no disturbing com ponents, the phase-jitter of the synthesiser has to be reduced by the PLL. There is a capacitor needed as external low -pass filter, to define the frequency response of the PLL-loop. To generate the right target-frequency, one half of m odulation-depth w hich is a factor of 2 or 4 dependent on B D 1 has to be added to N m ark. Since the center-frequency is a very critical param eter, there is a possibility im plem ented for adjustm ent by w afersort-trim . B D 1 B D 2 Fspace-Fm ark (Fcenter-Fm ark)/150H z N pll
0 X 600H z 2 M R K _R EG + 426 + Itrim + 2
1 X 1200H z 4 M R K _R EG + 426 + Itrim + 4
(Itrim =0 ... 3 defined at w afer-sort) AS5501 / AS5502 M ultim ode Pow erline M odem D ata Sheet R ev A, M ay 2000 Page 10/25
1.2.2 TX -B PF
The staircase w aveform generated by the FG -D A C in com bination w ith the divider by 16 has to be filtered by an anti-aliasing filter because the SC -Filter clock is not synchronous to the FSK -signal. There is a 6th order bandpass filter, w hich is also used as receive-filter in receive-m ode, im plem ented to reduce the FSK -spectrum . The filter-clock gets canceled by a sm oothing filter at the end of this filter-chain. B oth, A A F and SM F w ill be designed in a w ay to m ove their corner-frequencies according to the frequency-band program m ation. W ith the help of the resonator built w ith the transform er and attached capacitor, the unw anted frequencies (SC -clk, harm onics) are attenuated so that the signal spectrum at the transform er-output passes the follow ing specification [dB uV ] 10k 100k 1M 10M A : m ax 56dB uV @ 150kH z A B C U nw anted Frequency C om ponents Lim itations (avg. m easurem ent) B : m ax 46dbuV >500kH z C : m ax 50dB uV >5M H z
1.2.3 O utput-Stage
A S5502: The output stage is designed to am plify the FSK -signal by a factor of 7 w ith the help of an external buffer-stage to 14V pp. The transfer from the 5V circuitry (asic) to the 24V buffer-structure is done by current-source outputs. The on-chip resistor-netw ork is done in a w ay to shift the D C -operating point from 2.5V (on chip) to 12V (ext. buffer). W ith this output-voltage a transform er w ith a ratio of 2.5:1 can be used (V Lm ax=2V rm s). The buffer gives a very low im pedance w hich is needed to m odulate the pow er-line (Line-im pedance: 5 .. 150ohm ). A S5501 is available for 12V buffer-supply - am plification-factor: 3.5 instead of 7.0 - buffer D C -operating point: 6V instead of 12V AS5501 / AS5502 M ultim ode Pow erline M odem D ata Sheet R ev A, M ay 2000 Page 11/25 C pll A V SS A FC F 10nF
W ith the bias-current outputs M 1M and P1M the transistors T5 and T6 get sw itched on and the driver stage is activated. The TxO ut1,2 output-currents are in the range of 3m A w ith com plem entary A C -com ponents. For stability-reasons it is needed to place a capacitor of 150pF from node V X to V SS. The circuit w ith T1-T4 is a unity gain buffer structure. The transform er w ith attached capacitor C r gives a resonator for the used frequency-band. W ith the show n test-circuit, the harm onic distortion has to be w ithin the follow ing lim its w ith a pow er-line load of (5ohm s+50uH ) // 50ohm s: ratio to the fundam ental 2nd H arm . m in. 70dB 3rd H arm . m in. 75dB higher H arm . m in. 80dB In receive-m ode, w hen the bias-currents are turned off, the base of the tw o output-transistors are forced by resistors of 100k (R x) to 0V and V buf respectively to guarantee high im pedance of the buffer. The current of the pins TxO ut1,2 is 0 (V X is floating). Since the receiver-A G C is reacting on signal levels at the R X B PF-filter output, high outband noise-com ponents could give clipping in the first stages of the receiver path. To avoid this, aa attenuation of 16dB w ith R 2, R 3, C 3 is realized. (M onochrom atic N oise M easurem ent: O utband-noise w ith 0dB V @ line w . 80% A M (1kH z) => 12.8V pp after transform er; => 2.0V pp at pin R X IN ; ) The resistors R 1, R 2, R 3 are calculated to have a D C -voltages of V buf/2 at node V out and 2.5V at node R X IN . A n external diode for protection against high positive voltages is needed at V out (Pin TX FB ). AS5501 / AS5502 M ultim ode Pow erline M odem D ata Sheet R ev A, M ay 2000 Page 12/25 B C 547 B C 557 B C 557 B C 557 2k7 18 1u 0.47u 2.5:1 100 300 150p 2k7 B D 140 B D 139 B D 139 B D 140 TXO U T2 TXO U T1 TXFB P1M M 1M 24V R XIN 13.3k 10k 3k330p 24V 24V R 3 R 2 R 1 C 3 C 1 C r R B R B (R B , R 1, R 2, R 3, C 3 has to be adjusted for 12V VB U F version.) T2 T4 R x 100k R x 100k 24V C r has to be adjusted to proper Fcenter. VX Vout R x 100k LIN E3k 300 6u8 C 2 24V
1.3 R E C E IV E R
The receiver consists of the follow ing blocks: B PF(R X ,TX com m on), M IX ER , C A R D ET, IF-B PF, D EM O D , D A TA FIL and C K R -G EN A A F B PFa & A G C & A G C & A G C SM F W C O M P A C G D EB O U N C ER & U D C LO G IC B PFb B PFc R X O W C O M P D EB O U N C ER C D analog m ixer digital m ixer B PF C A R D ET M IXER IF-A A F IF-B PFa IF-SM F IFI IFO IF-B PFb IF-B PFc IF-B PF Fm ixer Fin C O M P Per-C ount D A C D atLPa D atLPb C O M P R X D D EM O D & D A TA FIL D PLL m ux C LR /T C K TX txen B D 1 B D 1,2 B D 1,2 C K R -G EN SC -C LK IF-SC C LK IF-SC C LK m uxasyn D FO D PLL-IN FSK _ZC TEST_D 5 A G C R X IN R X B U F LPF G =0.66 AS5501 / AS5502 M ultim ode Pow erline M odem D ata Sheet R ev A, M ay 2000 Page 13/25
The received signal gets filtered by the B A N D PA SS filter. A n A G C -function is im plem ented in this filter, to have im proved perform ance over a w ide range of input signal am plitude. The filtered signal gets transferred to a low frequency band by the use of an M IX ER -C IR C U IT so that the frequency-band can be further reduced by an additional IF_B A N D PA SS. The IF-filter output-signal gets D EM O D U LA TED , FILTER ED and SY N C H R O N IZED to a receive-clock. In receive m ode the C LO C K -R EC O V ER Y circuit is generating the receive-clock locked to the R X -data edges. The input signal gets com pared w ith a fixed C A R R IER D ETEC T threshold to get valid R X -data to be further processed by the connected C PU only.
1.3.1 R X B PF
The bandpass-filter elim inates the frequency com ponents w hich are not of interest. The B andw idth is program m able in 3 steps w ith the control-bits R X B W 1 and R X B W 2. R X B W 1 R X B W 2 B W /Fcenter B W @ 72.00kH z B W @ 82.05kH z B W @ 132.45kH z The center-frequency of the filter is defined by the SC -C lock-Frequency (M R K -R EG and the bits B D 1,2) in steps of 150H z. (See paragraph 1.2.1 FR EG _G EN ). Frequency-R esponse w ith R X B W 1=1, R X B W 2=0: Fin / Fcenter typ. rel. G ain 0.67 -45dB 0.98 -3dB 0.99 0.0dB 1 reference 1.01 0.0db 1.02 -3dB 1.5 -45dB A s already m entioned in the transm itter description, the A A F and SM F of the bandpass-filter are tuned according to the SC -C lock and therefore to the B PF-centerfrequency. A n additional attenuation of the m ains-frequency (50H z ..) is not needed because of the external coupling w hich is already a very good filter for that. input-pin R X IN gets buffered and low pass-filtered by the R X B U F w ith a fixed gain of 0.66. (M ax. input level 14V pp@ transform er =>2.2V pp@ R xin =>1.5V pp@ FilterInput) The gain of the SC -B PF is controlled by the A G C loop to keep the filter-output R X O constant at 1.0V p for a w ide range of input-dynam ic. In total there is a variable gain from -3.6 to +41.4dB in steps of 1dB . V (Line) V (V out) V (R xIn) V (R X O ) The w indow -com parator threshold for the A G C -control is set to 1.02V +/-12% . The A G C -U D C w ill be clocked by 8*Fbaud w hich gives a m ax. settling tim e of 9.4m s at 600bps. AS5501 / AS5502 M ultim ode Pow erline M odem D ata Sheet R ev A, M ay 2000 Page 14/25
1.3.2 C A R D ET
The carrier detect circuit is com paring the R X B PF-output against a constant threshold. The carrier detect has to go active w hen the R X IN input-voltage exceeds 5m V p. V (Line) V (V out) V (R xIn) V (R X O ) 8.9m V rm s 31.5m V p 5.0m V p 593m V p The carrier detect O N -tim e can be choosen by D 8 of the TST-R eg. The O FF-tim e is defined by the A G C -stage settling-tim e of m ax. 45/(8*Fbaud) plus 12 cycles of Fbaud*64. Fbaud=600 Fbaud=1200 Fbaud=2400 T (C D -O N ) w ith TST.D 8=L 16.7m s 8.33m s 4.17m s T (C D -O N ) w ith TST.D 8=H 8.33m s 4.17m s 2.08m s
1.3.3 M IX ER
There are tw o m ixer stages im plem ented. The analog m ixer (default) consists of an unity-gain am plifier-stage w hich is sw itched to inverting or non-inverting m ode by the m ixer-reference clock. The digital m ixer, enabled w ith bit TEST_D 5=H , consist of a com parator-stage w ith hysteresis of appr. 50m V w ith w hich the B PF-output gets transferred to digital. This signal gets com bined w ith the m ixer reference clock by an EX O R -gate. For the tw o different m odulation-depths, different interm ediate frequencies are generated by proper generation of the reference-frequency. (see paragr.: 1.2.1 FR EG -G EN ) B D 1 Fspace-Fm ark IF 0 600H z 2700H z 1 1200H z 5400H z
1.3.4 IF-B PF
The m ixer-output is fed to the input of the interm ediate-frequency filter. A ccording to the tw o different IF defined by B D 1, this B PF is program m ed to these frequencies by the IF-SC -C LO C K generator. B D 1 Fcenter B and W idth 0 2700H z 1200H z 1 5400H z 2400H z The corner-frequencies of the A A F and the SM F are controlled accordingly. The SC -filter is a 6th order filter w ith the follow ing characteristics: Fin / Fcenter Fc=2.7k Fc=5.4k typ. rel. G ain 0.45 1200H z 2400H z -45dB 0.78 2100H z 4200H z -3dB 1.22 3300H z 6600H z -3dB 2.14 5800H z 11600H z -45dB
1.3.5 D EM O D & D A TA FIL
The output of the IF-B PF gets transferred to digital by an com parator w ith pos. A C -feedback V hyst~10m V . The periode-tim e is then m easured by a counter w hich gets set to a proper starting point, so that at the end of a m easurem ent-periode the frequency-delta is represented by a 4 bit w ord. This digital inform ation is transform ed again into analog by an D A C w hich is included to the input-stage of the SC -D atafilter. N o A A F is needed because the D A C is synchronised w ith the filter. The unity-gain datafilter can be program m ed to three different corner-frequencies according to the B audrates of 600,1200 and 2400H z. AS5501 / AS5502 M ultim ode Pow erline M odem D ata Sheet R ev A, M ay 2000 Page 15/25
Fin/Fbaud typ. G ain 0.75 -3.0dB 1.3 -25dB A com parator w ith hysteresis of appr. 200m V and adjustable (bias-distortion w afer-sort-trim ) absolute reference is converting the D ataFilter-output to R X D A (asynchronous receive data).
1.3.6 B it Error R ate
The system specification of B ER is the follow ing: Param eter C ondition m in typ m ax B ER 1 B it Error R ate w ith M inim um Input Level W hite N oise w ith S/N =13dB R X L = 1.5m V rm s 5*10-5 10-3 B ER 3 B it Error R ate w ith M axim um Input Level W hite N oise w ith S/N =25dB R X L = 1.5V rm s 10-7 10-3 B ER 4 B it Error R ate w ith M edium Input Level W hite N oise w ith S/N =13dB R X L = 600m V rm s 10-6 10-3 B ER 5 B it Error R ate w ith Im pulsive N oise N oise: 5V pp rect., 100H z, D C =10% , Trise/fall=10us; R X L=90m V rm s 10-3 B ER 6 B it Error R ate w ith M odulated Sinusoidal N oise N oise: sine carrier w . 80% A M ; Fm od=1kH z, special S/N -M ask R X L=1.5V rm s 10-3
1.3.7 C K R -G EN
There is a digital pll for receive-clock reconstruction. The signal R X D A (async. R X D ) gets synchronised by this clock w hich then gives the synchronous receive data signal R X D . A m ultiplexer is used to select R X D A or R X D to be transferred to the pin R X D by the use of a control bit "A SY N ". The signal R X D A is used to verify the M ixer and D ataFil-structure. A second m ultiplexer selects C K R X or C K TX to be transferred to pin C LK R /T by the use of control signal "TxEn". In synchronouse-m ode R X D is valid at the high going edge of C K R /T.
1.4 T E ST -M U X
A test-input pin, a test-output pin w ith attached buffer and m ultiplexers are used to have access to som e internal nodes for testing. To have access to internal nodes of the receiver in norm al receive operation, the bit TEST_D 6 can be set to H for avoiding TST_IN function. The asic is forced to one of these test-m odes by setting the control-bits TEST1 and TEST2. T est1 T est2 M ux-State T ST -IN T ST -O U T C K SY S R eset-D elay T X -T im eout 0 0 0 bypass tim er V R EF M C LK /2 300m s 3sec 1 0 1 IFI IFO FSK _ZC 300m s 3sec 0 1 2 TX I R X O SC -C LK 1.17m s 11.7m s 1 1 3 D PLL-IN D FO Fm ixer 1.17m s 11.7m s M ux-State 0 (N orm al O peration): In norm al operation the test-m uxes are in position 0. In this configuration, the reference voltage V R EF (2.5V ) is present at pin TST-O U T. In this m ode the reset and TX -tim eout counter are bypassed w ith TST-IN set to H . AS5501 / AS5502 M ultim ode Pow erline M odem D ata Sheet R ev A, M ay 2000 Page 16/25
M ux-State 1(IF-Test): In this m ode the IFB PF can be m easured by forcing the IFI via pin TST-IN and m easuring IFO via pin TST-O U T. W ith pin C K SY S the FSK -ZC signal can be m easured. M ux-State 2 (TX PA TH / R X O ): In this m ode the TX PA TH can be m easured by forcing TX I via pin TST-IN and m easuring the TX -O utput-Stage output. The SC -C LK can be m easured via pin C K SY S. The receiver bandpass filter can be m easured by forcing R X IN and m easuring TST-O U T (R X O ). M ux-State 3 (D PLL / D A TA FIL): In this m ode the input of the R X -D PLL can be forced by TST-IN for digital verification of this block. Further the output of the data LP-filter can be m easured at TST-O U T. The M IX ER - PLL output can be m easured via pin C K SY S. TX Tim eout / R ES-D elay Test-M ode: W ith bit "Test2" set to 1 the TX -tim eout (3sec) and the R ES-D elay (300m s) gets reduced by a factor of 256 for production test. A SY N Test-M ode: The contol-bit "A SY N " is used for global verification of the receiver-block and especially for verification of the M IX ER and the D ataFilter by m easuring the R X D A -jitter (isochronous-distortion). TST-O U T opM U X V R EF IFO R X OM U X TST-IN IFI TX I 1 1 nc.0 D PLL-IN3 op D F O
1.5 Supply and A nalog G round
There are tw o different pairs of supply pins, one for analog (A V SS,A V D D ) and one for digital (D V SS, D V D D ). The tw o V SS-pins have to be at the sam e level to avoid substrate-current. The tw o V D D -pins should not differ m ore than 0.25V . The reason for splitting the supply lines is to avoid noise from the digital circuit injected to the analog section. The analog-ground is generated by resistive division of the supply-voltage to A V D D /2. Since the SC -clock is w orking in the range of >1M H z, an external capacitor of 1uF is needed to decouple the A G N D to A V SS. There has to be sufficient decoupling from A V D D to A V SS and from D V D D to D V SS separately. U sually a com bination of a 10uF tantal and 100nF ceram ic-capacitor is used dependent on the supply structure. A V SS A G N D A V D D D V D D D V SS 1uF 100n 10uF 10uF 100nF +5V +5V AS5501 / AS5502 M ultim ode Pow erline M odem D ata Sheet R ev A, M ay 2000 Page 17/25
- Package and M arking Package: SO IC 28 M arking: Y Y W W IZZ Y Y W W IZZ (date code) A S5501 A S5502 (A S-num ber dependent on version) N C 52FL N C 52FH (coded default setup) The default setup coded in the follow ing w ay, gets printed as 3rt m arking line: B onding option: 1st character ... "N " for not locked; "L" for locked version (pad LO C K bonded to V SS) (O ption "N ot Locked": A ll control registers are accessable via SER IF) (O ption "Locked": O nly contr. register TEST is accessable via SER IF) 6th character ..."H " for 24V buffer supply (standard version); " L" for 12V buffer supply; M ask options: C haracter hex. rep. of reg.-bits standard version bits C har 2nd M R K 8-5 '1100' C 3rd M R K 4-1 '0101' 5 4th PW D , M M V , ZC EN , R X B W 2 '0010' 2 5th R X B W 1, B D 2, B D 1, M R K 9 '1111' F 3. Pinlist PIN # N am e T ype Function
1 A V D D supply +5V supply pin for analog section
2 ZC inp. w . pd m ains zero-cross input for transm ission synchronisation 3 R ES-TH ana. inp. reset threshold adjust input 4 A FC F ana. i/o com pensation pin for PLL-loop 5 TST-O U T ana. outp. test function output pin (V R EF in norm al m ode) 6 TST-IN ana. inp. test function input pin 7 A G N D ana. I/O analog ground pin for external decoupling capacitor 8 R X IN ana. inp. receiver input pin 9 TxFb ana. inp. transm ission feedback / receive input 10 M 1M ana. outp. m inus 1m A bias current for TX -buffer stage AS5501 / AS5502 M ultim ode Pow erline M odem D ata Sheet R ev A, M ay 2000 Page 18/25 A M S-Logo YYW W IZZ A S5501(2) N C 52FL(H ) A VD D R esTh TstO ut TxFb R XIN P1M ZC A FC F TstIn A G N D M 1M TxO ut2 TxO ut1 A VSS D VSS M C LK A 0/C S SC Lk SD iIn SD -O ut C kSys R ESN TXD TxEnC LR /T C DR XD D VD D
11 P1M ana. outp. plus 1m A bias current for TX -buffer stage 12 TxO ut1 ana. outp. TX output 1 13 TxO ut2 ana. outp. TX output 2
14 A V SS supply 0V supply pin for analog section
15 D V SS supply 0V supply pin for digital section
16 M C LK dig. inp. m aster clock input (11.0592 M H z) 17 A 0/C S dig. inp. serial bus control signal w ith pull up 18 SC LK dig. inp. serial bus clock w ith pull up 19 SD -IN dig. inp. serial bus data input w ith pull up 20 SD -O U T dig. outp. serial bus data open drain output w ith pull up 21 C K SY S dig. outp. system clock output (5.5296M H z) 22 R ESN dig. odo. reset open drain output active at low supply 23 TX D dig. inp. transm it data input 24 TxEn dig. inp. transm it-m ode txen=0 / receive-m ode txen=1 25 C D dig. outp. carrier detect output 26 C LR /T dig. outp. receive / transm it clock output 27 R X D dig. outp. receive data output
28 D V D D supply +5V supply for digital section
- A B SO L U T E M A X IM U M R A T IN G S M ax. Supply V oltage M ax. Input V oltage M ax. C urrent forced to any input or output except pin "P1M " M ax. C urrent forced to pin "P1M " M ax. Pow er D issipation Storage Tem perature R ange H um idity N oncondensating ESD general lim it (R =1.5kO hm , C =100pF, 3 pulses each pol.) Lead Tem perature (m ax. 10sec) -100m A ... +25m A 700m W -55 deg C ... 150 deg C 5% ... 95% +/- 1kV m ax 300 deg C 5. O PE R A T IN G C O N D IT IO N S Param eter m in typ m ax unit O perating Supply V oltage 4.7 5 5.3 V O perating T em perature R ange -25 25 70 deg C 6. T E ST SPE C IFIC A T IO N
6.1 T est C onditions
Tem perature: -25, 25, 70 deg C . Signals: C lock: 11.0592M H z forced to pin M C LK ; M odes: "default": condition after pow er-up/reset (see paragr. 1.1) "M 72": M R K = 50, B D 1=H , B D 2=L, R xB w 1=L, R xB w 2=L "M 82": M R K =119, B D 1=L, B D 2=L, R xB w 1=H , R xB w 2=L "M 132": M R K =453, B D 1=H , B D 2=H , R xB w 1=H , R xB w 2=L "R xM ode": TxEn = H ; "TxM ode": M M V =H , TxEn=L (disable tim eout) AS5501 / AS5502 M ultim ode Pow erline M odem D ata Sheet R ev A, M ay 2000 Page 19/25
6.2 Pow er C onsum ption T est
V D D =5.3V m in typ m ax conditions I1(D V D D ) - - 3m A norm al transm ission sequ. I2(A V D D ) - - 36m A norm al transm ission sequ. I3(A V D D ) - - 32m A R xM ode, M 82, (receive) I4(A V D D ) - - 1m A PW D =H
6.3 Input C haracteristics
Z C (Schm itt-Trigger w ith pull dow n) m in typ m ax C ondition IIL (vin=0V ) -10uA 0 10uA - IIH (vin=V D D ) 80uA 150uA 250uA - V IL - - 1.1V V D D =5.0V V IH 3.9V - - V D D =5.0V V hyst (not tested at production test) 1.2V - 2.5V V D D =5.0V R E S-T H (see paragr. 1.1) m in typ m ax C ondition IIL (vin=0V ) -15uA -23uA -33uA V D D =5.0V IIH (vin=V D D ) 30uA 45uA 65uA V D D =5.0V T ST -IN (anal. buffer input) m in typ m ax C ondition I pull-dow n (vin=vdd) 80uA 150uA 250uA nor. M ode, TM 3 T xFb (resistive divider) m in typ m ax C ondition R IN (vin=0V ... V D D ) 45k 82k 148k R xM ode, V 24 R IN (vin=0V ... V D D ) 25k 46k 83k R xM ode, V 12 R X IN (receive input buffer) m in typ m ax C ondition R IN (vin=0V ... V D D ) 38k 68k 122k R xM ode M C L K , A 0/C S, SPI_C K , SPI-IN , T X D , T xE n (dig. std. input) m in typ m ax C ondition I pull-up (vin=0V ) 80uA 150uA 250uA A 0/C S, SPIC K , SPI-IN Ileak (vin=0..vdd) -1uA - 1uA M C LK , TX D , TX EN V IL - - 0.3*V dd - V IH 0.7*V dd - - - L O C K , V 12N m in typ m ax C ondition I pull-up (vin=0V ) 10uA 20uA 35uA at w afer-sort only AS5501 / AS5502 M ultim ode Pow erline M odem D ata Sheet R ev A, M ay 2000 Page 20/25
6.4 O utput C haracteristics
A FC F (PLL com pensation) typ. Load m in typ m ax C ondition IO U T (V afcf=0..5V , V dd=5V ) 1uF(no res) -200uA - 200uA (not tested at product. test) T ST -O U T (ana. buffer output) m ax. Load m in typ m ax C ondition IO U T (V tstout=0V ) 10k//50pF 400uA 820uA 1.6m A V dd=5V V R E F (in norm al m ode) (Iout= +/-250uA ) 10k//50pF 2,45 2,5 2,55 V dd= A G N D (resistive divider) typ. Load m in typ m ax C ondition V O U T 1uF(no res) 2.4 2.5 2.6 V D D =5.0V M 1M (current sink to V SS) Load m in typ m ax C ondition IO L (V m =12V , 24V ) (see 1.2.3) -0.5m A -0.75m A -1m A TxM ode Ileak (V m =0...24V ) - - 10uA R xM ode P1M (current source) Load m in typ m ax C ondition IO H (V m =1V ) (see 1.2.3) 0.5m A 0.75m A 1m A TxM ode V O L (Iout=1m A ) - - 0.5V R xM ode T xO ut1, T xO ut2 (current sink to V SS) Load m in typ m ax C ondition Ileak (V in=0...24V ) - - 10uA R xM ode C K SY S, C L R /T , C D , R X D (dig. std. output) m in typ m ax C ondition V O L (Iout=4m A ) - 0.25V 0.5V - V O H (Iout=-4m A ) V D D -0.5V V D D -0.25V - - SPI-O U T , R E S (dig. open drain output) m in typ m ax C ondition V O L (Iout = 4m A ) - 0.25V 0.5V - IL eak (V out = 0...V D D ) -10uA - 10uA R ES-pin I pull-up (V =0V ) 80uA 150uA 250uA SPI-O U T pin
6.5 R eset -T est
V por_off_1 (res-th=V D D ) 2.4V 2.5V 2.6V TSTIN =V D D V por_off_2 (res-th=floating) 3.65V 3.75V 3.90V TSTIN =V D D V por_hyst (res-th=floating) 50m V 100m V 150m V TSTIN =V D D V por_on_pw d (res-th=floating) 3.50V 3.65V 3.85V TSTIN =V D D , PW D =H V por_off_3 (res-th=V SS) 4.8V 5.0V 5.2V TSTIN =V D D R eset off-delay 1.1m s 0.3/256s 1.2m s TestM ode3 (pattern test) AS5501 / AS5502 M ultim ode Pow erline M odem D ata Sheet R ev A, M ay 2000 Page 21/25
6.6 C K T X -T est (pattern test)
Z C -T rigger T est included ! m in typ m ax C ondition Freq1(C L R /T ) - 600H z - TxM ode, B D 1=L, B D 2=L Freq2(C L R /T ) - 1200H z - TxM ode, B D 1=H , B D 2=L Freq3(C L R /T ) - 1200H z - TxM ode, B D 1=L, B D 2=H Freq4(C L R /T ) - 2400H z - TxM ode, default
6.7 T X -T im eout T est
TestM ode3: 3sec tim eout divided by 256 m in typ m ax C ondition
6.8 PL L -T est (SC C L K )
C afcf = 10nF Tsettle=5m s m in typ m ax C ondition Freq1(C K SY S) -0.8% 1.032M H z +0.8% TestM ode2, M R K 1-9=0, B D 1=L Freq2(C K SY S) -0.8% 2.263M H z +0.8% TestM ode2, M R K 1-9=511, B D 1=H Freq3(C K SY S) -0.8% 1.850M H z +0.8% TestM ode2, M R K 1-9=341, B D 1=L Freq4(C K SY S) -0.8% 1.445M H z +0.8% TestM ode2, M R K 1-9=170, B D 1=H Phase Jitter - - +/-50ns TestM ode2, M 82
6.9 FSY N T H -T est (FM IX E R )
Freq1(C K SY S) -0.5% 66.9kH z +0.5% TestM ode3, M R K 1-9=0, B D 1=L Freq2(C K SY S) -0.5% 146.55kH z +0.5% TestM ode3, M R K 1-9=511, B D 1=H Freq3(C K SY S) -0.5% 118.05kH z +0.5% TestM ode3, M R K 1-9=341, B D 1=L Freq4(C K SY S) -0.5% 95.4kH z +0.5% TestM ode3, M R K 1-9=170, B D 1=H Phase Jitter - - +/-100ns TestM ode3, M 82
6.10 T X O U T -T est
Testcircuit: (sim ilar to the circuit show n on page 12) V D D =5.0V m in typ m ax C ondition Freq1(V out) -0.05% 81.75kH z +0.05% TxM ode, M 82, TX D =H Freq2(V out) -0.05% 82.35kH z +0.05% TxM ode, M 82, TX D =L Freq3(V out) -0.05% 82.95kH z +0.05% TxM ode, M 82,TX D =L,B D 1=H Freq4(V out) -0.05% 63.90kH z +0.05% TxM ode, M R K 1-9=0, TX D =H Freq5(V out) -0.05% 140.55kH z +0.05% TxM ode, M R K 1-9=511, TX D =H Freq6(V out) -0.05% 115.05kH z +0.05% TxM ode, M R K 1-9=341, TX D =H Freq7(V out) -0.05% 89.40kH z +0.05% TxM ode, M R K 1-9=170, TX D =H V ppV 24(V out) 12V pp 13.0V pp 14V pp TxM ode, M 82,B D 1=H ,TX D =L/H V ppV 12(V out) 6.0V pp 6.5V pp 7.0V pp TxM ode, M 82,B D 1=H ,TX D =L/H AS5501 / AS5502 M ultim ode Pow erline M odem D ata Sheet R ev A, M ay 2000 Page 22/25
H D 2(V out) - - -70dB TxM ode, M 82, TX D =L H D 3(V out) - - -70dB TxM ode, M 82, TX D =L PSR R 1(V out) 15dB - - TxM ode, M 82, V D D =200m V pp, 50H z not tested, guaranteed by design PSR R 2(V out) 35dB - - TxM ode,M 82, V B U F=200m V pp, 50H z not tested, guaranteed by design
6.11 R X A G C and FIL T E R T est
V D D = 5.0V , TxEn=H , TestM ode2 input pin: R X IN , m easured pin: TST-O U T m in typ m ax C ondition Industrial M ode 72kH z dF=1.2kH z B d=1.2k B W =6kH z abs. G ain @ 72kH z, 100m V rm s 0.86V p 1.0V p 1.15V p M 72 abs. G ain @ 72kH z, 10m V rm s 0.86V p 1.0V p 1.15V p M 72 abs. G ain @ 72kH z, 3m V rm s 380m V p 500m V p 660m V p M 72 rel. G ain @ 69kH z -4dB -3.0dB -2dB M 72 rel. G ain @ 75kH z -4dB -3.0dB -2dB M 72 rel. G ain @ 42kH z - - -45dB M 72 rel. G ain @ 124kH z - - -45dB M 72 D om estic M ode 82.05kH z dF=600H z B d=600 B W =3k rel. G ain @ 80.55kH z -4dB -3.0dB -2dB M 82 rel. G ain @ 83.55kH z -4dB -3.0dB -2dB M 82 rel. G ain @ 55kH z - - -45dB M 82 rel. G ain @ 123kH z - - -45dB M 82 H om e A utom ation 132.45kH z dF=1.2kH z B d=2.4k B W =4.8kH z rel. G ain @ 130.05kH z -4dB -3.0dB -2dB M 132 rel. G ain @ 134.85kH z -4.5dB -3.0dB -2dB M 132 rel. G ain @ 88kH z - - -45dB M 132 rel. G ain @ 198kH z - - -45dB M 132 AS5501 / AS5502 M ultim ode Pow erline M odem D ata Sheet R ev A, M ay 2000 Page 23/25
6.12 IF-FIL T E R T est
V D D =5.0V input: TST_IN , output: TST_O U T m in typ m ax C ondition rel. G ain @ 1.2kH z - - -45dB B D 1=L, TestM ode1 rel. G ain @ 2.1kH z -4dB -3.0dB -2dB B D 1=L, TestM ode1 rel. G ain @ 3.3kH z -4dB -3.0dB -2dB B D 1=L, TestM ode1 rel. G ain @ 5.8kH z - - -45dB B D 1=L, TestM ode1 rel. G ain @ 2.4kH z - - -45dB B D 1=H , TestM ode1 rel. G ain @ 4.2kH z -4dB -3.0dB -2dB B D 1=H , TestM ode1 rel. G ain @ 6.6kH z -4dB -3.0dB -2dB B D 1=H , TestM ode1 rel. G ain @ 11.6kH z - - -45dB B D 1=H , TestM ode1
6.13 R X D -D istortion T est
A fsk-signal w ith a bit-stream of 010101... w ill be forced to the TxFb-Pin. The asynchronous R X D -signal (A SY N =H ) w ill be m easured. This test w ill indirectly cover the B it Error R ate requirem ents. V D D =5.0V , A SY N =H 72kH z, dF=1200H z, 1200baud input: R X IN , output: R X D m in typ m ax C ondition B ias D istortion @ V in=1.5V rm s - - 8% M 72 Isochr. D istortion @ V in=1.5V rm s - - 12% M 72 B ias D istortion @ V in=3.0m V rm s - - 8% M 72 Isochr. D istortion @ V in=3.0m V rm s - - 18% M 72 82.05kH z, dF=600H z, 600baud input: R X IN , output: R X D B ias D istortion @ V in=1.5V rm s - - 8% M 82 Isochr. D istortion @ V in=1.5V rm s - - 14% M 82 B ias D istortion @ V in=3.0m V rm s - - 10% M 82 Isochr. D istortion @ V in=3.0m V rm s - - 25% M 82 132.45kH z, dF=1200H z, 2400baud input: R X IN , output: R X D B ias D istortion @ V in=1.5V rm s - - 12% M 132 Isochr. D istortion @ V in=1.5V rm s - - 22% M 132 B ias D istortion @ V in=3.0m V rm s - - 14% M 132 Isochr. D istortion @ V in=3.0m V rm s - - 30% M 132 Isochr. D istortion @ V in=3.0m V rm s w ill not be tested at low tem perature ! AS5501 / AS5502 M ultim ode Pow erline M odem D ata Sheet R ev A, M ay 2000 Page 24/25
6.14 C arrier D etect - T est
V D D =5.0V , input: R X IN , output: C D m in typ m ax C ondition V IN _on (C D =H , Fin=82.05kH z) - - 4.9m V eff M 82 V IN _off (C D =L, Fin=82.05kH z) 2.9m V eff - - M 82 T release1 (C D =>L @ V in=1.5V rm s, 82.05kH z) 8.0m s - 9.0m s M 82 T release2 (C D =>H @ V in=1.5V rm s, 82.05kH z) 4.0m s - 5.0m s M 82, B D 1,2=H ,L T release3 (C D =>H @ V in=1.5V rm s, 82.05kH z) 1.9m s - 2.5m s M 82, B D 1,2=H ,H
6.15 C K R X - T est (pattern test)
The D PLL of the R x-clock recovery circuit w ill be tested by a digital pattern defined during design-phase. In Test-M ode 3 a certain D PLL-input w ill be supplied by the pin TST-IN . The C LR /T has to recover a m inim um of 20% jitter and a frequency tolerance of +/-1.5% .
6.16 Serial Interface - T est (pattern test)
The serial interface w ill be tested by a digital pattern defined during design-phase. m in typ m ax C ondition T spick 1us - - - T cssu, T cshd 200ns - - - T dsu, T dhd 100ns - - - C opyright 2000, Austria M ikro System e International AG , SchloB Prem statten, 8141 U nterprem statten, Austria.Tel. +43- (0)3136-500-0, Fax +43-(0)3136-52501, E-M ail info@ am sint.com All rights reserved. N o part of this publication m ay be reproduced, stored in a retrieval system , or transm itted, in any form or by any m eans, w ithout the prior perm ission in w riting by the copyright holder. To the best of its know ledge, Austria M ikro System e International asserts that the inform ation contained in this publication is accurate and correct. AS5501 / AS5502 M ultim ode Pow erline M odem D ata Sheet R ev A, M ay 2000 Page 25/25