AS4LC1M16

AS4LC1M16 AUSTIN | Alldatasheet

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AS4LC1M16 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. REV. 3/97 DS000020 AS4LC1M16 883C

1 MEG x 16 DRAM

AUSTIN SEMICONDUCTOR, INC. 3.3V, EDO PAGE MODE, OPTIONAL EXTENDED REFRESH DRAM PIN ASSIGNMENT (Top View) GENERAL DESCRIPTION The AS4LC1M16 is a randomly accessed solid-state memory containing 16,777,216 bits organized in a x16 con- figuration. The AS4LC1M16 has both BYTE WRITE and WORD WRITE access cycles via two ?C?A/S pins (?C?A?S/L and ?C?A?S?H). These function in a similar manner to a single ?C?AS of other DRAMs in that either ?C?A?S/L or ?C?A?S?H will generate AVAILABLE AS MILITARY SPECIFICATIONS

• MIL-STD 883
• SMD Planned

FEATURES

• JEDEC- and industry-standard x16 timing, functions, pinouts and packages
• High-performance CMOS silicon-gate process
• Single +3.3V ±0.3V power supply
• All device pins are TTL-compatible
• Refresh modes: ?R?A/S ONLY, ?C?A/S-BEFORE-?R?A/S (CBR), HIDDEN
• BYTE WRITE access cycles
• 1,024-cycle refresh (10 row-, 10 column-addresses)
• Low power, 0.3mW standby; 180mW active, typical
• Extended Data-Out (EDO) PAGE access cycle
• 5V-tolerant I/Os (5.5V maximum V IH level) OPTIONS MARKING
• Timing 60ns access (Contact Factory) -6 70ns access -7 80ns access -8
• Refresh Rate Standard 16ms period None
• Packages Ceramic SOJ ECJ No. 506 Ceramic Gull Wing ECG No. 604 Ceramic LCC EC No. 213 44/50-Pin SOJ/LCC/Gull Wing 450mil Vcc DQ1 DQ2 DQ3 DQ4 Vcc DQ5 DQ6 DQ7 DQ8 NC NC NC WE RAS NC NC Vcc Vss DQ16 DQ15 DQ14 DQ13 Vss DQ12 DQ11 DQ10 DQ9 NC NC CASL CASH OE Vss KEY TIMING PARAMETERS SPEED tRC tRAC tPC tAA tCAC tCAS -6 105ns 60ns 25ns 30ns 15ns 12ns -7 125ns 70ns 30ns 35ns 20ns 12ns -8 150ns 80ns 40ns 40ns 20ns 20ns an internal ?C?A/S. The AS4LC1M16 ?C?A/S function and timing are deter- mined by the first ?C?A/S (?C?A?S/L or ?C?A?S?H) to transition LOW and the last ?C?A/S to transition back HIGH. Use of only one of the two results in a BYTE WRITE cycle. ?C?A?S/L transitioning LOW selects an access cycle for the lower byte (DQ1-DQ8) and ?C?A?S?H transitioning LOW selects an access cycle for the upper byte (DQ9-DQ16). Each bit is uniquely addressed through the 20 address bits during READ or WRITE cycles. These are entered 10 bits (A0-A9) at a time. ?R?A/S is used to latch the first 10 bits and ?C?A/S the latter 10 bits. The ?C?A/S function also determines whether the cycle will be a refresh cycle (?R?A/S ONLY) or an active cycle (READ, WRITE or READ WRITE) once ?R?A/S goes LOW.

AS4LC1M16 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. REV. 3/97 DS000020 AS4LC1M16 883C AUSTIN SEMICONDUCTOR, INC. PAGE ACCESS PAGE operations allow faster data operations (READ, WRITE or READ-MODIFY-WRITE) within a row-address- defined page boundary. The PAGE cycle is always initiated with a row-address strobed-in by ?R?A/S followed by a col- umn-address strobed-in by ?C?A/S. ?C?A/S may be toggled-in by holding ?R?A/S LOW and strobing-in different column- addresses, thus executing faster memory cycles. Returning ?R?A/S HIGH terminates the PAGE MODE of operation. EDO PAGE MODE The AS4LC1M16 provides EDO PAGE MODE which is an accelerated FAST PAGE MODE cycle. The primary advantage of EDO is the availability of data-out even after ?C?A/S returns HIGH. EDO provides for ?C?A/S precharge time tCP) to occur without the output data going invalid. This elimination of ?C?A/S output control provides for pipeline READs. FAST-PAGE-MODE DRAMs have traditionally turned the output buffers off (High-Z) with the rising edge of ?C?A/S. EDO-PAGE-MODE DRAMs operate similar to FAST-PAGE-MODE DRAMs, except data will remain valid or become valid after ?C?A/S goes HIGH during READs, provided ?R?A/S and ?O/E are held LOW. If ?O/E is pulsed while ?R?A/S and ?C?A/S are LOW, data will toggle from valid data to High-Z and back to the same valid data. If ?O/E is toggled or pulsed after ?C?A/S goes HIGH while ?R?A/S remains LOW, data will transition to and remain High-Z (refer to Figure 1). The ?C?A/S/L and ?C?A/S?H inputs internally generate a ?C?A/S signal functioning in a similar manner to the single ?C?A/S input of other DRAMs. The key difference is each ?C?A/S input ( ?C?A/S/L and ?C?A/S?H ) controls its corresponding 8 DQ inputs during WRITE accesses. ?C?A/S/L controls DQ1 through DQ8 and ?C?A/S?H controls DQ9 through DQ16. The two ?C?A/S controls give the MT4LC1M16E5(S) both BYTE READ and BYTE WRITE cycle capabilities. A logic HIGH on ?W/E dictates READ mode while a logic LOW on ?W/E dictates WRITE mode. During a WRITE cycle, data-in (D) is latched by the falling edge of WE or ?C?A/S (?C?A/S/L or ?C?A/S/H), whichever occurs last. An EARLY WRITE occurs when WE is taken LOW prior to either ?C?A/S falling. A LATE WRITE or READ-MODIFY-WRITE occurs when WE falls after ?C?A/S ( ?C?A/S/L or ?C?A/S/H) was taken LOW. During EARLY WRITE cycles, the data-outputs (Q) will remain High-Z regardless of the state of ?O/E. During LATE WRITE or READ-MODIFY-WRITE cycles, ?O/E must be taken HIGH to disable the data-outputs prior to applying input data. If a LATE WRITE or READ-MODIFY-WRITE is attempted while keeping ?O/E LOW, no write will occur, and the data-outputs will drive read data from the accessed location. The 16 data inputs and 16 data outputs are routed through 16 pins using common I/O. Pin direction is controlled by ?O/E and ?W/E. GENERAL DESCRIPTION (continued) Figure 1 OUTPUT ENABLE AND DISABLE /,/, /,/,/, V V IH IL CASL/CASH V V IH ILRAS V V IH ILADDR /,/, ROW /,/, COLUMN (A) /,/, /,/,/, /,/, COLUMN (B) /,/,/,/, /,/, DON’T CARE UNDEFINED /,/, /,/, V V IH ILOE V V IOH IOL OPENDQ tOD VALID DATA (B)VALID DATA (A) /, COLUMN (C) /,/,/, /,/,/, VALID DATA (A) tOE /,/, VALID DATA (C) COLUMN (D) /,/,/, /,/, VALID DATA (D) tOD tOEHC tOD tOEP tOES The DQs go back to Low-Z if tOES is met. The DQs remain High-Z until the next CAS cycle if tOEHC is met. The DQs remain High-Z until the next CAS cycle if tOEP is met.

AS4LC1M16 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. REV. 3/97 DS000020 AS4LC1M16 883C AUSTIN SEMICONDUCTOR, INC. EDO PAGE MODE (continued) ?W/E can also perform the function of disabling the output drivers under certain conditions, as shown in Figure 2. During an application, if the DQ outputs are wire OR’d, ?O/E must be used to disable idle banks of DRAMs. Alterna- tively, pulsing ?W/E to the idle banks during ?C?A/S HIGH time will also High-Z the outputs. Independent of ?O/E control, the outputs will disable after tOFF, which is referenced from the rising edge of ?R?A/S or ?C?A/S, whichever occurs last. /,/, /,/, V V IH ILCASL/CASH V V IH ILRAS V V IH ILADDR /,/, ROW /,/, COLUMN (A) /,/, /,/,/, DON’T CARE UNDEFINED /,/, /,/, /,/, V V IH ILWE V V IOH IOL OPENDQ /,/,/, /,/, /,/, /,/, /,/, tWPZ The DQs go to High-Z if WE falls, and if tWPZ is met, will remain High-Z until CAS goes LOW with WE HIGH (i.e., until a READ cycle is initiated). V V IH ILOE VALID DATA (B) tWHZ WE may be used to disable the DQs to prepare for input data in an EARLY WRITE cycle. The DQs will remain High-Z until CAS goes LOW with WE HIGH (i.e., until a READ cycle is initiated). tWHZ COLUMN (D) /,/, /,/,/, /,/,/, VALID DATA (A) COLUMN (B) COLUMN (C) INPUT DATA (C) Figure 2 ?????W /////E CONTROL OF DQs

AS4LC1M16 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. REV. 3/97 DS000020 AS4LC1M16 883C AUSTIN SEMICONDUCTOR, INC. BYTE ACCESS CYCLE The BYTE WRITEs and BYTE READs are determined by the use of ?C?A/S/L and ?C?A/S?H. Enabling ?C?A/S/L will select a lower BYTE access (DQ1-DQ8). Enabling ?C?A/S?H will select an upper BYTE access (DQ9-DQ16). Enabling both ?C?A/S/L and ?C?A/S?H selects a WORD WRITE cycle. The AS4LC1M16 may be viewed as two 1 Meg x 8 DRAMs that have common input controls, with the excep- tion of the / ?C?A/S inputs. Figure 3 illustrates the BYTE WRITE and WORD WRITE cycles. Additionally, both bytes must always be of the same mode of operation if both bytes are active. A ?C?A/S precharge must be satisfied prior to changing modes of operation between the upper and lower bytes. For example, an EARLY STORED DATA RAS CASL WE X = NOT EFFECTIVE (DON'T CARE) ADDRESS 1ADDRESS 0 WORD WRITE LOWER BYTE WRITE CASH INPUT DATA X X X X X X X X INPUT DATA INPUT DATA STORED DATA INPUT DATA STORED DATA STORED DATA X X X X X X X X UPPER BYTE (DQ9-DQ16) OF WORD LOWER BYTE (DQ1-DQ8) OF WORD Figure 3 WORD AND BYTE WRITE EXAMPLE WRITE on one byte and a LATE WRITE on the other byte is not allowed during the same cycle. However, an EARLY WRITE on one byte and, after a ?C?A/S precharge has been satisfied, a LATE WRITE on the other byte is permissable. REFRESH Preserve correct memory cell data by maintaining power and executing a ?R?A/S cycle (READ, WRITE) or ?R?A/S refresh cycle ( ?R?A/S ONLY, CBR, or HIDDEN) so that all 1,024 combinations of ?R?A/S addresses are executed at least every 16ms, regardless of sequence. The CBR REFRESH cycle will invoke the refresh counter for automatic ?R?A/S addressing.

AS4LC1M16 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. REV. 3/97 DS000020 AS4LC1M16 883C AUSTIN SEMICONDUCTOR, INC. CASL CAS RAS NO. 2 CLOCK GENERATOR REFRESH CONTROLLER NO. 1 CLOCK GENERATOR 1024 x 1024 x 16 MEMORY ARRAY Vcc Vss OE DQ1 DQ16 REFRESH COUNTER CASH 1024 1024 x 16 SENSE AMPLIFIERS I/O GATING 1024 DATA-OUT BUFFER WE ROW- ADDRESS BUFFERS (10) ROW DECODER COLUMN- ADDRESS BUFFER DATA-IN BUFFER COLUMN DECODER FUNCTIONAL BLOCK DIAGRAM

AS4LC1M16 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. REV. 3/97 DS000020 AS4LC1M16 883C AUSTIN SEMICONDUCTOR, INC. TRUTH TABLE ADDRESSES FUNCTION ?R?A/S ?C?A/S/L ?C?A/S/H ?W/E ?O/E tR tC DQs NOTES Standby H H >XH >X X X X X High-Z READ: WORD L L L H L ROW COL Data-Out READ: LOWER BYTE L L H H L ROW COL Lower Byte, Upper Byte, Data-Out READ: UPPER BYTE L H L H L ROW COL Lower Byte, Data-Out Upper Byte WRITE: WORD L L L L X ROW COL Data-In (EARLY WRITE) WRITE: LOWER L L H L X ROW COL Lower Byte, Data-In BYTE (EARLY) Upper Byte, High-Z WRITE: UPPER L H L L X ROW COL Lower Byte, High-Z BYTE (EARLY) Upper Byte, Data-In READ WRITE L L L H >LL >H ROW COL Data-Out, Data-In 1, 2 EDO-PAGE-MODE 1st Cycle L H >LH >L H L ROW COL Data-Out 2 READ 2nd Cycle L H >LH >L H L n/a COL Data-Out 2 Any Cycle L L >HL >H H L n/a n/a Data-Out 2 EDO-PAGE-MODE 1st Cycle L H >LH >L L X ROW COL Data-In 1 WRITE 2nd Cycle L H >LH >L L X n/a COL Data-In 1 EDO-PAGE-MODE 1st Cycle L H >LH >LH >LL >H ROW COL Data-Out, Data-In 1, 2 READ-WRITE 2nd Cycle L H >LH >LH >LL >H n/a COL Data-Out, Data-In 1, 2 HIDDEN READ L >H >L L L H L ROW COL Data-Out 2 REFRESH WRITE L >H >L L L L X ROW COL Data-In 1, 3 ?R ?A/S-ONLY REFRESH L H H X X ROW n/a High-Z CBR REFRESH H >L L L H X X X High-Z 4 NOTE: 1. These WRITE cycles may also be BYTE WRITE cycles (either ?C ?A/S/L or ?C ?A/S/H active). 2. These READ cycles may also be BYTE READ cycles (either ?C ?A/S/L or ?C ?A/S/H active). 3. EARLY WRITE only. 4. Only one ?C ?A/S must be active (?C ?A/S/L or ?C ?A/S/H).

AS4LC1M16 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. REV. 3/97 DS000020 AS4LC1M16 883C AUSTIN SEMICONDUCTOR, INC. PARAMETER/CONDITION SYMBOL -6 -7 -8 UNITS NOTES STANDBY CURRENT: (TTL) ( ?R ?A/S = ?C ?A/S = VIH)I CC 1 22 2 m A STANDBY CURRENT: (CMOS) I CC 2 11 1 m A (?R ?A/S = ?C ?A/S = other inputs = VCC -0.2V) OPERATING CURRENT: Random READ/WRITE Average power supply current I CC 3 170 155 140 mA 5, 6 (?R ?A/S, ?C ?A/S address cycling: tRC = tRC [MIN]) OPERATING CURRENT: EDO PAGE MODE Average power supply current I CC 4 130 120 110 mA 5, 6 (?R ?A/S = VIL, ?C ?A/S, address cycling: tPC = tPC [MIN]) REFRESH CURRENT: ?R ?A/S ONLY Average power supply current I CC 5 160 145 130 mA 5, 6 (?R ?A/S cycling, ?C ?A/S=V IH: tRC = tRC [MIN]) REFRESH CURRENT: CBR Average power supply current I CC 6 150 140 130 mA 5, 7 (?R ?A/S, ?C ?A/S address cycling: tRC = tRC [MIN]) ABSOLUTE MAXIMUM RATINGS* Voltage on NC, Inputs or I/O pins *Stresses greater than those listed under “Absolute Maxi- mum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indi- cated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. MAX ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS (Notes: 1, 2, 3) (VCC = +3.3V ±0.3V) PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES Supply Voltage V CC 3.0 3.6 V Input High (Logic 1) Voltage, all inputs (including NC pins) V IH 2.0 V CC +1 V Input Low (Logic 0) Voltage, all inputs (including NC pins) V IL -1.0 0.8 V INPUT LEAKAGE CURRENT Any input 0V ≤ VIN ≤ 5.5V VCC = 3.6V I I -2 2 µA4 (All other pins not under test = 0V) OUTPUT LEAKAGE CURRENT (Q is disabled; 0V ≤ VOUT ≤ 5.5V) VCC =3.6V I OZ -10 10 µA OUTPUT LEVELS V OH 2.4 V Output High Voltage (IOUT = -2.0mA) Output Low Voltage (IOUT = 2.0mA) V OL 0.4 V

AS4LC1M16 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. REV. 3/97 DS000020 AS4LC1M16 883C AUSTIN SEMICONDUCTOR, INC. CAPACITANCE PARAMETER SYMBOL MAX UNITS NOTES Input Capacitance: Addresses C I1 7p F8 Input Capacitance: ?R ?A/S, ?C ?A/S/L,?C ?A/S/H, ?W /E, ?O /EC I2 7p F8 Input/Output Capacitance: DQ C IO 8p F8 ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS AC CHARACTERISTICS -6 -7 -8 PARAMETER SYM MIN MAX MIN MAX MIN MAX UNITS NOTES Access time from column-address tAA 30 35 40 ns Column-address set-up to ?C ?A/S precharge tACH 15 15 25 ns Column-address hold time (referenced to ?R ?A/S) tAR 45 50 60 ns Column-address setup time tASC 0 0 0 ns 25 Row-address setup time tASR 0 0 0 ns 25 Column-address to ?W /E delay time tAWD 55 60 65 ns 13 Access time from ?C ?A/S tCAC 15 20 20 ns 14, 26 Column-address hold time tCAH 10 12 15 ns 25 ?C ?A/S pulse width tCAS 12 10,000 13 10,000 15 10,000 ns 27 ?C ?A/S hold time (CBR REFRESH) tCHR 10 12 15 ns 7, 28 Last ?C ?A/S going LOW to first ?C ?A/S to return HIGH tCLCH 10 10 15 ns 29 ?C ?A/S to output in Low-Z tCLZ 0 0 0 ns 26 Data output hold after next ?C ?A/S LOW tCOH 3 3 3 ns ?C ?A/S precharge time tCP 10 10 10 ns 15, 30 Access time from ?C ?A/S precharge tCPA 35 40 40 ns 26 ?C ?A/S to ?R ?A/S precharge time tCRP 5 5 5 ns 28 ?C ?A/S hold time tCSH 50 55 60 ns 28 ?C ?A/S setup time (CBR REFRESH) tCSR 5 5 10 ns 7, 25 ?C ?A/S to ?W /E delay time tCWD 35 40 45 ns 13, 25 Write command to ?C ?A/S lead time tCWL 15 15 20 ns 28 Data-in hold time tDH 10 12 15 ns 16, 26 Data-in hold time (referenced to ?R ?A/S) tDHR 45 55 60 ns Data-in setup time tDS 0 0 0 ns 16, 26 Output disable tOD 0 15 0 15 0 15 ns Output Enable tOE 15 20 20 ns 17, 26 ?O /E hold time from ?W /E during READ-MODIFY-WRITE cycletOEH 12 12 15 ns 18 ?O /E HIGH hold from ?C ?A/S HIGH tOEHC 10 10 10 ns 18 ?O /E HIGH pulse width tOEP 10 10 10 ns

AS4LC1M16 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. REV. 3/97 DS000020 AS4LC1M16 883C AUSTIN SEMICONDUCTOR, INC. ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS AC CHARACTERISTICS -6 -7 -8 PARAMETER SYM MIN MAX MIN MAX MIN MAX UNITS NOTES ?O /E LOW to ?C ?A/S HIGH setup time tOES 5 5 10 ns Output buffer turn-off delay tOFF 0 15 0 15 0 20 ns 20, 26 ?O /E setup prior to ?R?A/S during HIDDEN REFRESH cycletORD 0 0 0 ns EDO-PAGE-MODE READ or WRITE cycle time tPC 30 35 40 ns 31 EDO-PAGE-MODE READ-WRITE cycle time tPRWC 75 85 90 ns 31 Access time from ?R ?A/S tRAC 60 70 80 ns 19 ?R ?A/S to column-address delay time tRAD 12 30 12 35 15 40 ns 21 Row-address hold time tRAH 10 10 10 ns Column-address to ?R ?A/S lead time tRAL 30 35 40 ns ?R ?A/S pulse width tRAS 60 10,000 70 10,000 80 10,000 ns ?R ?A/S pulse width (EDO PAGE MODE) tRASP 60 100,000 70 100,000 80 100,000 ns Random READ or WRITE cycle time tRC 110 130 150 ns ?R ?A/S to ?C ?A/S delay time tRCD 14 45 14 50 16 60 ns 22, 25 Read command hold time (referenced to ?C ?A/S) tRCH 0 0 0 ns 23, 28 Read command setup time tRCS 0 0 0 ns 25 Refresh period (1,024 cycles) tREF 16 16 16 ms ?R ?A/S precharge time tRP 40 50 60 ns ?R ?A/S to ?C ?A/S precharge time tRPC 5 5 5 ns Read command hold time (referenced to ?R ?A/S) tRRH 0 0 0 ns 23 ?R ?A/S hold time tRSH 13 15 20 ns 32 READ WRITE cycle time tRWC 150 180 200 ns ?R ?A/S to ?W /E delay time tRWD 80 90 105 ns 13 Write command to ?R ?A/S lead time tRWL 15 18 20 ns Transition time (rise or fall) tT 2 50 2 50 2 50 ns Write command hold time tWCH 10 12 15 ns 32 Write command hold time (referenced to ?R ?A/S) tWCR 45 55 60 ns ?W /E command setup time tWCS 0 0 0 ns 13, 25 Output disable delay from ?W /E tWHZ 0 13 0 15 0 20 ns Write command pulse width tWP 10 12 15 ns ?W /E pulse width to disable at ?C ?A/S HIGH tWPZ 10 12 15 ns ?W /E hold time (CBR REFRESH) tWRH 10 10 10 ns ?W /E setup time (CBR REFRESH) tWRP 10 10 10 ns

AS4LC1M16 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. REV. 3/97 DS000020 AS4LC1M16 883C AUSTIN SEMICONDUCTOR, INC. NOTES 1. All voltages referenced to V SS. 2. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (0˚C ≤ TA ≤ 70˚C) is assured. 3. An initial pause of 100 µs is required after power-up followed by eight ?R?A/S refresh cycles (?R?A/S ONLY or CBR with ?W/E HIGH) before proper device operation is assured. The eight ?R?A/S cycle wake-ups should be repeated any time the tREF refresh requirement is exceeded. 4. NC pins are assumed to be left floating and are not tested for leakage. 5. I CC is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. 6. Column address changed once each cycle. 7. Enables on-chip refresh and address counters. 8. This parameter is sampled. V CC = +3.0V; f = 1 MHz. 9. AC characteristics assume tT = 2.5ns. 10. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL (or between VIL and VIH). 11. In addition to meeting the transition rate specifica- tion, all input signals must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 12. Measured with a load equivalent to two TTL gates, 100pF and VOL = 0.8V and VOH = 2.0V. 13. tWCS, tRWD, tAWD and tCWD are not restrictive operating parameters. tWCS applies to EARLY WRITE cycles. tRWD, tAWD and tCWD apply to READ-MODIFY-WRITE cycles. If tWCS ≥ tWCS (MIN), the cycle is an EARLY WRITE cycle and the data output will remain an open circuit throughout the entire cycle. If tWCS < tWCS (MIN) and tRWD ≥ tRWD (MIN), tAWD ≥ tAWD (MIN) and tCWD ≥ tCWD (MIN), the cycle is a READ-MODIFY-WRITE and the data output will contain data read from the selected cell. If neither of the above conditions is met, the state of data-out is indeterminate. ?O/E held HIGH and ?W/E taken LOW after ?C?A/S goes LOW results in a LATE WRITE (?O/E-controlled) cycle. tWCS, tRWD, tCWD and tAWD are not applicable in a LATE WRITE cycle. 14. Assumes that tRCD ≥ tRCD (MAX). 15. If ?C?A/S is LOW at the falling edge of ?R?A/S, Q will be maintained from the previous cycle. To initiate a new cycle and clear the data-out buffer, ?C?A/S must be pulsed HIGH for tCP. 16. These parameters are referenced to ?C?A/S leading edge in EARLY WRITE cycles and ?W/E leading edge in LATE WRITE or READ-MODIFY-WRITE cycles. 17. If ?O/E is tied permanently LOW, LATE WRITE or READ-MODIFY-WRITE operations are not permis- sible and should not be attempted. Additionally, ?W/E must be pulsed during ?C?A/S HIGH time in order to place I/O buffers in High-Z. 18. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOD and tOEH met (?O/E HIGH during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycle. The DQs will provide the previously read data if ?C?A/S remains LOW and ?O/E is taken back LOW after tOEH is met. If ?C?A/S goes HIGH prior to ?O/E going back LOW, the DQs will remain open. 19. Assumes that tRCD < tRCD (MAX). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase by the amount that tRCD exceeds the value shown. 20. tOFF (MAX) defines the time at which the output achieves the open circuit condition, and is not referenced to V OH or VOL. It is referenced from the rising edge of ?R?A/S or ?C?A/S, whichever occurs last. 21. Operation within the tRAD (MAX) limit ensures that tRAC (MIN) and tCAC (MIN) can be met. tRAD (MAX) is specified as a reference point only; if tRAD is greater than the specified tRAD (MAX) limit, then access time is controlled exclusively by tAA, provided tRCD is not exceeded. 22. Operation within the tRCD (MAX) limit ensures that tRAC (MAX) can be met. tRCD (MAX) is specified as a reference point only; if tRCD is greater than the specified tRCD (MAX) limit, then access time is controlled exclusively by tCAC, provided tRAD is not exceeded. 23. Either tRCH or tRRH must be satisfied for a READ cycle. 24. The first ?C?A/Sx edge to transition LOW. 25. Output parameter (DQx) is referenced to correspond- ing ?C?A/S input; DQ1-DQ8 by ?C?A/S/L and DQ9-DQ16 by ?C?A/S?H. 26. Each ?C?A/Sx must meet minimum pulse width. 27. The last ?C?A/Sx edge to transition HIGH. 28. Last falling ?C?A/Sx edge to first rising ?C?A/Sx edge. 29. Last rising ?C?A/Sx edge to first falling ?C?A/Sx edge. 30. Last rising ?C?A/Sx edge to next cycle’s last rising ?C?A/Sx edge. 31. Last ?C?A/Sx to go LOW. 32. A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, ?W/E = LOW and ?O/E = HIGH.

AS4LC1M16 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. REV. 3/97 DS000020 AS4LC1M16 883C AUSTIN SEMICONDUCTOR, INC. TIMING PARAMETERS -6 -7 -8 SYM MIN MAX MIN MAX MIN MAX UNITS tAA 30 35 40 ns tACH 15 15 20 ns tAR 45 50 60 ns tASC 0 0 0 ns tASR 0 0 0 ns tCAC 15 20 20 ns tCAH 10 12 15 ns tCAS 12 10,000 13 10,000 20 10,000 ns tCLCH 10 10 10 ns tCLZ 0 0 0 ns tCRP 5 5 5 ns tCSH 50 55 60 ns tOD 0 15 0 15 0 20 ns tOE 15 20 20 ns tOFF 0 15 0 15 0 20 ns READ CYCLE NOTE 1 /,/, /,/,/, /,/, tWRP tWRH /,/, /,/, /,/, /,/, /,/,/, /,/, /,/, /,/, tRRH /,/,/, /,/,/, tCLZ tCAC tRAC tAA VALID DATA OPEN tOFF tRCH ROW tRCS tASCtRAH tRAD tAR tCAH tRAL tRCD tCAS tRSH tCSH tRP tRC tRAS tCRP tASR ROW OPEN RAS V V IH IL V V IH IL ADDR V V IH IL DQ V V OH OL V V IH IL /,/, /,/,/,/, /,/,/,/, /,/,/, tODtOE OE V V IH IL COLUMN /,/, /,/,/,/, /,/,/, WE CASL/CASH tCLCH NOTE 2 tACH DON’T CARE UNDEFINED /,/, tRAC 60 70 80 ns tRAD 12 30 12 35 15 40 ns tRAH 10 10 10 ns tRAL 30 35 40 ns tRAS 60 10,000 70 10,000 80 10,000 ns tRC 110 130 150 ns tRCD 14 45 14 50 20 60 ns tRCH 0 0 0 ns tRCS 0 0 0 ns tRP 40 50 60 ns tRRH 0 0 0 ns tRSH 13 15 15 ns tWRH 10 10 10 ns tWRP 10 10 10 ns -6 -7 -8 SYM MIN MAX MIN MAX MIN MAX UNITS NOTE: 1. Although ?W /E is a “don’t care” at ?R ?A/S time during an access cycle (READ or WRITE), the system designer should implement ?W /E HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs. 2. tOFF is referenced from rising edge of ?R ?A/S or ?C ?A/S, whichever occurs last.

AS4LC1M16 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. REV. 3/97 DS000020 AS4LC1M16 883C AUSTIN SEMICONDUCTOR, INC. EARLY WRITE CYCLE DON’T CARE UNDEFINED /,/, /,/, /,/, /,/, /,/,/, /,/, /,/, V V IH IL /,/, /,/,/, /,/,/, /,/,/, /,/,/, /,/,/, /,/, VALID DATA ROWCOLUMNROW tDS tDHR tWP tWCHtWCS tWCR tRWL tCWL tCAHtASCtRAHtASR tRAD tRAL tAR tCAS tRSH tCSH tRCDtCRP tRAS tRC tRP V V IH IL ADDR V V IH IL V V IH IL DQ V V IOH IOL V V IH IL RAS OE /,/,/, /,/,/, /,/,/, /,/,/, /,/,/, /,/,/, /,/,/, /,/, /,/, /,/,/, /,/,/, tDH tCLCH WE CASL/CASH tACH NOTE 1 /,/, /,/, /,/, /,/,/, tWRP tWRH tRAH 10 10 10 ns tRAL 30 35 40 ns tRAS 60 10,000 70 10,000 80 10,000 ns tRC 110 130 150 ns tRCD 14 45 14 50 20 60 ns tRP 40 50 60 ns tRSH 13 15 0 ns tRWL 15 15 20 ns tWCH 10 12 15 ns tWCR 45 55 60 ns tWCS 0 0 0 ns tWP 10 12 15 ns tWRH 10 10 10 ns tWRP 10 10 10 ns TIMING PARAMETERS -6 -7 -8 SYM MIN MAX MIN MAX MIN MAX UNITS tACH 15 15 20 ns tAR 45 50 60 ns tASC 0 0 0 ns tASR 0 0 0 ns tCAH 10 12 15 ns tCAS 12 10,000 13 10,000 20 10,000 ns tCLCH 10 10 10 ns tCRP 5 5 5 ns tCSH 50 55 60 ns tCWL 15 15 20 ns tDH 10 12 15 ns tDHR 45 55 55 ns tDS 0 0 0 ns tRAD 12 30 12 35 15 40 ns -6 -7 -8 SYM MIN MAX MIN MAX MIN MAX UNITS NOTE: 1. Although ?W /E is a “don’t care” at ?R ?A/S time during an access cycle (READ or WRITE), the system designer should implement ?W /E HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.

AS4LC1M16 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. REV. 3/97 DS000020 AS4LC1M16 883C AUSTIN SEMICONDUCTOR, INC. READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE cycles) /,/,/, /,/,/, VALID D OUT VALID D IN /,/, /,/, ROW /,/,/, /,/,/,/, /,/, COLUMN ROW /,/, /,/,/,/, /,/,/,/, /,/, V V IH IL V V IH IL ADDR V V IH IL V V IH IL DQ V V IOH IOL V V IH IL RAS OPENOPEN tOE tOD tCAC tRAC tAA tCLZ tDS tDH tAWD tWP tRWL tCWL tCWD tRWD tRCS tASC tCAH tAR tASR tRAD tRAL tCRP tRCD tCAS, CLCH tRSH tCSH tRAS tRWC tRP tRAH OE tOEH /,/, /,/,/, WE tACH CASL/CASH t NOTE 1 /,/, /,/, /,/, /,/,/, /,/, /,/, tWRP tWRH DON’T CARE UNDEFINED tOE 15 20 20 ns tOEH 12 12 15 ns tRAC 60 70 80 ns tRAD 12 30 12 35 15 40 ns tRAH 10 10 10 ns tRAL 30 35 40 ns tRAS 60 10,000 70 10,000 80 10,000 ns tRCD 14 45 14 50 20 60 ns tRCS 0 0 0 ns tRP 40 50 60 ns tRSH 13 15 15 ns tRWC 150 180 200 ns tRWD 80 90 105 ns tRWL 15 15 20 ns tWP 10 12 15 ns tWRH 10 10 10 ns tWRP 10 10 10 ns TIMING PARAMETERS -6 -7 -8 SYM MIN MAX MIN MAX MIN MAX UNITS tAA 30 35 40 ns tACH 15 15 20 ns tAR 45 50 60 ns tASC 0 0 0 ns tASR 0 0 0 ns tAWD 55 60 65 ns tCAC 15 20 20 ns tCAH 10 12 15 ns tCAS 12 10,000 13 10,000 20 10,000 ns tCLCH 10 10 10 ns tCLZ 0 0 0 ns tCRP 5 5 5 ns tCSH 50 55 60 ns tCWD 35 40 45 ns tCWL 15 15 20 ns tDH 10 12 15 ns tDS 0 0 0 ns tOD 0 15 0 15 0 20 ns NOTE: 1. Although ?W /E is a “don’t care” at ?R ?A/S time during an access cycle (READ or WRITE), the system designer should implement ?W /E HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs. -6 -7 -8 SYM MIN MAX MIN MAX MIN MAX UNITS

AS4LC1M16 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. REV. 3/97 DS000020 AS4LC1M16 883C AUSTIN SEMICONDUCTOR, INC. tOEP 10 10 10 ns tOES 5 5 5 ns tO F F 3 1 531 502 0n s tPC 30 35 40 ns tRAC 60 70 80 ns tRAD 12 30 12 35 15 40 ns tRAH 10 10 10 ns tRAL 30 35 40 ns tRASP 60 100,000 70 100,000 80 100,000 ns tRCD 14 45 14 50 20 60 ns tRCH 0 0 0 ns tRCS 0 0 0 ns tRP 40 50 60 ns tRRH 0 0 0 ns tRSH 13 15 15 ns tWRH 10 10 10 ns tWRP 10 10 10 ns TIMING PARAMETERS -6 -7 -8 SYM MIN MAX MIN MAX MIN MAX UNITS tAA 30 35 40 ns tACH 15 15 20 ns tAR 45 50 60 ns tASC 0 0 0 ns tASR 0 0 0 ns tCAC 15 20 20 ns tCAH 10 12 15 ns tCAS 12 10,000 13 10,000 20 10,000 ns tCLCH 10 10 10 ns tCLZ 0 0 0 ns tCOH 3 3 5 ns tCP 10 10 10 ns tCPA 35 40 40 ns tCRP 5 5 5 ns tCSH 50 55 60 ns tO D0 1 501 502 0n s tOE 15 20 20 ns tOEHC 10 10 10 ns -6 -7 -8 SYM MIN MAX MIN MAX MIN MAX UNITS EDO-PAGE-MODE READ CYCLE ACH /,/, /,/,/, /,/,/, /,/, /,/, /,/, VALID DATA /,/, /,/, VALID DATA VALID DATA /,/, /,/, /,/, /,/, /,/, /,/, /,/, /,/,/, COLUMNCOLUMNCOLUMNROW ROW DON’T CARE UNDEFINED tOD tCAHtASC tRAL tCP tRSH tCPtCPtCAS, CLCHtRCDtCRP tPCtCSH tRASP tRP tCAHtASCtCAHtASC tRAD t AR tRAH tRAD tASR tRCS tRRH tRCH tOFF tCAC tCPA tAA tCLZtCAC tCPA tAA tCAC tRAC tAA tCLZ tOE tOD tOE tOD OPENOPEN V V IH IL V V IH IL ADDR V V IH IL V V IH IL DQ V V OH OL V V IH IL RAS OE CASL/CASH WE tCOH tOEP tOEHC tOES tOES tt CAS, CLCHtt CAS, CLCHt NOTE 1 /,/, /,/, /,/,/, tWRP tWRH t ACHt ACHt NOTE: 1. Although ?W /E is a “don’t care” at ?R ?A/S time during an access cycle (READ or WRITE), the system designer should implement ?W /E HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.

AS4LC1M16 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. REV. 3/97 DS000020 AS4LC1M16 883C AUSTIN SEMICONDUCTOR, INC. EDO-PAGE-MODE EARLY-WRITE CYCLE tRAD 12 30 12 35 15 40 ns tRAH 10 10 10 ns tRAL 30 35 40 ns tRASP 60 125,000 70 125,000 80 100,000 ns tRCD 14 45 14 50 20 60 ns tRP 40 50 60 ns tRSH 13 15 15 ns tRWL 15 15 20 ns tWCH 10 12 15 ns tWCR 45 55 60 ns tWCS 0 0 0 ns tWP 10 12 15 ns tWRH 10 10 10 ns tWRP 10 10 10 ns TIMING PARAMETERS -6 -7 -8 SYM MIN MAX MIN MAX MIN MAX UNITS tACH 15 15 20 ns tAR 45 50 60 ns tASC 0 0 0 ns tASR 0 0 0 ns tCAH 10 12 15 ns tCAS 12 10,000 13 10,000 20 10,000 ns tCLCH 10 10 10 ns tCP 10 10 10 ns tCRP 5 5 5 ns tCSH 50 55 60 ns tCWL 15 15 20 ns tDH 10 12 15 ns tDHR 45 55 55 ns tDS 0 0 0 ns tPC 25 30 40 ns -6 -7 -8 SYM MIN MAX MIN MAX MIN MAX UNITS NOTE: 1. Although ?W /E is a “don’t care” at ?R ?A/S time during an access cycle (READ or WRITE), the system designer should implement ?W /E HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs. /,/, /,/,/, /,/, /,/, /,/, /,/, /,/,/, /,/, /,/, /,/, /,/, /,/,/, /,/, /,/, /,/, /,/,/, /,/, tDS tDH tDS tDH tDS tDH tDHR tWCR VALID DATA VALID DATA VALID DATA tRWL tWP tCWL tWCHtWCS tWP tCWL tWCHtWCS tWP tCWL tWCHtWCS tCAHtASC tRAL tCAHtASCtCAHtASCtRAHtASR tRAD tAR COLUMNCOLUMNCOLUMNROW ROW tCP tRSH tCPtCPtCAS, CLCHtRCDtCRP tPCtCSH tRASP tRP V V IH IL CASL/CASH V V IH IL ADDR V V IH IL WE V V IH IL DQ V V IOH IOL RAS OE V V IH IL /,/, /,/,/, /,/,/, /,/,/,/, /,/,/,/, /,/,/, /,/,/, /,/,/, DON’T CARE UNDEFINED tACH tACH tACH tt CAS, CLCHtt CAS, CLCHt NOTE 1 /,/, /,/,/,/, /,/, tWRP tWRH

AS4LC1M16 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. REV. 3/97 DS000020 AS4LC1M16 883C AUSTIN SEMICONDUCTOR, INC. EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE cycles) /,/,/, /,/,/,/, /,/, /,/, /,/, /, /,/, /,/, /,/,/, /,/, /,/, /,/, /,/, DON’T CARE UNDEFINED /,/,/, t t OD tOE tOD tOE tOD tOE OPEN D OUT VALID D IN VALID D OUT VALID D IN VALID D OUT VALID D IN VALID OPEN tDH tDS tAA tCPA tCLZ tCAC tDH tDS tAA tCPA tCLZ tCAC tDH tDS tAA tCLZ tCAC tRAC tWP tCWL tRWL tCWD tAWD tWP tCWL tCWD tAWD tWP tCWL tCWD tAWD tRCS tRWD tASR tRAH tASC tRAD tAR tCAH tASC tCAH tASC tCAH tRAL tCP tRSH tCP tRPtRASP tCPtRCD tCSH tPC tCRP ROW COLUMN COLUMN COLUMN ROW V V IH IL V V IH IL ADDR V V IH IL V V IH IL DQ V V IOH IOL V V IH IL RAS OE tPRWC OEH /,/,/, tCAS, tCLCHtCAS, tCLCHtCAS, tCLCH WE CASL/CASH NOTE 1 NOTE 2 /,/, /,/, /,/, tWRP tWRH tOE 15 20 20 ns tOEH 12 12 15 ns tPC 25 30 40 ns tPRWC 75 85 90 ns tRAC 60 70 80 ns tRAD 12 30 12 35 15 40 ns tRAH 10 10 10 ns tRAL 30 35 40 ns tRASP 60 125,000 70 125,000 80 100,000 ns tRCD 14 45 14 50 20 60 ns tRCS 0 0 0 ns tRP 40 50 60 ns tRSH 13 15 15 ns tRWD 80 90 105 ns tRWL 15 15 20 ns tWP 10 12 15 ns tWRH 10 10 10 ns tWRP 10 10 10 ns TIMING PARAMETERS -6 -7 -8 SYM MIN MAX MIN MAX MIN MAX UNITS tAA 30 35 40 ns tAR 45 50 60 ns tASC 0 0 0 ns tASR 0 0 0 ns tAWD 55 60 65 ns tCAC 15 20 20 ns tCAH 10 12 15 ns tCAS 12 10,000 13 10,000 20 10,000 ns tCLCH 10 10 10 ns tCLZ 0 0 0 ns tCP 10 10 10 ns tCPA 35 40 40 ns tCRP 5 5 5 ns tCSH 50 55 60 ns tCWD 35 40 45 ns tCWL 15 15 20 ns tDH 10 12 15 ns tDS 0 0 0 ns tOD 0 15 0 15 0 20 ns -6 -7 -8 SYM MIN MAX MIN MAX MIN MAX UNITS NOTE: 1. tPC is for LATE WRITE cycles only. 2. Although ?W /E is a “don’t care” at ?R ?A/S time during an access cycle (READ or WRITE), the system designer should implement ?W /E HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.

AS4LC1M16 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. REV. 3/97 DS000020 AS4LC1M16 883C AUSTIN SEMICONDUCTOR, INC. EDO-PAGE-MODE READ-EARLY-WRITE CYCLE (Pseudo READ-MODIFY-WRITE) V V IH IL V V IH ILRAS V V IH ILADDR V V IH ILWE /,/, /,/, tRASP tRP ROW /,/, /,/, COLUMN (A) /,/, COLUMN (N) /,/, ROW V V IH ILOE V V IOH IOL tCRP tCSH tCAS, CLCHtRCD tASR tRAH tRAD tASC tAR tCAH tASC tCAH tASC tCAH tRAL tCP tRSH VALID DIN /,/, /,/,/,/, /,/,/, /,/, /,/, tRCS tRCH tWCS tOE VALID D OUTVALID DOUT tWHZ tCAC tCPA tAA tCAC tAA OPENDQ tPC RACt tCOH tWCH tDS tDH tPC COLUMN (B) tACH CASL/CASH t tCAS, CLCHttCAS, CLCHttCP tCP DON’T CARE UNDEFINED /,/, /,/, NOTE 1 /,/, /,/, /,/,/,/, /,/, tWRP tWRH tPC 25 30 40 ns tRAC 60 70 80 ns tRAD 12 30 12 35 15 40 ns tRAH 10 10 10 ns tRAL 30 35 40 ns tRASP 60 125,000 70 125,000 80 100,000 ns tRCD 14 45 14 50 20 60 ns tRCH 0 0 0 ns tRCS 0 0 0 ns tRP 40 50 60 ns tRSH 13 15 15 ns tWCH 10 12 15 ns tWCS 0 0 0 ns tWHZ 0 13 0 15 0 20 ns tWRH 10 10 10 ns tWRP 10 10 10 ns TIMING PARAMETERS -6 -7 -8 SYM MIN MAX MIN MAX MIN MAX UNITS tAA 30 35 40 ns tACH 15 15 20 ns tAR 45 50 60 ns tASC 0 0 0 ns tASR 0 0 0 ns tCAC 15 20 20 ns tCAH 10 12 15 ns tCAS 12 10,000 13 10,000 20 10,000 ns tCLCH 10 10 10 ns tCOH 3 3 5 ns tCP 10 10 10 ns tCPA 35 40 40 ns tCRP 5 5 5 ns tCSH 50 55 60 ns tDH 10 12 15 ns tDS 0 0 0 ns tOE 15 20 20 ns -6 -7 -8 SYM MIN MAX MIN MAX MIN MAX UNITS NOTE: 1. Although ?W /E is a “don’t care” at ?R ?A/S time during an access cycle (READ or WRITE), the system designer should implement ?W /E HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.

AS4LC1M16 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. REV. 3/97 DS000020 AS4LC1M16 883C AUSTIN SEMICONDUCTOR, INC. READ CYCLE (with ?W /E-controlled disable) /,/, /,/, /,/, /,/, /,/, /,/, /,/,/, tCLZ tCAC tRAC tAA VALID DATA OPEN tRCHtRCS tASCtRAH tRAD tAR tCAH tRCD tCAS, CLCH tCSH tCRP tASR ROW OPEN RAS V V IH IL V V IH IL ADDR V V IH IL DQ V V OH OL V V IH IL /,/, /,/,/, /,/,/, /,/,/, tODtOE OE V V IH IL COLUMN /,/, /,/,/, /,/,/, WE tWHZ tWPZ tCP tASC tRCS COLUMN tCLZ CASL/CASH t NOTE 1 /,/, /,/, /,/,/, /,/, /,/, tWRP tWRH DON’T CARE UNDEFINED /,/, /,/, NOTE: 1. Although ?W /E is a “don’t care” at ?R ?A/S time during an access cycle (READ or WRITE), the system designer should implement ?W /E HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs. tOD 0 15 0 15 0 15 ns tOE 15 20 20 ns tRAC 60 70 80 ns tRAD 12 30 12 35 15 40 ns tRAH 10 10 10 ns tRCD 14 45 14 50 20 60 ns tRCH 0 0 0 ns tRCS 0 0 0 ns tWHZ 0 13 0 15 0 20 ns tWPZ 10 12 15 ns tWRH 10 10 10 ns tWRP 10 10 10 ns TIMING PARAMETERS -6 -7 -8 SYM MIN MAX MIN MAX MIN MAX UNITS tAA 30 35 40 ns tAR 45 50 60 ns tASC 0 0 0 ns tASR 0 0 0 ns tCAC 15 20 20 ns tCAH 10 12 15 ns tCAS 12 10,000 13 10,000 20 10,000 ns tCLCH 10 10 10 ns tCLZ 0 0 0 ns tCP 10 10 10 ns tCRP 5 5 5 ns tCSH 50 55 60 ns -6 -7 -8 SYM MIN MAX MIN MAX MIN MAX UNITS

AS4LC1M16 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. REV. 3/97 DS000020 AS4LC1M16 883C AUSTIN SEMICONDUCTOR, INC. /,/,/, /,/,/, /,/,/, /,/, ROW V V IH IL V V IH IL ADDR V V IH IL RAS tRC tRAS tRP tCRP tASR tRAH ROW OPENQ V V OH OL tRPC CASL/CASH /,/, /,/,/, /,/, /,/,/, /,/,/,/, /,/, /,/, /,/, WE V V IH IL tWRHtWRP tWRHtWRP NOTE 1 CBR REFRESH CYCLE (Addresses and ?O /E = DON’T CARE) tRP V V IH ILRAS tRAS OPEN tCHRtCSR V V IH ILCASL and CASH DQ tRP tRAS tRPC tCSRtRPC tCHRtCP V V IH IL tWRP tWRH tWRP tWRH /,/, /,/,/, /,/, /,/,/, /,/,/, /,/,/, /,/, WE NOTE 2 V V OH OL NOTE: 1. Although ?W /E is a “don’t care” at ?R ?A/S time during an access cycle (READ or WRITE), the system designer should implement ?W /E HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs. 2. tWRP and tWRH are for system design reference only. The ?W /E signal is actually a “don’t care” at ?R ?A/S time during a CBR REFRESH. However, ?W /E should be held HIGH at ?R ?A/S time during a CBR REFRESH to ensure compatibility with other DRAMs that require ?W /E HIGH at ?R ?A/S time during a CBR REFRESH. tRAS 60 10,000 70 10,000 80 10,000 ns tRC 105 125 150 ns tRP 40 50 60 ns tRPC 5 5 5 ns tWRH 10 10 10 ns tWRP 10 10 10 ns TIMING PARAMETERS -6 -7 -8 SYM MIN MAX MIN MAX MIN MAX UNITS tASR 0 0 0 ns tCHR 10 12 15 ns tCP 10 10 10 ns tCRP 5 5 5 ns tCSR 5 5 10 ns tRAH 10 10 10 ns -6 -7 -8 SYM MIN MAX MIN MAX MIN MAX UNITS

AS4LC1M16 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. REV. 3/97 DS000020 AS4LC1M16 883C AUSTIN SEMICONDUCTOR, INC. TIMING PARAMETERS -6 -7 -8 SYM MIN MAX MIN MAX MIN MAX UNITS tAA 30 35 40 ns tAR 45 50 60 ns tASC 0 0 0 ns tASR 0 0 0 ns tCAC 15 20 20 ns tCAH 10 12 15 ns tCHR 10 12 15 ns tCLZ 0 0 0 ns tCRP 5 5 5 ns tO D0 1 501 5 0 2 0n s tOE 15 20 20 ns /,/, /,/,/, /,/, DON’T CARE UNDEFINED tCLZ tOFF /,/, /,/,/, /,/,/, /,/,/, /,/,/, /,/, /,/, /,/, OPENVALID DATAOPEN COLUMNROW tCAC tRAC tAA tCAHtASCtRAHtASR tRAD tAR tRAL tCRP tRCD tRSH tRAS tRC tRP tCHR tRAS DQx V V IOH IOL V V IH ILADDR V V IH IL V V IH ILRAS /,/, /,/,/,/, /,/,/,/, /,/, V V IH IL tOE tOD OE tORD CASL/CASH HIDDEN REFRESH CYCLE 32 (?W /E = HIGH; ?O /E = LOW) tOFF 3 15 3 15 3 15 ns tORD 0 0 0 ns tRAC 60 70 80 ns tRAD 12 30 12 35 15 40 ns tRAH 10 10 10 ns tRAL 30 35 40 ns tRAS 60 10,000 70 10,000 80 10,000 ns tRC 105 125 145 ns tRCD 14 45 14 50 20 60 ns tRP 40 50 60 ns tRSH 13 15 15 ns -6 -7 -8 SYM MIN MAX MIN MAX MIN MAX UNITS

AS4LC1M16 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. REV. 3/97 DS000020 AS4LC1M16 883C AUSTIN SEMICONDUCTOR, INC. ELECTRICAL TEST REQUIREMENTS SUBGROUPS MIL-STD-883 TEST REQUIREMENTS (per Method 5005, Table I) INTERIM ELECTRICAL (PRE-BURN-IN) TEST PARAMETERS 2, 8A, 10 (Method 5004) FINAL ELECTRICAL TEST PARAMETERS 1*, 2, 3, 7*, 8, 9, 10, 11 (Method 5004) GROUP A TEST REQUIREMENTS 1, 2, 3, 4**, 7, 8, 9, 10, 11 (Method 5005) GROUP C AND D END-POINT ELECTRICAL PARAMETERS 1, 2, 3, 7, 8, 9, 10, 11 (Method 5005) * PDA applies to subgroups 1 and 7. ** Subgroup 4 shall be measured only for initial qualification and after process or design changes, which may affect input or output capacitance.

AS4LC1M16 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. REV. 3/97 DS000020 AS4LC1M16 883C AUSTIN SEMICONDUCTOR, INC.