AS4DDR264M72PBG1-5/XT

AS4DDR264M72PBG1 AUSTIN | Alldatasheet

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Technical content

Rev. 3.0 6/09 Austin Semiconductor, Inc. 64Mx72 DDR2 SDRAM w/ SHARED CONTROL BUS iNTEGRATED Plastic Encapsulated Microcircuit

FEATURES

„ DDR2 Data rate = 667, 533, 400 „ Available in Industrial, Enhanced and Military Temp „ Package:

• Proprietary Enchanced Die Stacked iPEM  208 Plastic Ball Grid Array (PBGA), 16 x 23mm  1.00mm ball pitch „ Differential data strobe (DQS, DQS#) per byte „ Internal, pipelined, double data rate architecture „ 4n-bit prefetch architecture „ DLL for alignment of DQ and DQS transitions with clock signal „ Eight internal banks for concurrent operation (Per DDR2 SDRAM Die) „ Programmable Burst lengths: 4 or 8 „ Auto Refresh and Self Refresh Modes (I/T Version) „ On Die Termination (ODT) „ Adjustable data – output drive strength „ 1.8V ±0.1V common core power and I/O supply „ Programmable CAS latency: 3, 4, 5, 6 or 7 „ Posted CAS additive latency: 0, 1, 2, 3, 4 or 5 „ Write latency = Read latency - 1* tCK „ Organized as 64M x 72 „ Weight: AS4DDR264M72PBG1 ~ 2.0 grams typical NOTE: Self Refresh Mode available on Industrial and Enhanced temp. only BENEFITS „ 61% Space Savings „ 55% I/O reduction vs Individual package approach „ Reduced part count „ Reduced trace lengths for lower parasitic capacitance „ Suitable for hi-reliability applications „ Upgradable to 128M x 72 density in future „ Pin/Function equivalent to White W3H64M72E-xBSx FUNCTIONAL BLOCK DIAGRAM ODT VRef VCC VCCQ VSS VSSQ VCCL VSSDL VCCL VSSDL VCCL VSSDL VCCL VSSDL VCCL VSSDL WE\\ RAS\\ CAS\\ CKE\\ Ax, BA0-2 UDMx, LDMx UDSQx,UDSQx\\ LDSQx, LDSQx\\ ODT CKx,CKx\\ A BC D DQ0-15 DQ16-31 DQ32-47 DQ48-63A B C D DQ64-71 VCCQVCCQ VCCQ VCCQ VSSQ VSSQ VSSQ VSSQ VSSQ CS\\ LDM4 UDM4 ODT ConfigurationAddressing Parameter 64 Megx72 Configuration 8 Megx16x8Banks RefreshCount 8K RowAddress A0 ͲA12(8k) BankAddress BA0 ͲBA2(8) ColumnAddress A0 ͲA9(1K)

Rev. 3.0 6/09 Austin Semiconductor, Inc. 123456789 1 0 1 1 A Vcc Vss Vcc Vcc Vss Vcc Vcc Vss Vcc Vss A B Vcc Vss NC NC NC NC NC NC NC Vss Vcc B C Vss NC NC NC NC NC NC DQ34 CK3 CK3\\ Vss C D DQ35 DQ51 NC NC NC NC DQ50 DQ53 DQ37 CK2\\ CK2 D E DQ52 DQ36 DQ33 NC BA2 NC DQ39 LDQS2 LDQS3 DQ48 DQ32 E F LDM3 LDM2 DQ49 DQ43 DQ59 NC DQ55 DQ58 DQ42 LDQS2\\ LDQS3\\ F G DQ38 DQ54 DQ60 DQ57 UDM2 Vss DQ63 DQ56 DQ40 DQ61 DQ45 G H UDM3 DQ44 DQ41 DQ46 DQ62 Vcc UDQS2\\ DQ47 UDQS2 UDQS3 UDQS3\\ H J Vcc A6 A10 A9 Vcc Vss Vcc A3 A12 RFU Vcc J K Vss A0 A11 Vcc Vss Vref Vss Vcc A1 BA1 Vss K L Vcc A2 A4 A8 Vcc Vss Vcc BA0 A5 A7 Vcc L M UDQS1\\ UDQS1 UDQS0 DQ15 UDQS0\\ Vcc DQ30 DQ14 DQ9 DQ12 UDM1 M N DQ13 DQ29 DQ8 DQ24 DQ31 Vss UDM0 DQ25 DQ28 DQ22 DQ6 N P LDQS1\\ LDQS0\\ DQ10 DQ26 DQ23 ODT DQ27 DQ11 DQ17 LDM0 LDM1 p R DQ0 DQ16 LDQS1 LDQS0 DQ7 LDQS4\\ UDQS4 UDQS4\\ DQ1 DQ4 DQ20 R T CK0 CK0\\ DQ5 DQ21 DQ18 LDQS4 DQ71 CKE WE\\ DQ19 DQ3 T U Vss CK1\\ CK1 DQ2 RAS\\ CAS\\ DQ64 DQ70 DQ65 DQ68 Vss U V Vcc Vss CK4\\ CK4 CS\\ DQ66 DQ69 LDM4 DQ67 Vss Vcc V W Vss Vcc Vss Vcc Vcc Vss Vcc Vcc Vss Vcc Vss W 123456789 1 0 1 1 Ground Array Power UNPOPULATED Address CNTRL Level REF. NC RFU Data I/O SDRAM-DDRII PINOUT TOP VIEW

Rev. 3.0 6/09 Austin Semiconductor, Inc. BGA Locations Symbol Type Description P6 ODT CNTL Input On-Die-Termination: Registered High enables on data bus termination C9,C10,D10,D11,T1,T2, CKx, CKx\\ CNTL Input Differential input clocks, one set for each x16bits U2,U3,V3,V4 T8 CKE CNTL Input Clock enable which activates all on silicon clocking circuitry V5 CS\\ CNTL Input Chip Selects, one for each 16 bits of the data bus width U5 RAS\\ CNTL Input Command input which along with CAS\\, WE\\ and CS\\ define operations U6 CAS\\ CNTL Input Command input which along with RAS\\, WE\\ and CS\\ define operations T9 WE\\ CNTL Input Command input which along with RAS\\, CAS\\ and CS\\ define operations G5,H1,M11,N7, UDMx CNTL Input One Data Mask cntl. for each upper 8 bits of a x16 word F1,F2,P10,P11,V8 LDMx CNTL Input One Data Mask cntl. For each lower 8 bits of a x16 word H9,H10,M2,M3,R7 UDQSx CNTL Input Data Strobe input for upper byte of each x16 word H7,H11,M1,M5,R8 UDQSx\\ CNTL Input Differential input of UDQSx, only used when Differential DQS mode is enabled E8,E9,R3,R4,T6 LDQSx CNTL Input Data Strobe input for lower byte of each x16 word F10,F11,P1,P2,R6 LDQSx\\ CNTL Input Differential input of LDQSx, only used when Differential DQS mode is enabled J2,J3,J4,J8,J9,K2, Ax Input Array Address inputs providing ROW addresses for Active commands, and K3,K9,L2,L3,L4,L9,L10 the column address and auto precharge bit (A10) for READ/WRITE commands J10 RFU Future Input L8,K10,E5 BA0,BA1,BA2 Input Bank Address inputs C8,D1,D2,D7,D8,D9,E1, DQx Input/Output Data bidirectional input/Output pins E2,E3,E7,E10,E11,F3, F4,F5,F7,F8,F9,G1,G2, G3,G4,G7,G8,G9,G10, G11,H2,H3,H4,H5,H8, M4,M7,M8,M9,M10,N1, N2,N3,N4,N5,N8,N9, N10,N11,P3,P4,P5,P7, P8,P9,R1,R2,R5,R9, R10,R11,T3,T4,T5,T7, T10,T11,U4,U7,U8,U9, U10,V6,V7,V9 k6 Vref Supply SSTL_18 Voltage Reference A2,A4,A5,A7,A8,A10, VCC Supply Core Power Supply B1,B11,H6,J1,J5,J7,J11, K4,K8,L1,L5,L7,L11,M6, V1,V11,W2,W4,W5, W7,W8,W10 A3,A6,A9,A11,B2,B10, VSS Supply Core Ground return C1,C11,G6,J6,K1,K5, K7,K11,L6,N6,U1,U11, V2,V10,W1,W3,W6, W9,W11 B3,B4,B5,B6,B7,B8,B9, NC No connection C2,C3,C4,C5,C6,C7,D3, D4,D5,D6,E4, E6, F6 A1 UNPOPULATED Unpopulated ball matrix location (location registration aid)

Rev. 3.0 6/09 Austin Semiconductor, Inc.

DESCRIPTION

The 4.8Gb DDR2 SDRAM, a high-speed CMOS, dynamic random-access memory containing 4,831,838,208 bits. Each of the five chips in the MCP are internally configured as 8-bank DRAM. The block diagram of the device is shown in Figure 2. Ball assignments and are shown in Figure 3. The 4.8Gb DDR2 SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 4 n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls. A single read or write access for the x72 DDR2 SDRAM effectively consists of a single 4 n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and four corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O balls. A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. There are strobes, one for the lower byte (LDQS, LDQS#) and one for the upper byte (UDQS, UDQS#). The MCP DDR2 SDRAM operates from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Read and write accesses to the DDR2 SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and the starting column location for the burst access. The DDR2 SDRAM provides for programmable read or write burst lengths of four or eight locations. DDR2 SDRAM supports interrupting a burst read of eight with another read, or a burst write of eight with another write. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard DDR SDRAMs, the pipelined, multibank architecture of DDR2 SDRAMs allows for concurrent operation, thereby providing high, effective bandwidth by hiding row precharge and activation time. A self refresh mode is provided, along with a power-saving power-down mode. All inputs are compatible with the JEDEC standard for SSTL_18. All full drive-strength outputs are SSTL_18- compatible. GENERAL NOTES  The functionality and the timing specifications discussed in this data sheet are for the DLLenabled mode of operation.  Throughout the data sheet, the various figures and text refer to DQs as ¡°DQ.¡± The DQ term is to be interpreted as any and all DQ collectively, unless specifically stated otherwise. Additionally, each chip is divided into 2 bytes, the lower byte and upper byte. For the lower byte (DQ0¨CDQ7), DM refers to LDM and DQS refers to LDQS. For the upper byte (DQ8¨CDQ15), DM refers to UDM and DQS refers to UDQS.  Complete functionality is described throughout the document and any page or diagram may have been simplified to convey a topic and may not be inclusive of all requirements.  Any specific requirement takes precedence over a general statement. INITIALIZATION DDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. The following sequence is required for power up and initialization and is shown in Figure 4 on page 5.

Rev. 3.0 6/09 Austin Semiconductor, Inc. FIGURE 4 - POWER-UP AND INITIALIZATION Notes appear on page 7 LVCMOS LOW LEVEL2 tVTD1 CKE RTT Power-up: VDD and stable clock (CK, CK#) T = 200µs (MIN) High-Z DM15 DQS15 High-Z Address3 CK CK# tCL VTT1 VREF VDDQ Comman d3 NOP4 PRE T0 Ta0 Don’t care tCL tCK ODT DQ15 High-Z T = 400ns (MIN)16 Tb0 200 cycles of CK are require d before a READ comman d can be issued. MR with DLL RESET tRFC LM8 PRE9LM7 REF10 REF LM11 Tg0 Th0 Ti0 Tj0 MR without DLL RESET EMR with OCD default Tk0 Tl0 Tm0Te0 Tf0 EMR(2) EMR(3) tMRD LM6LM5 A10 = 1 tRPA Tc0T d0 SSTL_18 LOW LEVEL2 Valid16 Valid Indicates a break in time scale LM12 EMR with OCD exit LM13 Normal operation See note 17 Code Code A10 = 1Code Code Code Code Code tMRD tMRD tMRD tMRDtRPA tRFC tMRD tMRD EMR VDD VDDL

Rev. 3.0 6/09 Austin Semiconductor, Inc. NOTES: 1. Applying power; if CKE is maintained below 0.2 x VCC, outputs remain disabled. To guarantee RTT (ODT resistance) is off, VREF must be valid and a low level must be applied to the ODT ball (all other inputs may be undefined, I/Os and outputs must be less than VCC during voltage ramp time to avoid DDR2 SDRAM device latch-up). VTT is not applied directly to the device; however, tVTD should be ³0 to avoid device latch-up. At least one of the following two sets of conditions (A or B) must be met to obtain a stable supply state (stable supply defined as VCC, VREF, and VTT are between their minimum and maximum values as stated in DC Operating Conditions table): A. (single power source) The VCC voltage ramp from 300mV to VCC(MIN) must take no longer than 200ms.  All VCC are driven from a single power converter output  VTT is limited to 0.95V MAX  VREF tracks VCC/2; VREF must be within ±0.3V with respect to VCC/2 during supply ramp time.  VCC > VREF at all times 2. CKE requires LVCMOS input levels prior to state T0 to ensure DQs are High-Z during device power-up prior to VREF being stable. After state T0, CKE is required to have SSTL_18 input levels. Once CKE transitions to a high level, it must stay HIGH for the duration of the initialization sequence. 3. A10 = PRECHARGE ALL, CODE = desired values for mode registers (bank addresses are required to be decoded). 4. For a minimum of 200µs after stable power and clock (CK, CK#), apply NOP or DESELECT commands, then take CKE HIGH. 5. Issue a LOAD MODE command to the EMR(2). To issue an EMR(2) command, provide LOW to BA0, and provide HIGH to BA1; set register E7 to “0” or “1” to select appropriate self refresh rate; remaining EMR(2) bits must be “0” (see “Extended Mode Register 2 (EMR2)” on page 84 for all EMR(2) requirements). 6. Issue a LOAD MODE command to the EMR(3). To issue an EMR(3) command, provide HIGH to BA0 and BA1; remaining EMR(3) bits must be “0.” See “Extended Mode Register 3 (EMR 3)” on page 13 for all EMR(3) requirements. 7. Issue a LOAD MODE command to the EMR to enable DLL. To issue a DLL ENABLE command, provide LOW to BA1 and A0; provide HIGH to BA0; bits E7, E8, and E9 can be set to “0” or “1;” Austin recommends setting them to “0;” remaining EMR bits must be “0. ”See “Extended Mode Register (EMR)” on page 10 for all EMR requirements. 8. Issue a LOAD MODE command to the MR for DLL RESET. 200 cycles of clock input is required to lock the DLL. To issue a DLL RESET, provide HIGH to A8 and provide LOW to BA1 and BA0; CKE must be HIGH the entire time the DLL is resetting; remaining MR bits must be “0.” See “Mode Register (MR)” on page 7 for all MR requirements. 9. Issue PRECHARGE ALL command. 10. Issue two or more REFRESH commands. 11. Issue a LOAD MODE command to the MR with LOW to A8 to initialize device operation (that is, to program operating parameters without resetting the DLL). To access the MR, set BA0 and BA1 LOW; remaining MR bits must be set to desired settings. See “Mode Register (MR)” on page 7 for all MR requirements. 12. Issue a LOAD MODE command to the EMR to enable OCD default by setting bits E7, E8, and E9 to “1,” and then setting all other desired parameters. To access the EMR, set BA0 LOW and BA1 HIGH (see “Extended Mode Register (EMR)” on page 10 for all EMR requirements). 13. Issue a LOAD MODE command to the EMR to enable OCD exit by setting bits E7, E8, and E9 to “0,” and then setting all other desired parameters. To access the extended mode registers, EMR, set BA0 LOW and BA1 HIGH for all EMR requirements. 14. The DDR2 SDRAM is now initialized and ready for normal operation 200 clock cycles after the DLL RESET at Tf0. 15. DM represents UDM, LDM collectively for each die x16 configuration. DQS represents UDQS, USQS, LDQS, LDQS for each die x16 configuration. DQ represents DQ0-DQ15 for each die x16 configuration. 16. Wait a minimum of 400ns then issue a PRECHARGE ALL command.

Rev. 3.0 6/09 Austin Semiconductor, Inc. MODE REGISTER (MR) The mode register is used to define the specific mode of operation of the DDR2 SDRAM. This definition includes the selection of a burst length, burst type, CL, operating mode, DLL RESET, write recovery, and power-down mode, as shown in Figure 5. Contents of the mode register can be altered by re-executing the LOAD MODE (LM) command. If the user chooses to modify only a subset of the MR variables, all variables (M0–M14) must be programmed when the command is issued. The mode register is programmed via the LM command (bits BA2–BA0 = 0, 0,0) and other bits (M13–M0) will retain the stored information until it is programmed again or the device loses power (except for bit M8, which is selfclearing). Reprogramming the mode register will not alter the contents of the memory array, provided it is performed correctly. The LM command can only be issued (or reissued) when all banks are in the precharged state (idle state) and no bursts are in progress. The controller must wait the specified time tMRD before initiating any subsequent operations such as an ACTIVE command. Violating either of these requirements will result in unspecified operation. BURST LENGTH Burst length is defined by bits M0–M3, as shown in Figure 5. Read and write accesses to the DDR2 SDRAM are burst- oriented, with the burst length being programmable to either four or eight. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A2–Ai when BL = 4 and by A3–Ai when BL = 8 (where Ai is the most significant column address bit for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both READ and WRITE bursts. FIGURE 5 – MODE REGISTER (MR) DEFINITION BURST TYPE Accesses within a given burst may be programmed to be either sequential or interleaved. The burst type is selected via bit M3, as shown in Figure 5. The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address, as shown in Table 2. DDR2 SDRAM supports 4-bit burst mode and 8-bit burst mode only. For 8-bit burst mode, full interleave address ordering is supported; however, sequential address ordering is nibble-based. Burst Length CAS# BT PD A9 A7 A6 A5 A4 A3 A8 A2 A1 A0 Mode Register (Mx) Address Bus 9 7 6 5 4 3 8 2 1 0 A10 A12 A11 BA0 BA1 10 11 12 n 0 0 Burst Length Reserved Reserved Reserved Reserved Reserved Reserved Burst Type Sequential Interleaved CAS Latency (CL) Reserved Reserved Reserved Mode Normal Test DLL TM DLL Reset No Yes Write Recovery Reserved M10 M11 WR An2 MR M16 Mode Register Definition Mode register (MR) Extended mode register (EMR) Extended mode register (EMR2) Extended mode register (EMR3) M15 M12 PD Mode Fast exit (normal) Slow exit (low power) Latency BA21 Notes: 1.A13 Not used on this part, and must be programmed to ‘0’ on this part. 2.BA2 must be programmed to “0” and is reserved for future use.

Rev. 3.0 6/09 Austin Semiconductor, Inc. NOTES: 1. For a burst length of two, A1-Ai select two-data-element block; A0 selects the starting column within the block. 2. For a burst length of four, A2-Ai select four-data-element block; A0-1 select the starting column within the block. 3. For a burst length of eight, A3-Ai select eight-data-element block; A0-2 select the starting column within the block. 4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. TABLE 2 - BURST DEFINITION OPERATING MODE The normal operating mode is selected by issuing a command with bit M7 set to “0” and all other bits set to the desired values, as shown in Figure 5. When bit M7 is “1,” no other bits of the mode register are programmed. Programming bit M7 to “1” places the DDR2 SDRAM into a test mode that is only used by the manufacturer and should not be used. No operation or functionality is guaranteed if M7 bit is “1.” Type = Sequential Type = Interleaved A1 A0 A2 A1 A0 Order of Accesses Within a Burst Burst Length Starting Column Address DLL RESET DLL RESET is defined by bit M8, as shown in Figure 5. Programming bit M8 to “1” will activate the DLL RESET function. Bit M8 is self-clearing, meaning it returns back to a value of “0” after the DLL RESET function has been issued. Anytime the DLL RESET function is used, 200 clock cycles must occur before a READ command can be issued to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in a violation of the tAC or tDQSCK parameters. WRITE RECOVERY Write recovery (WR) time is defined by bits M9-M11, as shown in Figure 5. The WR register is used by the DDR2 SDRAM during WRITE with auto precharge operation. During WRITE with auto precharge operation, the DDR2 SDRAM delays the internal auto precharge operation by WR clocks (programmed in bits M9-M11) from the last data burst. WR values of 2, 3, 4, 5, 6 or 7 clocks may be used for programming bits M9-M11. The user is required to program the value of WR, which is calculated by dividing tWR (in ns) by tCK (in ns) and rounding up a non integer value to the next integer; WR [cycles] = tWR [ns] / tCK [ns]. Reserved states should not be used as unknown operation or incompatibility with future versions may result. POWER-DOWN MODE Active power-down (PD) mode is defined by bit M12, as shown in Figure 5. PD mode allows the user to determine the active power-down mode, which determines performance versus power savings. PD mode bit M12 does not apply to precharge PD mode. When bit M12 = 0, standard active PD mode or “fast-exit” active PD mode is enabled. The tXARD parameter is used for fast-exit active PD exit timing. The DLL is expected to be enabled and running during this mode. When bit M12 = 1, a lower-power active PD mode or “slowexit” active PD mode is enabled. The tXARD parameter is used for slow-exit active PD exit timing. The DLL can be enabled, but “frozen” during active PD mode since the exit-to-READ command timing is relaxed. The power difference expected between PD normal and PD low-power mode is defined in the I CC table.

Rev. 3.0 6/09 Austin Semiconductor, Inc. CAS LATENCY (CL) The CAS latency (CL) is defined by bits M4-M6, as shown in Figure 5. CL is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The CL can be set to 3, 4, 5, 6 or 7 clocks, depending on the speed grade option being used. DDR2 SDRAM does not support any half-clock latencies. Reserved states should not be used as unknown operation or incompatibility with future versions may result. DDR2 SDRAM also supports a feature called posted CAS additive latency (AL). This feature allows the READ command to be issued prior to tRCD (MIN) by delaying the internal command to the DDR2 SDRAM by AL clocks. Examples of CL = 3 and CL = 4 are shown in Figure 6; both assume AL = 0. If a READ command is registered at clock edge n, and the CL is m clocks, the data will be available nominally coincident with clock edge n+m (this assumes AL = 0). FIGURE 6 - CAS LATENCY (CL) Notes: 1. BL = 4. 2. Posted CAS# additive latency (AL) = 0. 3. Shown with nominal tAC, tDQSCK, and tDQSQ. DO n + 3 DO n + 2 DO n + 1 CK CK# Command DQ DQS, DQS# CL = 3 (AL = 0) READ T0 T1 T2 Don’t careTransitioning data NOP NOP NOP DO n T3 T4 T5 NOP NOP NOP DO n + 3 DO n + 2 DO n + 1 CK CK# Command DQ DQS, DQS# CL = 4 (AL = 0) READ T0 T1 T2 NOP NOP NOP DO n T3 T4 T5 NOP NOP NOP

Rev. 3.0 6/09 Austin Semiconductor, Inc. FIGURE 7 – EXTENDED MODE REGISTER DEFINITION EXTENDED MODE REGISTER (EMR) The extended mode register controls functions beyond those controlled by the mode register; these additional functions are DLL enable/disable, output drive strength, on die termination (ODT) (RTT), posted AL, off-chip driver impedance calibration (OCD), DQS# enable/disable, RDQS/RDQS# enable/disable, and output disable/enable. These functions are controlled via the bits shown in Figure 7. The EMR is programmed via the LOAD MODE (LM) command and will retain the stored information until it is programmed again or the device loses power. Reprogramming the EMR will not alter the contents of the memory array, provided it is performed correctly. The EMR must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time tMRD before initiating any subsequent operation. Violating either of these requirements could esult in unspecified operation. DLL Posted CAS# RTTOut A9 A7 A6 A5 A4 A3 A8 A2 A1 A0 Extended mode register (Ex) Address bus 97 6 5 4 382 1 0 A10 A12 A11 BA0 BA1 101112n Output Drive Strength Full Reduced Posted CAS# Additive Latency (AL) Reserved DLL Enable Enable (normal) Disable (test/debug) E11 RDQS Enable No Yes OCD Program An2 ODS RTTDQS# E10 DQS# Enable Enable Disable RDQS RTT (Nominal) RTT disabled 75: 150: 50: Outputs Enabled Disabled E12 Mode Register Set Mode register (MR) Extended mode register (EMR) Extended mode register (EMR2) Extended mode register (EMR3) E15 E14 MRS BA21 OCD Operation OCD exit Reserved Reserved Reserved Enable OCD defaults Notes: 1.During initialization, all three bits must be set to “1” for OCD default state, then must be set to “0” before initialization is finished, as detailed in the initialization procedure. 2.E13 (A13) must be programmed to “0” and is reserved for future use. 3.E16 must be programmed to “0” and is reserved for future use. 4.Not all AL options are supported in any individual speed grade. (100%) (40-60%)

Figure 7. The normal drive strength for all outputs are to approximately 45-60 percent of the SSTL_18 drive strength. point-to-point environments. CC characterization of read current. incompatibility with future versions may result. Timing” section for ODT timing diagrams.

Rev. 3.0 6/09 Austin Semiconductor, Inc. POSTED CAS ADDITIVE LATENCY (AL) Posted CAS additive latency (AL) is supported to make the command and data bus efficient for sustainable bandwidths in DDR2 SDRAM. Bits E3–E5 define the value of AL, as shown in Figure 7. Bits E3–E5 allow the user to program the DDR2 SDRAM with an inverse AL of 0, 1, 2, 3, 4, 5 or 6 clocks. Reserved states should not be used as unknown operation or incompatibility with future versions may result. In this operation, the DDR2 SDRAM allows a READ or WRITE command to be issued prior to tRCD (MIN) with the requirement that AL = tRCD (MIN). A typical application using this feature would set AL = tRCD (MIN) - 1x tCK. The READ or WRITE command is held for the time of the AL before it is issued internally to the DDR2 SDRAM device. RL is controlled by the sum of AL and CL; RL = AL+CL. Write latency (WL) is equal to RL minus one clock; WL = AL + CL - 1 x tCK. FIGURE 8 - EXTENDED MODE REGISTER 2 (EMR2) DEFINITION A9 A7 A6 A5 A4 A3 A8 A2 A1 A0 Extended mode register (Ex) Address bus 97 6 5 4 382 1 0 A10 A12 A11 BA0 BA1 101112n 1415 An2 E14 Mode Register Set Mode register (MR) Extended mode register (EMR) Extended mode register (EMR2) Extended mode register (EMR3) E15 MRS 0 0 0 0 0 SRT 0 0 0 0 0 0 0 BA21 SRT Enable 1X refresh rate (0°C to 85°C) 2X refresh rate (>85°C) Notes: 1.E16 bit (BA2) must be programmed to “0” and is reserved for future use. 2.Mode bits (En) with corresponding address balls (An) greater than A12 are reserved for future use and must be programmed to “ 0.”

Rev. 3.0 6/09 Austin Semiconductor, Inc. EXTENDED MODE REGISTER 2 The extended mode register 2 (EMR2) controls functions beyond those controlled by the mode register. Currently all bits in EMR2 are reserved, as shown in Figure 8. The EMR2 is programmed via the LM command and will retain the stored information until it is programmed again or the device loses power. Reprogramming the EMR will not alter the contents of the memory array, provided it is performed correctly. EMR2 must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time tMRD before initiating any subsequent operation. Violating either of these requirements could result in unspecified operation. EXTENDED MODE REGISTER 3 The extended mode register 3 (EMR3) controls functions beyond those controlled by the mode register. Currently, all bits in EMR3 are reserved, as shown in Figure 9. The EMR3 is programmed via the LM command and will retain the stored information until it is programmed again or the device loses power. Reprogramming the EMR will not alter the contents of the memory array, provided it is performed correctly. EMR3 must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specifi ed time tMRD before initiating any subsequent operation. Violating either of these requirements could result in unspecified operation. COMMAND TRUTH TABLES The following tables provide a quick reference of DDR2 SDRAM available commands, including CKE power-down modes, and bank-to-bank commands. FIGURE 9 - EXTENDED MODE REGISTER 3 (EMR3) DEFINITION E14 Mode Register Set Mode register (MR) Extended mode register (EMR) Extended mode register (EMR2) Extended mode register (EMR3) E15 A9 A7 A6 A5 A4 A3A8 A2 A1 A0 Extended mode register (Ex) Address bus 97 6 5 4 382 1 0 A10A12 A11BA0BA1 101112n 1415 An2 MRS 0 0 0 0 0 0 0 0 0 0 0 0 0 BA21 Notes: 1.Mode bits (En) with corresponding address balls (An) greater than A12 are reserved for future use and must be programmed to “ 0.” 2.E16 (BA2) must be programmed to “0” on this device and is reserved for future use.

Rev. 3.0 6/09 Austin Semiconductor, Inc. TABLE 3 - TRUTH TABLE - DDR2 COMMANDS Note: 1. All DDR2-SDRAM commands are defined by staes of CS#, RAS#, CAS#, WE#, and CKE a the rising edge of the clock. 2. Bank addresses (BA) BA2-BA0 determine which bank is to be operated upon. BA during a LM command selects which mode register is programmed. 3. Burst reads or writes at BL=4 cannot be terminated or interrupted. 4. The power down mode does not perform any REFRESH operations. The duration of power down is therefore limited by the refresh requirements outlined in the AC parametric section. 5. The state of ODT does not effect the states described in this table. The ODT function is not available during self refresh. See “On Die Termination (ODT)” for details. 6. “X” means “H or L” (but a defined logic level) 7. Self refresh exit is asynchronous. BA0 A11 LOAD MODE H HLLLL B A 2 REFRESH H H LLLHXXXX SELF-REFRESH Entry H L LLLHXXXX HXXX LHHH Single Bank Precharge HHL L H L X X L X 2 All banks PRECHARGE HHL L H L X X H X Bank Activate HHL L H L B A WRITE HHL L H L B A Column Address L Column Address 2,3 WRITE with auto precharge HHL H L L B A Column Address H Column Address 2,3 READ H H LHLH B A Column Address L Column Address 2,3 READ with auto precharge H H LHLH B A Column Address L Column Address 2,3 NO OPERATION H X LHHHXXXX Device DESELECT H X HXXXXXXX HXXX LHHH HXXX LHHH Function CS# RAS# A10 A9-A0 NotesPrevious Cycle Current Cycle CAS# WE# BA2 thru A12 CKE POWER-DOWN exit L H XXXX4 POWER-DOWN entry H L XXXX4 7SELF-REFRESH exit LH X OP CODE ROW ADDRESS XXX

Rev. 3.0 6/09 Austin Semiconductor, Inc. DESELECT The DESELECT function (CS# HIGH) prevents new commands from being executed by the DDR2 SDRAM. The DDR2 SDRAM is effectively deselected. Operations already in progress are not affected. NO OPERATION (NOP) The NO OPERATION (NOP) command is used to instruct the selected DDR2 SDRAM to perform a NOP (CS# is LOW; RAS#, CAS#, and WE are HIGH). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. LOAD MODE (LM) The mode registers are loaded via inputs BA2–BA0, and A12–A0. BA2–BA0 determine which mode register will be programmed. See “Mode Register (MR)”. The LM command can only be issued when all banks are idle, and a subsequent execute able command cannot be issued until tMRD is met. BANK/ROW ACTIVATION ACTIVE COMMAND The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA2–BA0 inputs selects the bank, and the address provided on inputs A12–A0 selects the row. This row remains active (or open) for accesses until a PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank. ACTIVE OPERATION Before any READ or WRITE commands can be issued to a bank within the DDR2 SDRAM, a row in that bank must be opened (activated), even when additive latency is used. This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated. After a row is opened with an ACTIVE command, a READ or WRITE command may be issued to that row, subject to the tRCD specification. tRCD (MIN) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVE command on which a READ or WRITE command can be entered. The same procedure is used to convert other specification limits from time units to clock cycles. For example, a tRCD (MIN) specification of 20ns with a 266 MHz clock ( tCK = 3.75ns) results in 5.3 clocks, rounded up to 6. A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous active row has been closed (precharged). The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. The minimum time interval between successive ACTIVE commands to different banks is defined by tRRD. FIGURE 10 - ACTIVE COMMAND CK# CK CKE CS# RAS# CAS# WE# ADDRESS BANK ADDRESS Row Bank DON’T CARE

Rev. 3.0 6/09 Austin Semiconductor, Inc. READ COMMAND The READ command is used to initiate a burst read access to an active row. The value on the BA2–BA0 inputs selects the bank, and the address provided on inputs A0–i (where i = A9) selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the READ burst; if auto precharge is not selected, the row will remain open for subsequent accesses. READ OPERATION READ bursts are initiated with a READ command. The starting column and bank addresses are provided with the READ command and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row being accessed is automatically precharged at the completion of the burst. If auto precharge is disabled, the row will be left open after the completion of the burst. During READ bursts, the valid data-out element from the starting column address will be available READ latency (RL) clocks later. RL is defined as the sum of AL and CL; RL = AL + CL. The value for AL and CL are programmable via the MR and EMR commands, respectively. Each subsequent data- out element will be valid nominally at the next positive or negative clock edge (i.e., at the next crossing of CK and CK#). DQS/DQS# is driven by the DDR2 SDRAM along with output data. The initial LOW state on DQS and HIGH state on DQS# is known as the read preamble ( tRPRE). The LOW state on DQS and HIGH state on DQS# coincident with the last data- out element is known as the read postamble ( tRPST). Upon completion of a burst, assuming no other commands have been initiated, the DQ will go High-Z. Data from any READ burst may be concatenated with data from a subsequent READ command to provide a continuous flow of data. The first data element from the new burst follows the last element of a completed burst. The new READ command should be issued x cycles after the first READ command, where x equals BL / 2 cycles. CK RAS# WE# ADDRESS A BANK ADDRESS Col Bank ENABLE DISABLE A10 CK# CKE CS# CAS# UTO PRECHARGE DON’T CARE FIGURE 11 - READ COMMAND

Rev. 3.0 6/09 Austin Semiconductor, Inc. WRITE COMMAND The WRITE command is used to initiate a burst write access to an active row. The value on the BA2–BA0 inputs selects the bank, and the address provided on inputs A0–9 selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the WRITE burst; if auto precharge is not selected, the row will remain open for subsequent accesses. Input data appearing on the DQ is written to the memory array subject to the DM input logic level appearing coincident with the data. If a given DM signal is registered LOW, the corresponding data will be written to memory; if the DM signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that byte/column location. WRITE OPERATION WRITE bursts are initiated with a WRITE command, as shown in Figure 12. DDR2 SDRAM uses WL equal to RL minus one clock cycle [WL = RL - 1CK = AL + (CL - 1CK)]. The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic WRITE commands used in the following illustrations, auto precharge is disabled. During WRITE bursts, the first valid data-in element will be registered on the first rising edge of DQS following the WRITE command, and subsequent data elements will be registered on successive edges of DQS. The LOW state on DQS between the WRITE command and the first rising edge is known as the write preamble; the LOW state on DQS following the last data-in element is known as the write postamble. The time between the WRITE command and the fi rst rising DQS edge is WL ± tDQSS. Subsequent DQS positive rising edges are timed, relative to the associated clock edge, as ± tDQSS. tDQSS is specified with a relatively wide range (25 percent of one clock cycle). All of the WRITE diagrams show the nominal case, and where the two extreme cases ( tDQSS [MIN] and tDQSS [MAX]) might not be intuitive, they have also been included. Upon completion of a burst, assuming no other commands have been initiated, the DQ will remain High-Z and any additional input data will be ignored. Data for any WRITE burst may be concatenated with a subsequent WRITE command to provide continuous flow of input data. The fi rst data element from the new burst is applied after the last element of a completed burst. The new WRITE command should be issued x cycles after the first WRITE command, where x equals BL/2. DDR2 SDRAM supports concurrent auto precharge options, as shown in Table 4. DDR2 SDRAM does not allow interrupting or truncating any WRITE burst using BL = 4 operation. Once the BL = 4 WRITE command is registered, it must be allowed to complete the entire WRITE burst cycle. However, a WRITE (with auto precharge disabled) using BL = 8 operation might be interrupted and truncated ONLY by another WRITE burst as long as the interruption occurs on a 4-bit boundary, due to the 4 n prefetch architecture of DDR2 SDRAM. WRITE burst BL = 8 operations may not to be interrupted or truncated with any command except another WRITE command. Data for any WRITE burst may be followed by a subsequent READ command. The number of clock cycles required to meet tWTR is either 2 or tWTR/tCK, whichever is greater. Data for any WRITE burst may be followed by a subsequent PRECHARGE command. tWT starts at the end of the data burst, regardless of the data mask condition.

Rev. 3.0 6/09 Austin Semiconductor, Inc. FIGURE 12 - WRITE COMMAND CK RAS# WE# HIGH ADDRESS EN AP CA A10 DIS AP BANK ADDRESS BA Note: CK# CKE CS# CAS# DON’T CARE CA = column address; BA = bank address; EN AP = enable auto precharge; and DIS AP = disable auto precharge. TABLE 4 - WRITE USING CONCURRENT AUTO PRECHARGE READ OR READ w/ AP (CL-1) + (BL/2) + tWTR tCK WRITE OR WRITE w/ AP (BL/2) tCK PRECHARGE or ACTIVE 1 tCK UnitsFrom Command (Bank n) WRITE with Auto Precharge To Command (Bank m) Minimum Delay (With Concurrent Auto Precharge)

Rev. 3.0 6/09 Austin Semiconductor, Inc. PRECHARGE COMMAND The PRECHARGE command, illustrated in Figure 13, is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row activation a specified time ( tRP) after the PRECHARGE command is issued, except in the case of concurrent auto precharge, where a READ or WRITE command to a different bank is allowed as long as it does not interrupt the data transfer in the current bank and does not violate any other timing parameters. Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. A PRECHARGE command is allowed if there is no open row in that bank (idle state) or if the previously open row is already in the process of precharging. However, the precharge period will be determined by the last PRECHARGE command issued to the bank. PRECHARGE OPERATION Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA2–BA0 select the bank. Otherwise BA2–BA0 are treated as “Don’t Care.” When all banks are to be precharged, inputs BA2–BA0 are treated as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. tRPA timing applies when the PRECHARGE (ALL) command is issued, regardless of the number of banks already open or closed. If a single-bank PRECHARGE command is issued, tRP timing applies. SELF REFRESH COMMAND The SELF REFRESH command can be used to retain data in the DDR2 SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the DDR2 SDRAM retains data without external clocking. All power supply inputs (including V REF) must be maintained at valid levels upon entry/exit and during SELF REFRESH operation. The SELF REFRESH command is initiated like a REFRESH command except CKE is LOW. The DLL is automatically disabled upon entering self refresh and is automatically enabled upon exiting self refresh (200 clock cycles must then occur before a READ command can be FIGURE 13 – PRECHARGE COMMAND issued). The differential clock should remain stable and meet tCKE specifications at least 1 x tCK after entering self refresh mode. All command and address input signals except CKE are “Don’t Care” during self refresh. The procedure for exiting self refresh requires a sequence of commands. First, the differential clock must be stable and meet tCK specifications at least 1 x tCK prior to CKE going back HIGH. Once CKE is HIGH ( tCLE(MIN) has been satisfied with four clock registrations), the DDR2 SDRAM must have NOP or DESELECT commands issued for tXSNR because time is required for the completion of any internal refresh in progress. A simple algorithm for meeting both refresh and DLL requirements is to apply NOP or DESELECT commands for 200 clock cycles before applying any other command. Note: Self refresh not available at military temperature. CK# CK CKE WE# A10 BA ONE BANK BA2, BA0 DON’T CARE Note: CS# RAS # CAS # HIGH ADDRE SS ALL BANKS BA = bank address (if A10 is LOW; otherwise "Don't Care").

Rev. 3.0 6/09 Austin Semiconductor, Inc. RESET FUNCTION (CKE LOW Anytime) DDR2 SDRAM applications may go into a reset state anytime during normal operation. If an application enters a reset condition, CKE is used to ensure the DDR2 SDRAM device resumes normal operation after reinitializing. All data will be lost during a reset condition; however, the DDR2 SDRAM device will continue to operate properly if the following conditions outlined in this section are satisfied. The reset condition defined here assumes all supply voltages (V DD, VDDQ and V REF) are stable and meet all DC specifications prior to, during, and after the RESET operation. All other input pins of the DDR2 SDRAM device are a “Don’t Care” during RESET with the exception of CKE. If CKE asynchronously drops LOW during any valid operation (including a READ or WRITE burst), the memory controller must satisfy the timing parameter tDELAY before turning off the clocks. Stable clocks must exist at the CK, CK# inputs of the DRAM before CKE is raised HIGH, at which time the normal initialization sequence must occur. The DDR2 SDRAM device is now ready for normal operation after the initialization sequence.

Rev. 3.0 6/09 Austin Semiconductor, Inc. Parameter Symbol Units Notes Supply Voltage VCC V I/O Reference Voltage VREF V1 I/O Termination Voltag VTT V2 MIN TYP MAX 1.7 1.8 1.9 VREF 0.51 x VCC VREF + 0.04 0.49 x VCC VREF - 0.04 0.50 x VCC DC OPERATING CONDITIONS 1. VREF is expected to equal VCC/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on V REF may not exceed ± 1 percent of the DC value. Peak-to- peak AC noise on VREF may not exceed ±2 percent of VREF. This measurement is to be taken at the nearest VREF bypass capacitor. 2. VTT is not applied directly to the device. V TT is a system supply for signal termination resistors, is expected to be set equal to V REF and must track variations in the DC level of VREF. ABSOLUTE MAXIMUM RATINGS Min Max Unit -1.0 2.3 V -0.5 2.3 V -55.0 125.0 oC -55.0 125.0 oC -5 5 uA -10 10 uA Voltage on any pin relative to V SS Storage Temperature RAS\\, CAS\\, WE\\, CS\\, CKE, DM, DQS, DQS\\, RDQS Device Operating Temperature uA uA uADM -10.0 10.0 5u A TCASE ADDR, BAx CK, CK\\ IVREF II Input Leakage current; Any input 0V<VIN<VCC; VREF = .5XVCC; Other balls not under test = 0V VREF Leakage Current IOZ OV ” VOUT ” VDD, DQ & ODT Disabled Symbol Parameter VCC VIN, VOUT TSTG Voltage on VCC pin relative to V SS INPUT / OUTPUT CAPACITANCE TA = 25oC, f = 1 MHz, VCC = 1.8V Parameter Symbol Max Unit Input capacitance (A0-A12, BA0-BA2, CS\\, RAS\\, CAS\\, WE\\, CKE, ODT) CADDR 25 pF Input capacitance CK, CK# CIN2 8p F Input capacitance DM, DQS, DQS# CIN3 10 pF Input capacitance DQ0-71 COUT 12 pF

Rev. 3.0 6/09 Austin Semiconductor, Inc. INPUT DC LOGIC LEVEL All voltages referenced to Vss Parameter Symbol Min Max Unit AC Input High (Logic 1) Voltage DDR2-400 & DDR2-533 VIH (AC) V REF + 0.250 V CC+0.3001 V AC Input High (Logic 1) Voltage DDR2-667 VIH (AC) V REF + 0.200 V CC+0.3001 V ACInput Low (Logic 0) Voltage DDR2-400 & DDR2-533 VIL (AC) -0.3 VREF - 0.250 V AC Input Low (Logic 0) Voltage DDR2-667 VIL (AC) -0.3 VREF - 0.200 V Note 1: 300mV is allowed provided Vcc does not exceed 1.9V Parameter Symbol Min Max Unit Input High (Logic 1) Voltage VIH (DC) V REF + 0.125 V CC + 0.3001 V Input Low (Logic 0) Voltage VIL (DC) -0.300 VREF - 0.125 V Note 1: 300mV is allowed provided Vcc does not exceed 1.9V INPUT AC LOGIC LEVEL All voltages referenced to Vss

Rev. 3.0 6/09 Austin Semiconductor, Inc. DDRII ICC SPECIFICATIONS AND CONDITIONS Parameter Symbol Units Operating Current: One bank active-precharge Precharge POWER-DOWN current Precharge quiet STANDBY current Precharge STANDBY current Active POWER-DOWN curren t Active STANDBY current Operating Burst WRITE current Operating Burst READ current Burst REFRESH current Self REFRESH current Operating bank Interleave READ current: 1700 1600 mA 1500 mA 1250 1100 1000 mA 250 200 mA 850 700 600 mA 300 All banks open; tCK=tCK(ICC), tRAS MAX(ICC), tRP=tRP(ICC); CKE is HIGH, CS\\ is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching ICC5 ICC6CK and CK\\ at 0V; CKE </=0.2V; Other contro, address and data inputs are floating ICC3N ICC4W ICC4R ICC7 All banks idle; tCK-=tCK(ICC); CKE is HIGH, CS\\ is HIGH; Other control and address bus inputs are switching; Data bus inputs are switching 600 MRS[12]=1 330 50 50 250 275 220 mA 150 ICC2QAll banks idle; tCK=tCK(ICC); CKE is HIGH, CS\\ is HIGH; Other control and address bus inputs are stable; Data bus inputs are floating ICC2N ICC3PAll banks open; tCK=tCK(ICC); CKE is LOW; Other control and address inputs are stable; Data bus inputs are floating 300 MRS[12]=0 125 115 -38 660 600 750 Operating Current: One bank active-READ-precharge current ICC1 All banks idle; tCK-tCK(ICC); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating ICC0 ICC2P tCL=tCK(ICC), tRC=tRC(ICC), tRAS=tRAS MIN(ICC); CKE is HIGH, CS\\ is HIGH between valid commands; Address bus switching, Data bus switching IOUT=0ma; BL=4, CL=CL(ICC), AL=0; tCK = tCK(ICC), tRC- tRC(ICC), tRAS=tRAS MIN(ICC), tRCD=tRCD(ICC); CKE is HIGH, CS\\ is HIGH between valid commands; Address bus is switching; Data bus is switching 550 mA650 mA mA mA mA195 All banks open, continuous burst writes; BL=4, CL=CL(ICC), tRP=tRP(ICC); CKE is HIGH, CS\\ is HIGH betwwn valid commands; Address bus inputs are switching; Data bus All banks open, continuous burst READS, Iout=0mA; BL=4, CL=CL(ICC), AL=0; tCL=tCK(ICC), tRAS=tRAS MAX(ICC), tRP=tRP(ICC); CKE is HIGH, CS\\ is HIGH betwwn valid commands; Address and Data bus inputs switching 850 700 All bank interleaving READS, IOUT = 0mA; BL=4, CL=CL(ICC), AL=tRCD(ICC)-1xtCK(ICC); tCK=tCK(ICC), tRC=tRC(ICC), tRRD=tRRD(ICC); CKE is HIGH, CS\\ is HIGH between valid commands; Address bus inputs are stable during deselects; Data bus inputs are switching tCK=tCK(ICC); refresh command at every iRFC(ICC) interval; CKE is HIGH, CS\\ is HIGH Between valid commands; Address bus inputs are switching; Data bus inputs are switching 600

667 MHZ 533 MHZ 400 MHZ

Rev. 3.0 6/09 Austin Semiconductor, Inc. AC OPERATING SPECIFICATIONS -3 -38 -5 667MHz 533MHz 400MHz Parameter Symbol MIN MAX MIN MAX MIN MAX Units Clock Cycle Time CL=5 tCKAVG 38 n s CL=4 tCKAVG 3.75 8 3.75 8 5 8 ns CL=3 tCKAVG 585858 n s Half Clock Period Min of tHP tCH,tCL tCH,tCL tCH,tCL ps Clock Jitter - Period tJITPER -125 125 -125 125 -125 125 ps Clock Jitter - Half Period tJIT DUTY -125 125 -125 125 -150 150 ps Clock Jitter - Cycle to Cycle tJITCC ps Cumulative Jitter error, 2 Cycles tERR2PER -175 175 -175 175 -175 175 ps Cumulative Jitter error, 4 Cycles tERR4PER -250 250 -250 250 -250 250 ps Cumulative Jitter error, 6-10 Cycles tERR10PER -350 350 -350 350 -350 350 ps Cumulative Jitter error, 11-50 Cycles tERR50PER -450 450 -450 450 -450 450 ps DQ hold skew factor tQHS - 340 - 400 - 450 ps DQ output access time from CK/CK\\ tAC -450 450 -500 500 -600 600 ps Data-out High-Z window from CK/CK\\ tHZ tAC(MAX) tAC(MAX) tAC(MAX) ps DQS Low-Z window from CL/CK\\ tLZ1 tAC(MIN) tAC(MAX) tAC(MIN) tAC(MAX) tAC(MIN) tAC(MAX) ps DQ Low-Z window from CK/CK\\ tLZ2 2*tAC(MIN) tAC(MAX) 2*tAC(MIN) tAC(MAX) 2*tAC(MIN) tAC(MAX) ps DQ and DM input setup time relative to DQS tDSJEDEC 100 100 150 ps DQ and DM input hold time relative to DQS tDHJEDEC 175 225 275 ps DQ and DM input pulse width (for each input) tDIPW 0.35 0.35 0.35 tCK Data Hold skew factor tQHS 340 400 450 ps DQ-DQS Hold, DQS to first DQ to go non valid, per access tQH tHP-tQHS tHP-tQHS tHP-tQHS ps Data valid output window (DVW) tDVW tQH-tDQSQ tQH-tDQSQ tQH-tDQSQ ps DQS input-high pulse width tDQSH 0.35 0.35 0.35 tCK DQS input-low pulse width tDQSL 0.35 0.35 0.35 tCK DQS output access time from CK/CK\\ tDQSCK -400 400 -400 400 -450 450 ps DQS falling edge to CK rising - setup time tDSS 0.2 0.2 0.2 tCK DQS falling edge from CK rising-hold time tDSH 0.2 0.2 0.2 tCK DQS-DQ skew, DQS to last DQ valid, per group, per access tDQSQ 240 300 350 ps WRITE preamble setup time tWPRES 0 0 0 ps DQS WRITE preamble tWPRE 0.35 0.35 0.35 tCK WRITE command to first DQS latching transition WL-tDQSS WL+tDQSS WL-tDQSS WL+tDQSS WL-tDQSS WL+tDQSS tCK DATA Strobe Clock 250 Clock JitterDATA 250 250

Rev. 3.0 6/09 Austin Semiconductor, Inc. AC OPERATING SPECIFICATIONS (CONTINUED) -3 -38 -5 667Mbps 533Mbps 400Mbps Symbol MIN MAX MIN MAX MIN MAX Units Address and Control input puslse width for each input tIPW 0.6 0.6 0.6 tCK Address and Control input setup time tISJEDEC 200 250 350 ps Address and Control input hold time tIHJEDEC 275 375 475 ps CAS\\ to CAS\\ command delay tCCD 222 t C K ACTIVE to ACTIVE command (same bank) tRC 55 55 55 ns ACTIVE bank a to ACTIVE bank b Command tRRD 10 10 10 ns ACTIVE to READ or WRITE delay tRCD 15 15 15 ns 4-Bank activate period tFAW 50 50 50 ns ACTIVE to PRECHARGE tRAS 40 700001 40 700001 40 700001 ns Internal READ to PRECHARGE command delay tRTP 7.5 7.5 7.5 ns WRITE recovery time tWR 15 15 15 ns Auto PRECHARGE WRITE recovery+PRECHARGE time tDAL tWR + tRP tWR + tRP tWR + tRP ns Internal WRITE to READ command delay tWTR 7.5 7.5 10 ns PRECHARGE command period tRP 15 15 15 ns PRECHARGE ALL command period tRPA tRP+tCL tRP+tCL tRP+tCL ns LOAD MODE, command Cycle time tMRD 222 t C K CKE LOW to CK, CK\\ uncertainty tDELAY ns REFRESH to ACTIVE or REFRESH to REFRESH command Interval Average periodic REFRESH interval [Industrial temp] tREFI IT 7.8 7.8 7.8 us Average periodic REFRESH interval [Enhanced temp] tREFIET 5.9 5.9 5.9 us Average periodic REFRESH interval [Military temp] tREFIXT 3.9 3.9 3.9 us Exit SELF REFRESH to non READ command Exit SELF REFRESH to READ command Exit SELF REFRESH timing reference ODT turn-on delay tAOND 222222 t C K ODT turn-on delay tAOND tAC(min) tAC(max)+ 700 tAC(min) tAC(max)+ 1000 tAC(min) tAC(max)+ 1000 ps ODT turn-off delay tAOF tAC(min) tAC(max)+ 600 tAC(min) tAC(max)+ 600 tAC(min) tAC(max)+ 600 ps ODT turn-on (power-down mode) tAONPD tAC(min) + 2000 2 x tCK + tAC(max)+ 1000 tAC(min) + 2000 2 x tCK + tAC(max)+ 1000 tAC(min) + 2000 2 x tCK + tAC(max)+ 1000 ps ODT turn-off (power-down mode) tAOFPD tAC(min) + 2000 2.5 x tCK + tAC(max)+ 1000 tAC(min) + 2000 2.5 x tCK + tAC(max)+ 1000 tAC(min) + 2000 2.5 x tCK + tAC(max)+ 1000 ps ODT to power-down entry latency tANPD 3 3 3 tCK ODT power-down exit latency tAXPD 8 8 8 tCK ODT enable from MRS command tMOD 12 12 12 ns Exit active POWER-DOWN to READ command, MR[12]=0 tXARD 2 2 2 tCK Exit active POWER-DOWN to READ command, MR[12]=1 tSARDS 7 - AL 6 - AL 6 - AL tCK Exit PRECHARGE POWER-DOWN to any non READ tXP 2 2 2 tCK CKE Min. HIGH/LOW time tCLE 3 3 3 tCK Note 1: Max value reduced to 10,000ns at 125 oC COMMAND and ADDRESS 70000 1 REFRESHS. REFRESHODT tIS + tCL + tIH tRFC tXSNR tXSRD tISXR tRFC(min)+1 tRFC(min)+1 tIS + tCL + tIH tIS + tCL + tIH 127 70000 1 127 70000 1 127 PWRDN pstIS 200 tIS tIS Parameter 200 ns tCK ns 200 tRFC(min)+1

Rev. 3.0 6/09 Austin Semiconductor, Inc. MECHANICAL DIAGRAM

Rev. 3.0 6/09 Austin Semiconductor, Inc.

ORDERING INFORMATION

AS4DDR264M72PBG1-3/IT Consult Factory AS4DDR264M72PBG1-38/IT Consult Factory AS4DDR264M72PBG1-5/IT Consult Factory AS4DDR264M72PBG1-3/ET Consult Factory AS4DDR264M72PBG1-38/ET Consult Factory AS4DDR264M72PBG1-5/ET Consult Factory AS4DDR264M72PBG1-3/XT Consult Factory AS4DDR264M72PBG1-38/XT Consult Factory AS4DDR264M72PBG1-5/XT Consult Factory AS4DDR264M72PBG1R-3/IT Consult Factory AS4DDR264M72PBG1R-38/IT Consult Factory AS4DDR264M72PBG1R-5/IT Consult Factory AS4DDR264M72PBG1R-3/ET Consult Factory AS4DDR264M72PBG1R-38/ET Consult Factory AS4DDR264M72PBG1R-5/ET Consult Factory AS4DDR264M72PBG1R-3/XT Consult Factory AS4DDR264M72PBG1R-38/XT Consult Factory AS4DDR264M72PBG1R-5/XT Consult Factory IT = Industrial = Industrial class integrated component, fully operable across -40C to +85C ET = Enhanced = Enhanced class integrated component, fully operable across -40C to +105C XT = Military = Mil-Temperature class integrated component, fully operable across -55C to +125C Core Clock Freqency Data Clock Rate Device Grade 333MHz Industrial 266MHz Industrial 200MHZ 333MHz 266MHz 200MHZ 266MHz 200MHZ 333MHz 533Mbs 400Mbs 667Mbs 667Mbs 533Mbs 400Mbs 667Mbs 533Mbs 400Mbs Industrial Enhanced Enhanced Enhanced Military Military Military 266MHz 533Mbs Industrial - RoHS 333MHz 667Mbs Industrial - RoHS 200MHZ 400Mbs Industrial - RoHS 333MHz 667Mbs Enhanced - RoHS 266MHz 533Mbs Enhanced - RoHS 200MHZ 400Mbs Enhanced - RoHS 200MHZ 400Mbs Military - RoHS 333MHz 667Mbs Military - RoHS 266MHz 533Mbs Military - RoHS

Rev. 3.0 6/09 Austin Semiconductor, Inc. DOCUMENT TITLE 4.8Gb, 64M x 72, DDR2 SDRAM, 16mm x 23mm - 208 PBGA Multi-Chip Package [iPEM]

REVISION HISTORY

Rev # History Release Date Status

0.0 Initial Release January 2008 Advance

0.5 Updated Pinout May 2008 Advance

1.0 Revised part description (pg 1) May 2008 Preliminary

Revised typical weight (pg 1) Reference to compatible part

1.1 Added configuration addressing table September 2008 Preliminary

1.5 Updated Drawing December 2008 Preliminary

removed references to VCCQ

2.0 Updated Drawing January 2009 Preliminary

2.5 Updated Drawing April 2009 Preliminary

3.0 Updated Drawing* June 2009 Preliminary

*No overall dimensions changed. New product shipped after July 1, 2009 will be with the underfilled package. Changed “Extended” temp reference to “Military”