AS4C1024 | DigiCamel IC Datasheet

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ASI) AusTIN SEMICONDUCTOR, INC. AS4C1024 883C

1 MEG x1 DRAM

SPECIFICATIONS PIN ASSIGNMENT (Top View) + MIL-STD-883 18-Pin DIP FEATURES (D-6) * Industry standard pinout and timing (calm * All inputs, outputs and clocks are fully TTI wis “ls compatible als: ale + Single +5V410% power supply Mee oa bee * Low power, 5mW standby; 175mW active, typical pe een 9 + Optional PAGE MODE access cycle ale apa + Refresh modes: RAS-ONLY, CAS-BEFORE-RAS, and nly onda HIDDEN aan om pas + 512-cycle refresh distributed across &ms ve {s we)ae + Specifications guaranteed over full military temperature range (-85°C to +125°C) 20-Pin LCC OPTIONS MARKING eGcesg= * Timing od ete 80ns access -8 mc fis peated 100ns access -10 | 120ns access 12 | + Packages matin wefan Ceramic DIP (300 mil) C No. 101 aes Midas Ceramic LCC EC No. 202 See *Aekdress not used for RAS-ONLY REFRESH PAGE MODE operations allow faster data operations GENERAL DESCRIPTION (READ, WRITE or READ-MODIFY-WRITE) within a row The AG4C1024 883C is a randomly accessed solid-state address (A0 -A9) defined page boundary. The PAGE MODE, memory containing 1,048,576 bits organized in a x1-bit cycle is always initiated with a row address strobed-in by configuration. During READ or WRITE cycles, each bit is RAS followed by a column address strobed-in by CAS: uniquely addressed through the 20 address bits, which are CAS may be toggled-in by holding RAS LOW and strobing- entered 10 bits (AQ-AQ) at a time. RAS is used to latch the indifferent columnaddresses, thus executing fastermemory first 10 bits and CAS the latter 10 bits. A READ or WRITE cycles. Returning RAS HIGH terminates the PAGE MODE cycle is selected with the WE input. A logic HIGH on WE. operation. dictates READ mode while a logic LOW on WE dictates Returning RAS and CAS HIGH terminates a memory WRITE mode. During a WRITE cycle, data in (D) is latched cycleand decreases chip currentto a reduced standby level. by the falling edge of WE or CAS, whichever occurs last. If Also, the chip is preconditioned for the next cycle during the WE goes LOW prior to TAS going LOW, the output (Q) RASHIGH time. Memory cell data is retained in its correct remains open (High-Z) until the next CAS cycle. If WE goes state by maintaining power and executing any RAS cycle LOW after data reaches Q, Q is activated and retains the (READ, WRITE, RAS-ONLY, CAS-BEFORE-RAS, or HID: selected cell data as long as CAS remains LOW (regardless DEN refresh) so that all 512 combinations of RAS addresses. of WE or RAS). This late WE pulse results ina READ-WRITE. (A0-A8) are executed at least every 8ms, regardless of cycle. sequence. see Parl Tae Sankara Wo sane Ws Gorge ars Won WARE Eseosre

ASI) AusTIN SEMICONDUCTOR, INC. AS4C1024 883C ( 1 MEG x1 DRAM ABSOLUTE MAXIMUM RATINGS* *Stresses greater than those listed under “Absolute Maxi- Voltage on Any Pin Relative to Vss 15V to +7.0V mum Ratings” may cause permanent damage to the device. Storage Temperature Range BSC to +150°C This is a stress rating only and functional operation of the Power Dissipation ...cscsuemsautnunsnansnssesnes IW device at these or any other conditions above those indi Lead Temperature (eoldering 5 seconds) 270°C _cated in the operational sections of this specification is not Junction Temperature (Tj)... L175°C_ implied. Exposure to absolute maximum rating conditions ee Short Circuit Output CUTER .arnnninnmnnnn SOMA —_‘fOF extended perlods may affect reliability. ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS PARAMETER/CONDITION _ symBoL| MIN | MAX | UNITS | NOTES Supply Voltage - Voc | 45 | 55 | V Input Low (Logic 0) Voltage, All inputs Vi Vv INPUT LEAKAGE CURRENT Any Input OV s Vin s 6.5V h HA (All other pins not under test = OV) al: OUTPUT LEAKAGE CURRENT (Q is disabled, OV < Vour < 6.5V) [see Reed ee Gee | OUTPUT LEVELS Vou | 24 Vv Output High Voltage (lour = -5mA) Output Low Voltage (lout = 4.2mA) Vou v "PARAMETERICONDITION sympo | -8 | -10 | -12 [unis | notes | ‘STANDBY CURRENT: (TTL) tect 3] 3 | 3 | ma (RAS = TAS = Vix) e STANDBY CURRENT: (CMOS) tec2 1 [4 [ma (RAS = CAS = Voc -0.2V; all other inputs = Vcc -0.2V) és OPERATING CURRENT: Random READWRITE Average power supply current leca 80 | 70 | ma | 3,4 (RAS, CAS, Address Cycling: 'RC = "RC (MIN)) S OPERATING CURRENT: FAST PAGE MODE Average power supply current leca 70 | 60 | 50 | mA | 3,4 (RAS = Vi; CAS, Address Cycling: PC ='PC (MIN) REFRESH CURRENT: RAS-ONLY ‘Average power supply current lees 80/70 | ma | 3 (RAS Cycling; CAS = Vin: RC = 'RC (MIN)) REFRESH CURRENT: CAS-BEFORE-RAS Average power supply current lece 90 | 80} 70 | mA | 3,5 (RAS, CAS, Address Cycling: "RC = 'RG (MIN)) soG0018

ASI) austIN SEMICONDUCTOR, INC. AS4C1024 883C PARAMETER SYMBOL | max | units | Notes | Input Capacitance: A0-A9, D Ci [7 [| pr | 2 | es Input Capacitance: FAS, CAS, WE | ce [| | 7 | pe | 2 | Output Capacitance: Q [ co [| | 8 | pw | 2 | ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS AC CHARACTERISTICS 228 Pee er ey PARAMETER, | sym | MN MAX | min] max | unis |" nores_| Random READ or WRITE cycle time | TAC | 150 a a A READ-WAITE cycle time r= td a a | FAST-PAGE-MODE READ 45 65 beef moe of WRITE cycle time Petpet cycle time [AccesstimefromRAS na [| 80 a HT | [AccasstimetromCAS Teac || 20 eee | Accass time from column address [TAA | es ee Kd _40 Ce es ee RAS pulse width ["Ras | 80 | 100,000 | 100 | 100,000 [700,000[ ns |_| AS pulse width (FAST PAGE MODE) 30 | 100,000 | 100 _| 100,000 [100,000 | ns | | | RAShoidtime ins | 20 | 25 ed (el | RAS prechargetime ap [60 | _| 70 | aaa | eet = +- [CAS pulsewieth «cas [20 | 100,000 | 25 | v00,000| 30 | vo0,000 [ns [| i Bee Bes 100 El en Pe ee CAS precharge time 10 oe | Es Me CAS precharge time (FAST PAGE MODE)| ‘cP [10 fase MB LS cen on S| ane Speed Bo [eo = |e rs 26. eo fe ar | Bis ESOC Rand ee DS ees HT Row address hold time __[ RAH | 10 | aa aI BE] nS address delay time Column address setup time aso [On [of PO [ee [ew Column address hold time FS TF ME EEN I TA Wn Column address hold time TAR haa 70 Pee es (referenced to RAS) RAS lead time Rieadcommandsetuptime =| wos | 9 = To To 2 (referenced to TAS) Read command hold time 'RRH ss 19 eres Bees cla GAS to output in Low-2 [esouz! [702 Spooner |e eon] 88 ae Output buffer tum-off delay on oreo ao Onc) eon oi) aoc ire] ees] WE command setup time wes | 0 | ES SR OW a exo

i AUSTIN SEMICONDUCTOR, INC. AS4C1024 883C 1MEG x 1 DRAM ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS ee re ees ges ae PARAMETER SyM_|_MIN_| MAX _| MIN [ Max | MINT MAX | UNITS | NOTES| WRITE command hold time a | wee fs |_| _f as WRITE command hold time (referenced to RAS\\ ‘won | 60 | | 7o | | 80 | tae | [WRITE command pulsewidth | swe | 15 | | 20 | Tas | ns TO omen ——Cetet tet tet tet WRITE command to CAS\\ lead time Tow. | 20 | | 2 | | 30 | | ns | ‘| [Datainsetuptime | os | ol TCT oh [Uf co TU ns fe | Data-in hold time ToH | 16 | ao as ns Te [Data-in hold time referenced to RAS\\__ tpHR | 60 | | 70 | | 80 }-#8-| RAS\\ to WRITE delay [trawo | so | | too | _—*'|_‘120 [Column address toWE\\delaytime ———«i| AWD | 40 | | 60 | {60 [ ns {ai | ae eee eee ‘Transition time (rise or fall) {| 3 [| 5 | 3 | 50 | 3 [Refresh period (512 cycles) S| mer | ~~] 8 | CT 8 ST UT le} fl hms | RAS \\ to CAS\\ precharge time a tere fo ff {fo | _t = t ICAS\\ set-up time (CAS-BEFORE-RAS REFRESH) tcsa | 10 | | 10 | | 70 | | ns | 5 | ICAS\\hold time (CAS-BEFORE-RAS REFRESH) | ‘CHR | 15 | | 20 | [a5 | [ns [ 5 | WE\\ set-up time before RAS\\low __ [twee [io [to [To TT ns [9.10.11] ICAS\\ before RAS\\ refresh od 7eACI 024 BBC an Pe comme Tn a in nigindap miceweioaaeaiarnan Sone @ 2-15

ASL) AusTIN SEMICONDUCTOR, INC. AS4C1024 883C

All voltages referenced to Vss. 16. If CAS is LOW at the falling edge of RAS, Q will be 2. ‘This parameter is sampled, not 100% tested. Capaci- maintained from the previous cycle. To initiate a new tance is measured with Vcc = 5V, f = 1 MHz at less cycle and clear the data out buffer, CAS must be than 50mVrms; I’, = 25°C £3°C: Vbias = 2.4V applied pulsed HIGH for ‘CPN. od to each input and output individually with remaining 17. Operation within the "RCD (MAX) limit ensures that inputs and outputs open 'RAC (MAX) can be met. RCD (MAX) is specified as 3. Iec is dependent on cycle rates. a reference point only; if (RCD Is greater than the 4. Icc is dependent on output loading and cycle rates. specified 'RCD (MAX) limit, then access time is Specified values are obtained with minimum cycle controlled exclusively by ‘CAC. time and the output open. 18, Operation within the ‘RAD (MAX) limit ensures that 5. Enables on-chip refresh and address counters. 'RCD (MAX) can be met. ‘RAD (MAX) is specified as 6. ‘The minimum specifications are used only to indicate a reference point only; if RAD is greater than the cycle time at which proper operation over the full specified ‘RAD (MAX) limit, then access time is temperature range (-55°C < TS +125°C) is assured. controlled exclusively by ‘AA. 7. An initial pause of 100s is required after power-up 19. Either ‘RCH or 'RRH must be satisfied fora READ followed by any eight RAS refresh only cycles or CBR cycle. refresh cycle (WE\\ held high) before proper device 20. ‘OFF (MAX) defines the time at which the output operation is assured. achieves open circuit condition. ‘OFF (MAX) is not referenced to Vox or VoL. 8. AC characteristics assume transition time ('T) = 5ns. 21. 'WCS, 'RWD, ‘AWD and 'CWD are restrictive This parameter is not measured. operating parameters in late WRITE, READ-WRITE 9. Vim (MIN) and Vi (MAX) are reference levels for and READ-MODIFY-WRITE cycles only. If WCS = measuring timing of input signals. Transition times ‘WCS (MIN), the cycle is an early WRITE cycle and are measured between Vix and Vi. (or between ViL the data output will remain an open circuit through- and Vi) out the entire cycle. If 'RWD 2 'RWD (MIN), ‘AWD = 10. In addition to meeting the transition rate specifica- ‘AWD (MIN) and ‘CWD 2 ‘CWD (MIN), the cycle is a tion, all input signals must transit between Vit and READ-WRITE and the data output will contain data Vu. (or between Vu. and Vik) in a monotonic manner. read from the selected cell. If neither of the above 1. IFCAS = Vin, data output (Q) Is High-Z. conditions are met, the state of the Q (at access time 12. If CAS = Vit, Q may contain data from the last valid and until TAS goes back to Vu) is indeterminate. READ cycle. 22. These parameters are referenced to CAS leading edge 13. Measured with a load equivalent to 2 TTL gates and in early WRITE cycles and WE leading edge in late 100pF. WRITE or READ-WRITE cycles. 14, Assumes that ‘RCD <'RCD (MAX). 23, A HIDDEN REFRESH may also be performed after a 15. Assumes that ‘RCD 2 'RCD (MAX). WRITE cycle. In this case, WE = LOW. a 2-16 Tact Barkan Fo omnes Aft args ohn Re vO Ta

7) au: SEM TOR, INC AS4C1024 883C ASI) AUSTIN SEMICONDUCTOR, INC. {we x1 DRAM READ CYCLE ‘le He EARLY-WRITE CYCLE 3 =e “aj a [Doowr care BY unoeriveo

I) ; ; AS4C1024 883C ASI) AUSTIN SEMICONDUCTOR, INC. Ba a peg READ-WRITE CYCLE (LATE-WRITE and READ-MODIFY-WRITE CYCLES) mma Vet C , Some oe _ ome ve —+— ; a \\ | i soon Vet “7 on 8), a) WL UW FAST-PAGE-MODE READ CYCLE fo b— WA _ RSE ee aes ee ag ae Sees ine to cane pea recta NR,

I TIN SEMIC T AS4C1024 883C ASI) AUSTIN SEMICONDUCTOR, INC 4d REG 91 DR ARE FAST-PAGE-MODE EARLY-WRITE CYCLE = intimal — 2 ES - cas Yh OF 7 —] iF [ rh ae soon Vil 7) row ben { sai : Y Y DK se HIN come Ms = FAST-PAGE-MODE READ-WRITE CYCLE (LATE-WRITE and READ-MODIFY-WRITE CYCLES) = ee eee Ay a aT fea oe Ye OF is ff ; ene { \\ | ||, | ee sale “PC = LATE-WRITE cycle [Z] vont cane 'PRWC = FAST RMW cycle 0 unoerined fm a S| tL ght chang routs 9 aceon a nena,

7 1 3 Y ; AS4C1024 883C f ;:MICONDUCTOR, INC. ASI) AUSTIN SEMIC CTOR, IN ee Dae RAS-ONLY REFRESH CYCLE (ADDR = AO-A8; A9 and WE = DON’T CARE) ‘cre | nares poenanes lc ot vw = fa ———— k mpi CAS-BEFORE-RAS REFRESH CYCLE (AO-A9 and WE = DON'T CARE) ‘RPC Stern] tesgl |, toring) BES Lc he-'cin @ | OPEN, — gad Ly vag we WE TELL 7 X Wh HIDDEN REFRESH CYCLE 2° (WE = HIGH) oe we ZN VIII TL LL . Tse [oowr care RRQ unoerINe

AUSTIN SEMICONDUCTOR, INC. AS4C1024 883C ASI) 1MEGx1DRAM ELECTRICAL TEST REQUIREMENTS ; SUBGROUPS MIL-STD-883 TEST REQUIREMENTS (per Method 5005, Table |) INTERIM ELECTRICAL (PRE-BURN-IN) TEST PARAMETERS 2,8A, 10 ie : (Method 5004) =n FINAL ELECTRICAL TEST PARAMETERS, 1°, 2,3, 7°, 8,9, 10,11 (Method 5004) GROUP A TEST REQUIREMENTS | 1,2, 3,4", 7,8, 9, 10, 11 (Method 5005) a GROUP C AND D END-POINT ELECTRICAL PARAMETERS 1,2, 3, 7,8,9, 10,11 _ __ (Method 5005) ; * PDA applies to subgroups 1 and 7 ** Subgroup 4 shall be measured only for initial qualification and after process or design changes, which may affect input or output capacitance. Stone

Product Information

AS4C1024 specifications and overview.

Summary

FAST PAGE MODE REV. 10

Description

FAST PAGE MODE REV. 10

Source title AS4C1024 Datasheet(PDF) - Austin Semiconductor

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