AS3933 AMSCO | Alldatasheet
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Technical content
This product, formerly sold by ams AG, and before that optionally by either Applied Sensors GmbH, acam-messelectronic GmbH or Cambridge CMOS Sensors, is now owned and sold by ScioSense The technical content of this document under ams / Applied Sensors / acam- messelectronic / Cambridge CMOS Sensors is still valid. Contact information Headquarters: ScioSense B.V. High Tech Campus 10
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[v1-08] 2015-Sep-02 Document Feedback AS3933 3D Low Frequency Wake-Up Receiver The AS3933 is a 3-channel low power ASK receiver that is able to generate a wake-up upon detection of a data signal which uses a LF carrier frequency between 15-150 kHz. The integrated correlator can be used for detection of a programmable 16-bit or 32-bit Manchester wake-up pattern. The device can operate using one, two, or three active channels. The AS3933 provides a digital RSSI value for each active channel, it supports a programmable data rate and Manchester decoding with clock recovery. The AS3933 offers an internal Clock Generator, which is either derived from a crystal oscillator or the internal RC oscillator. The user can decide to use the external clock generator instead. The programmable features of AS3933 enable to optimize its settings for achieving a longer distance while retaining a reliable wake-up generation. The sensitivity level of AS3933 can be adjusted in presence of a strong field or in noisy environments. Antenna tuning is greatly simplified, as the automatic tuning feature ensures perfect matching to the desired carrier frequency. The device is available in 16-p in TSSOP and 16-LD QFN (4x4mm) packages, and DoW (dice on wafer). Ordering Information and Content Guide appear at end of datasheet. Key Benefits & Features The benefits and features of AS3933, 3D Low Frequency Wake-Up Receiver are listed below: Figure 1: Added Value of Using AS3933 Benefits Features
- Enables low power active tags • 3-channel ASK wake-up receiver
- Selectable carrier frequency • Carrier frequency range 15 – 150 kHz
- One, two, or three channel operation • 1-D, 2-D, or 3-D wake-up pattern detection
- Highly resistant to false wake-ups • 32-bit programmable wake-up pattern
- Improved immunity to false wake-ups • Supporting doubling of wake-up pattern
- Allows frequency only detection • Wake-up without pattern detection selectable
- Improved range with best-in-class sensitivit y • Wake-up sensitivity 80μVRMS (typ.) General Description
Document Feedback [v1-08] 2015-Sep-02 AS3933 − General Description
Applications
The AS3933, 3D Low Frequency Wake-Up Receiver is ideal for Active RFID tags, Real-time location systems, Operator identification, Access control, and Wireless sensors. Figure 2: AS3933 Typical Application Diagram with Crystal Oscillator
- Adjustable range • Sensitivity level adjustable
- Provides tracking of false wake-ups • False wake-up counter
- Ensures wake-up in a noise environment • Periodical forced wake-up supported (1s – 2h)
- Extended battery life • Current consumption in 3-channel listening mode 2.3 μA (typ.)
- Flexible clock configuration • RTC based 32 kHz XTAL, RC-OSC, or external clock
- Operates from a 3V battery • Operating supply range 2.4V – 3.6V (TA = 25°C)
- Industrial temperature range • Operation temperature range -40°C to 85°C Benefits Features XTAL CL CLCBAT TX TRANSMITTER VCC Transmitting Antenna X, Y, and Z Receiving Antennas VCC LF1P LF2P LF3P LFN VSS GND XIN XOUT WAKE DAT CL_DAT CS SCL SDI SDO AS3933
[v1-08] 2015-Sep-02 Document Feedback AS3933 − Pin Assignments Figure 7: QFN Pin Assignment (Top View) LF3P 7 Analog I/O Input antenna channel three LF2P 8 Input antenna channel two LF1P 9 Input antenna channel one LFN 10 Common ground for antenna one, two and three XIN 11 Crystal oscillator input XOUT 12 Crystal oscillator output VSS 13 Supply pad Substrate WAKE 14 Digital output Wake-up output IRQ DAT 15 Data output CL_DAT 16 Manchester recovered clock Pin Name Pin Number Pin Type Description AS3933 LF2P LFN LF3P CS DAT XIN SDI LF1P 5 6 7 8 13141516 XOUT VSS WAKE CL_DAT SCL SDO VCC GND
Document Feedback [v1-08] 2015-Sep-02 AS3933 − Pin Assignments Pin Description Figure 8: QFN-16 Pin Description Pin Name Pin Number Pin Type Description LF3P 1 Analog I/O Input antenna channel three LF2P 2 Input antenna channel two LF1P 3 Input antenna channel one LFN 4 Common ground for antenna one, two and three XIN 5 Crystal oscillator input XOUT 6 Crystal oscillator output VSS 7 Supply pad Substrate WAKE 8 Digital output Wake-up output IRQ DAT 9 Data output CL_DAT 10 Manchester recovered clock CS 11 Digital input Chip select SCL 12 SDI interface clock SDI 13 SDI data input SDO 14 Digital output / tristate SDI data output (tristate when CS is low) VCC 15 Supply pad Positive supply voltage GND 16 Negative supply voltage
[v1-08] 2015-Sep-02 Document Feedback AS3933 − Pin Assignments Dice On Wafer DoW Attributes:
- Wafer Diameter: 8”
- Process: 0.35μm
- Wafer Thickness: 725μm ± 15μm
- Scribe line: 80μm
- Chip Size: 2.070 x 1.700 mm
- Pad Size: 85 x 85 μm Figure 9: DoW Pad Assignment
Document Feedback [v1-08] 2015-Sep-02 AS3933 − Pin Assignments Figure 10: DoW Pad Description and Position Position Pad Name Center X (µm) Center Y (µm) Upper Side 1 GND 381.5 1532.5 2 GND 634.5 1532.5 3 VCC 817.5 1532.5 4 SDO 1000.5 1532.5 5 SDI 1230.5 1532.5 6 SCL 1417.5 1532.5 Right Side 1 CL_DAT 1902.5 257.5 2 CS 1902.5 1365.5 Bottom Side 1 XIN 648.35 94.5 2 XOUT 847.5 94.5 3 VSS 1203.5 87.5 4 WAKE 1387.5 87.5 5 DAT 1569.5 87.5 Left Side 1L F N 8 7 . 5 3 0 3 . 5 2L F 1 P 8 7 . 5 6 6 9 . 5 3 LF2P 87.5 1103.5 4 LF3P 87.5 1356.5
[v1-08] 2015-Sep-02 Document Feedback AS3933 − Absolute Maximum Ratings Stresses beyond those listed in Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated in Operating Conditions is not implied. Exposure to absolu te maximum rating conditions for extended periods may affect device reliability. Figure 11: Absolute Maximum Ratings Symbol Parameter Min Max Unit Note Electrical Parameters VDD DC supply voltage -0.5 5 V VIN Input pin voltage -0.5 5 V ISOURCE Input current (latch up immunity) -100 100 mA Norm: Jedec 78 Electrostatic Discharge ESD Electrostatic discharge ±2 kV Norm: MIL 883 E method 3015 (HBM) Continuous Power Dissipation Pt Total power dissipation (all supplies and outputs) 0.07 mW Temperature Ranges and Storage Conditions Tstrg Storage temperature -65 150 °C Tbody Package body temperature 260 °C Norm: IPC/JEDEC J-STD-020 The reflow peak soldering temperature (body temperature) is specified according IPC/JEDEC J-STD-020 “Moisture/Reflow Sensitivity Classification for Non-hermetic Solid State Surface Mount Devices”. RH NC Relative Humidity (non-condensing) 58 5 % MSL Moisture Sensitivity Level 3 Represents a maximum floor life time of 168h Absolute Maximum Ratings
[v1-08] 2015-Sep-02 Document Feedback AS3933 − Electrical Characteristics Figure 14: Electrical System Specifications Symbol Parameter Conditions Min Typ Max Unit Input Characteristics RIN AC Input Impedance at125kHz In case no antenna damper is set (R1<4> =0) 2M Ω F1max Maximum Input Frequency Band1 150 kHz F1min Minimum Input Frequency Band1 95 kHz F2max Maximum Input Frequency Band2 95 kHz F2min Minimum Input Frequency Band2 65 kHz F3max Maximum Input Frequency Band3 65 kHz F3min Minimum Input Frequency Band3 40 kHz F4max Maximum Input Frequency Band4 40 kHz F4min Minimum Input Frequency Band4 23 kHz F5max Maximum Input Frequency Band5 23 kHz F5min Minimum Input Frequency Band5 15 kHz Current Consumption I1CHRC Current Consumption in standard listening mode with one active channel and RC-oscillator as Clock Generator 3.1 μA I2CHRC Current Consumption in standard listening mode with two active channels and RC-oscillator as Clock Generator 4.6 μA
Document Feedback [v1-08] 2015-Sep-02 AS3933 − Electrical Characteristics I3CHRC Current Consumption in standard listening mode with three active channels and RC-oscillator as Clock Generator 6.1 μA I3CHSCRC Current Consumption in scanning mode with three active channels and RC-oscillator as Clock Generator 3.1 μA I3CHOORC Current Consumption in ON/OFF mode with three active channels and RC-oscillator as Clock Generator 11% Duty Cycle 2.3 μA 50% Duty Cycle 3.8 I3CHXT Current Consumption in standard listening mode with three active channels and crystal oscillator as Clock Generator 6.5 8.9 μA IDATA Current Consumption in Preamble detection / Pattern correlation / Data receiving mode (RC-oscillator) With 125 kHz carrier frequency and 1 kbps data-rate. No load on the output pins. 8.3 12 μA IBOOST Additional current consumption per channel if gain boost enabled 150 nA Input Sensitivity SENS1 Input Sensitivity on all channels in the Band1 With 125 kHz carrier frequency, chip in default mode, 4 half bits burst + 4 symbols preamble and single preamble detection 100 μVrms SENS1B Input Sensitivity on all channels in the Band1 with 3dB gain boost With 125 kHz carrier frequency, chip in default mode, 4 half bits burst + 4 symbols preamble and single preamble detection 80 μVrms SENS2 Input Sensitivity on all channels in the Band2 With 90 kHz carrier frequency, chip in default mode, 4 half bits burst + 4 symbols preamble and single preamble detection 100 μVrms Symbol Parameter Conditions Min Typ Max Unit
[v1-08] 2015-Sep-02 Document Feedback AS3933 − Electrical Characteristics SENS2B Input Sensitivity on all channels in the Band2 with 3dB gain boost With 90 kHz carrier frequency, chip in default mode, 4 half bits burst + 4 symbols preamble and single preamble detection 80 μVrms SENS3 Input Sensitivity on all channels in the Band3 With 60 kHz carrier frequency, chip in default mode, 4 half bits burst + 4 symbols preamble and single preamble detection 100 μVrms SENS3B Input Sensitivity on all channels in the Band3 with 3dB gain boost With 60 kHz carrier frequency, chip in default mode, 4 half bits burst + 4 symbols preamble and single preamble detection 80 μVrms SENS4B Input Sensitivity on all channels in the Band4 with 3dB gain boost With 30 kHz carrier frequency, chip in default mode, 4 half bits burst + 4 symbols preamble and single preamble detection 80 μVrms SENS5B Input Sensitivity on all channels in the Band5 with 3dB gain boost With 18 kHz carrier frequency, chip in default mode, 4 half bits burst + 4 symbols preamble and single preamble detection 80 μVrms Channel Settling Time TSAMP Amplifier settling time 250 μs Crystal Oscillator FXTAL Frequency Crystal dependent 25 32.768 45 kHz TXTAL Start-up Time 1 s IXTAL Current consumption 300 nA External Clock Source IEXTCL Current consumption 0.8 μA FEXTCL Frequency 25 45 kHz Symbol Parameter Conditions Min Typ Max Unit
Document Feedback [v1-08] 2015-Sep-02 AS3933 − Electrical Characteristics RC Oscillator FRCNCAL Frequency If no calibration is performed 25 32.768 45 kHz FRCCAL32 If calibration with 32.768 kHz reference signal is performed 31 32.768 34.5 FRCCALMAX Maximum achievable frequency after calibration 23.75 FRCCALMIN Minimum achievable frequency after calibration 45 TRC Start-up time From RC enable (R1<0> = 0) 1 s TCALRC Calibration time 65 Periods of reference clock IRC Current consumption 650 nA LC Oscillator FLCOMIN Minimum Frequency L=47mH (Premo: SDTR1103-0108+), C=2.3nF 15 kHz FLCO MAX Maximum Frequency L=7.2mH (Premo: SDTR1103-0720+), C=1nF 150 kHz RPARMIN Minimum Eq. Parallel 10 k Ω Tuning Caps LF1Ptuning Capacitance Maximum internal capacitance (in step of 1pF) on LF1P 31 pF LF2Ptuning Maximum internal capacitance (in step of 1pF) on LF2P 31 pF LF3Ptuning Maximum internal capacitance (in step of 1pF) on LF3P 31 pF Symbol Parameter Conditions Min Typ Max Unit
[v1-08] 2015-Sep-02 Document Feedback AS3933 − Detailed Description The AS3933 is a three-dimensional low power low-frequency wake-up receiver. The AS3933 is capable of detecting the presence of an inductive coupled carrier and can extract the envelope of the ON-OFF-Keying (OOK) modulated carrier. In case the carrier is Manchester co ded, the clock can be recovered from the received signal and the data can be correlated with a programmed pattern. If the detected pattern corresponds to the stored one, a wake-up signal (IRQ) is risen up. The pattern correlation can be disabled; in this case the wake-up detection is based only on the frequency detection. The AS3933 is made up of three independent receiving channels, one envelop detector, one data correlator, one Manchester decoder, 19 programmable registers with the main logic and a Clock Generator. The digital logic can be accessed by an SPI. The Clock Generator can be based on a crystal oscillator, or an internal RC-oscillator or an external clock. In case the RC-oscillator is used to improve its accuracy, a calibration can be performed. The internal LC-oscillator can deliver the antenna’s oscillation frequency for each channel and the internal tuning capacitor bank can provide fine tuning. The Internal RC-oscillator can be calibrated either over SPI or using the internal algorithm ba sed on the antenna resonance frequency. Figure 19: Block Diagram of LF Wake-Up Receiver AS3933 Detailed Description Wakeup Main Logic Envelope Detector / Data Slicer Correlator I/V Bias Xtal Oscillator Xin RC Oscillator Manchester Decoder SPIChannel Amplifier 1 Channel Amplifier 2 Channel Amplifier 3 RSSI RSSI RSSI Data Data Data IRQ XoutGNDVCC LF1P LF2P LF3P SCL SDI SDO LFN DAT CS CL_DAT Channel Selector Freq. OK Freq. OK Freq. OK Tuning Capacitors Tuning Capacitors Tuning Capacitors LC-Oscillator Clock Buffer Clock Generator
Document Feedback [v1-08] 2015-Sep-02 AS3933 − Detailed Description AS3933 needs the following external components:
- Power supply capacitor - CBAT - 100 nF.
- 32.768 kHz crystal with its tw o pulling capacitors - XTAL and CL - (it is possible to om it these components if the internal RC oscillator is us ed instead of the crystal oscillator).
- One, two, or three LC resonators according to the number of used channels. In case the internal RC-oscillator is used (no crystal oscillator is mounted), the pin XIN has to be connected to the supply, while pin XOUT should stay floating. Application diagrams with and without crystal are shown in Figure 2 , Figure 3 and Figure 4 . Operating Modes The diagram in Figure 20 shows how the AS3933 operates. Figure 20: Operating Modes Flow Chart Pattern Correlation (Wake=0) Listening Mode (WAKE=0) Data Receiving (WAKE=1) Frequency Detection OK And Pattern Detection Enabled Frequency Detection OK And Pattern Detection Disabled Pattern matches Clear Wake or Time out Pattern doesn’t match Start RSSI (Wake=1) Start RSSI (Wake=0)
[v1-08] 2015-Sep-02 Document Feedback AS3933 − Detailed Description Listening Mode In listening mode, the chip is active and looks continuously for the presence of the carrier on the input of all active channels. In this mode, only the active channel amplifiers and the Clock Generator are running. In case th e carrier is detected, then the RSSI measurements get started on all three channels and the result is stored in the memory. If the three dimensional detection is not required, then it is possible to deactivate one or more channels. In case only two channels are required, then the deactivated channel must be the number two; while in case only one channel is needed, then the active channel must be the number one. Inside the listening mode, it is possible to distinguish the following three low power sub modes: Standard Listening Mode . All channels are active at the same time. Scanning Mode (Low Power Mode 1) . In this sub-mode, a time slot T=1ms is defined and in each time slot only one channel can be active. As shown in Figure 21 when a certain time slot is over, the current active channel is switched OFF and the next channel becomes active and so on. If, for example all three channels are enabled, in the fi rst time slot the only active channel is the number one. When the first time slot is over, the channel one is switched OFF and the channel three becomes active. During the third time slot, the channel two is active while the other two are OFF. This channel rotation starts back from the channel one and goes on until the presence of the carrier is detected by any channel. The Scanning mode (channel rotation) is managed internally by the AS3933 and doesn’t need any activity from the host system (MCU). As soon as one channel detects the frequency, all three channels become immediately active at the same time. The AS3933 can perform a simultaneous multidirectional evaluation (on all three channels) of the field and evaluate which channel has the strongest RSSI. The channel with the highest RSSI will be put through to the demodulator. In this way it is possible to perform multidirectional monitoring of the field with a current consumption of a single channe l, keeping the sensitivity as good as if all channels are active at the same time.
[v1-08] 2015-Sep-02 Document Feedback AS3933 − Detailed Description Artificial Wake-Up For each of these sub modes it is possible to enable a further feature called Artificial Wake-up. The Artificial Wake-up is a counter based on the used Clock Generator. Three bits define a time window (see R8<2:0> ). If no activity is seen within this time window, the chip will produce an interrupt on the WAKE pin that lasts 128 μs. With this interrupt the microcontroller ( μC) can get feedback on the surrounding environment (e.g. read the false wake-up register R13<7:0> ) and/or take actions in order to change the setup. Preamble Detection / Pattern Correlation The chip can go in to this mode after detecting a LF carrier only if the data correlation is enabled ( R1<1> =1). The correlator searches first for preamble bits and then for data pattern. The paragraph Wake-Up Protocol: Pattern Detection Enabled describes how the protocol can be implemented. Should the pattern correlation be disabled ( R1<1> =0), the AS3933 goes directly in Data receiv ing mode (see paragraph Data Receiving ). If the received pattern matches, then the wake-up interrupt is displayed on the WAKE output (Wake goes high) and the chip goes in Data receiving mode. If the pattern fails, then the internal wake-up (on all active channels) is terminated and no interrupt is produced. Having per default DAT_MASK disabled ( R0<6> =0), the DAT pin shows the entire demodulated incoming signal (carrier burst+preamble+pattern+data). If DAT_MASK is enabled ( R0<6> =1), the data will be displayed only after the generation of the WAKEUP interrupt. Note(s): It is important to note th at the Manchester decoder must be enabled ( R1<3> =1) for this feature. Data Receiving After a successful wake-up the chip enters the data receiving mode. In this mode the chip can be retained a normal OOK receiver. The data is provided on the DAT pin and in case the Manchester decoder is enabled (see R1<3> ), the recovered clock is present on the CL_DAT. It is possible to set the chip back to listening mode either with a direct command CLEAR_WAKE (see Figure 29) or by using the timeout feature. This feature automatically sets the chip back to listening mode after a certain time defined by the bits R7<7:5> .
Document Feedback [v1-08] 2015-Sep-02 AS3933 − Detailed Description System and Block Specification Register Overview Figure 23: Register Overview 7 6 5 4 3 2 1 0 R0 PATT32 DAT_MAS K ON_OFF MUX_123 EN_A2 EN_A3 EN_A1 R1 ABS_HY AGC_TLI M AGC_UD ATT_ON EN_MAN CH EN_PAT2 EN_WPAT EN_XTAL R2 S_ABS EN_EXT_ CLK G_BOOST Reserved DISPLAY_CLK S_WU1 R3 HY_20m HY_POS FS_SLC FS_ENV R4 T_OFF R_VAL GR R5 PATT2B R6 PATT1B R7 T_OUT T_HBIT R8 BAND_SEL T_AUTO R9 BLOCK_A GC Reserved R10 n.a RSSI1 R11 n.a RSSI2 R12 n.a RSSI3 R13 F_WAKE R14 RC_CAL_ OK RC_CAL_ KO RC_OSC_TAPS R15 n.a. LC_OSC_ OK LC_OSC_ KO n.a. R16 CLOCK_G EN_DIS n.a. RC_OSC_ MIN RC_OSC_ MAX n.a LC_OSC_MUX R17 n.a. CAP__CH1 R18 n.a. CAP__CH2 R19 n.a. CAP__CH3
[v1-08] 2015-Sep-02 Document Feedback AS3933 − Detailed Description Register Description and Default Values Figure 24: Default Values of Registers Register Name Type Default Value Description R0<7> PAT32 R/W 0 Pattern extended to 32 bits (PAT32=0 16 bits, PAT32=1 32bits) R0<6> DAT_MAS K R/W 0 Masks data on DAT pin before wake-up (DAT_MASK = 0 → data not masked; DAT_MASK = 1 → data masked) R0<5> ON_OFF R/W 0 ON/OFF operation mode. (Duty-cycle defined in the register R4<7:6> R0<4> MUX_123 R/W 0 Scan mode enable R0<3> EN_A2 R/W 1 Channel 2 enable R0<2> EN_A3 R/W 1 Channel 3 enable R0<1> EN_A1 R/W 1 Channel 1 enable R0<0> Reserved 0 Reserved R1<7> ABS_HY R/W 0 Enable Data slicer absolute reference R1<6> AGC_TLIM R/W 0 AGC acting only on the first carrier burst R1<5> AGC_UD R/W 1 AGC operatin g in both direction (up-down) R1<4> ATT_ON R/W 0 Antenna damper enable R1<3> EN_MANC H R/W 0 Manchester decoder enable R1<2> EN_PAT2 R/W 0 Double wake-up pattern correlation R1<1> EN_WPAT R/W 1 Correlator enable R1<0> EN_XTAL R/W 1 Crystal oscillator enable R2<7> S_ABSH R/W 0 Data slicer absolute threshold reduction R2<6> EN_EXT_C LK R/W 0 Enables external clock generator R2<5> G_BOOST R/W 0 3dB Amplifier Gain Boost (G_BOOST=1) R2<5> Reserved 0 Reserved R2<3:2> DISPLAY_ CLK R/W 00 Set to 11 in case the clock generator's frequency is shown on pin CL_DAT. R2<1:0> S_WU1 R/W 00 Tolerance setting for the stage wake-up (see Figure 37)
Document Feedback [v1-08] 2015-Sep-02 AS3933 − Detailed Description R3<7> HY_20m R/W 0 Data slicer hysteresis if HY_20m = 0 then comparator hysteresis = 40mV if HY_20m = 1 then comparator hysteresis = 20mV R3<6> HY_POS R/W 0 Data slicer hysteresis only on positive edges (HY_POS=0, hysteresis on both edges, HY_POS=1, hysteresis only on positive edges) R3<5:3> FS_SCL R/W 100 Data slicer time constant (see Figure 45) R3<2:0> FS_ENV R/W 000 Envelop detector time constant (see Figure 44) R4<7:6> T_OFF R/W 00 OFF time in ON/OFF operation mode T_OFF=00 1ms T_OFF=01 2ms T_OFF=10 4ms T_OFF=11 8ms R4<5:4> D_RES R/W 01 Antenna damping resistor (see Figure 40) R4<3:0> GR R/W 0000 Gain reduction (see Figure 39) R5<7:0> TS2 R/W 01101001 2nd Byte of wake-up pattern R6<7:0> TS1 R/W 10010110 1st Byte of wake-up pattern R7<7:5> T_OUT R/W 000 Automatic time-out (see Figure 49) R7<4:0> T_HBIT R/W 01011 Bit rate definition (see Figure 48) R8<7:5> BAND_SEL R/W 000 Band selection (see Figure 36) R8<2:0> T_AUTO R/W 000 Artificial wake-up T_AUTO=000 No artificial wake-up T_AUTO=001 1 sec T_AUTO=010 5 sec T_AUTO=011 20 sec T_AUTO=100 2 min T_AUTO=101 15min T_AUTO=110 1 hour T_AUTO=111 2 hour R9<7> BLOCK_A GC R/W 0 Disables AGC R9<6:0> 000000 Reserved Register Name Type Default Value Description
[v1-08] 2015-Sep-02 Document Feedback AS3933 − Detailed Description R10<4:0> RSSI1 R RSSI channel 1 R11<4:0> RSSI2 R RSSI channel 2 R12<4:0> RSSI3 R RSSI channel 3 R13<7:0> F_WAK R False wake-up register R14<7> RC_CAL_O K R Successful RC calibration R14<6> RC_CAL_K O R Unsuccessful RC calibration R14<5:0> RC_OSC_T APS R RC-Oscillator taps setting R15<4> LC_OSC_O K R LC-Oscillator working R15<3> LC_OSC_K O R LC-Oscillator not working R16<7> CLOCK_GE N_DIS R/W 0 The Clock Generator output signal displayed on CL_DAT pin R16<5> RC_OSC_ MIN R/W 0 Sets the RC-oscillator to minimum frequency R16<4> RC_OSC_ MAX R/W 0 Sets the RC-oscillator to maximum frequency R16<2> LC_OSC_ MUX3 R/W 0 Displays the resonance frequency of LF3P on DAT pin R16<1> LC_OSC_ MUX2 R/W 0 Displays the resonance frequency of LF2P on DAT pin R16<0> LC_OSC_ MUX1 R/W 0 Displays the resonance frequency of LF1P on DAT pin R17<4:0> CAPS_CH1 R/W 00000 Capacitor banks on the channel1 R18<4:0> CAPS_CH1 R/W 00000 Capacitor banks on the channel2 R19<4:0> CAPS_CH1 R/W 00000 Capacitor banks on the channel3 Register Name Type Default Value Description
[v1-08] 2015-Sep-02 Document Feedback AS3933 − Detailed Description Figure 27: SDI Command Structure In case a write or read command happens the next 6 bits (B13 to B8) define the register address which has to be written respectively read, as shown in Figure 28 . Figure 28: SDI Command Structure B15 B14 Mode 0 0 WRITE 0 1 READ 1 0 NOT ALLOWED 1 1 DIRECT COMMAND B13 B12 B11 B10 B9 B8 Read/Write Register 0 0 0 0 0 0 R0 0 0 0 0 0 1 R1 0 0 0 0 1 0 R2 0 0 0 0 1 1 R3 0 0 0 1 0 0 R4 0 0 0 1 0 1 R5 0 0 0 1 1 0 R6 0 0 0 1 1 1 R7 0 0 1 0 0 0 R8 0 0 1 0 0 1 R9
001010 R 1 0
001011 R 1 1
001100 R 1 2
001101 R 1 3
Document Feedback [v1-08] 2015-Sep-02 AS3933 − Detailed Description Channel Amplifier and Frequency Detector Each of the 3 channels consists of a variable gain amplifier (VGA) with automatic gain control (AGC) and a frequency detector. When the AS3933 is in listening mode (waiting for RF signal) the gain of all channel amplif iers is set to maximum. The frequency detector counts the zero crossing of the amplified RF signal to detect the presence of the wanted carrier. As soon as the carrier is detected the AGC is enabled, the gain of the VGA is reduced and set to the right value. The RSSI (Received Signal Strength Indicator) represents how strong the input signal is and it is the inverse representati on of the gain of the VGA. In fact, if for example the input signal is very strong the AGC will reduce the gain of the VGA. The gain reduction will correspond to a big RSSI, as it is the inverse of the gain setting of the VGA (small gain corresponds to a big RSSI and vice versa). The AS3933 is a pretty wide LF wake-up receiver and can work between 15 kHz and 150 kHz. Once the carrier frequency has been chosen the user must se t the amplifier working in the appropriate frequency band using the bits R8<7:5> , as described in the Figure 36 . It is possible to boost the gain of the amplifiers for +3dB with an improvement of the sens itivity, as shown in the Figure 14 (R2<5> =1). The gain boost will increase the current consumption of 100nA (typ) per channel. In case the lowest frequency band is used (15kHz – 23 kHz) the gain boost is automatically enabled from the logic. It is possible to enable/disable individual channels, in case not all three channels are needed. This enables to reduce the current consumption by 1.5 μA (typ.) per channel. Frequency Detector / RSSI / Channel Selector The frequency detection is based on a zero crossing counter and uses the Clock Generator as time base. This counter counts the zero crossing of the input signal within a time window defined by the clock generator and if it matches to the expected value it enabled the AGC (the RSSI measurement can get started). The Clock Generator can be based either on the internal RC-oscillator or on the Crystal oscillator or on the external clock source. The details on the choice of the Clock Generator are discussed in the Clock Generator . The Clock Generator generates time windows equal to N times its period, where N depends on the operating frequency band, as shown in the Figure 36 .
Document Feedback [v1-08] 2015-Sep-02 AS3933 − Detailed Description The AGC starts working after the frequency detection. At the beginning the gain in the VGA is set to maximum and the AGC reduce it according to the received signal input level. The AGC needs maximum 35 carrier period s to settle, getting a stable RSSI. The AGC can operate in two modes:
- AGC down only ( R1<5> =0)
- AGC up and down ( R1<5> =1) If the AGC down only mode is selected, the AGC can only decrease the gain for the whole duration of the data reception; in this mode the system holds the RSSI peak. When the AGC up and down mode is selected, the RSSI can dynamically follow the input sign al strength variation in both directions. The RSSI is available for all 3 channels at the same time and it is stored in 3 registers ( R10<4:0> , R11<4:0> , R12<4:0> ). Once the RSSI gets stable (maximum after 35 carrier periods after frequency detection) the channel selector checks which channel receives the strongest signal. The channel selector compares the RSSI on the active channels and freezes the AGC on the channels which have the smaller RSSI. From this time on the AGC is active only on the selected channel. It is possible to set things back having the AGC active on all channels just sending a clear_wake (sets the chip back to listening mode) or reset_RSSI (resets the ACG) direct command. Both AGC modes (only down or down and up) can also operate with time limitation. This option allows AGC operation only in time slot of 256μs after the fr equency detection (during carrier burst), then the RSSI is frozen till the wake-up or RSSI reset occurs (clear_wakeup or reset_RSSI). The RSSI is reset either with the direct command 'clear_wakeup' or 'reset_RSSI' . The 'reset_RSSI' command resets only the VGA setting but does not terminate wake-up frequency detection condition. This means that if th e signal is still present the new AGC setting (RSSI) will appear not later than 35 LF carrier periods after the command was received. The AGC setting is reset during data receiving if fo r duration of 3 Manchester half symbols no carrier is detected. If the wake-up IRQ is cleared the chip will go back to listening mode. In case the maximum amplific ation at the beginning is a drawback (e.g. in noisy environment) it is possible to set a smaller starting gain on the amplifier, according to the Figure 39 . In this way it is possible to reduce the false frequency detection.
Document Feedback [v1-08] 2015-Sep-02 AS3933 − Detailed Description Figure 41: Antenna Damper Demodulator / Data Slicer As soon as the AS3933 detects successfully the frequency and the RSSI has got stable the channel selector compares the RSSI on all active channels and connects the channel amplifier which has the biggest RSSI to the demodulator. The channel selector needs 32 RF carrier periods to ta ke this decision. The output signal (amplified LF carrier) of selected channel is connected to the input of th e demodulator. The demodulator takes the signal to base-band and recovers two signals from the amplified RF signal; a fast and a slow envelop. Those two signals are fed to the data slicer, which is a comparator with programmable hysteresis. At the output of the data slicer are streamed the di gital received bits. A concept block diagram is shown in the Figure 42 . Channel Amplifier1 LC R LC R LC R Channel Amplifier2 Channel Amplifier1 LF1P LF2P LF3P LFN
[v1-08] 2015-Sep-02 Document Feedback AS3933 − Detailed Description Figure 45: Minimum Required Preamble Lengths as Function of Slow Envelop Settings Note(s) and/or Footnote(s): 1. These times are minimum required, but it is recommended to prolong the preamble. With the bits R3<6> and R3<7> it is possible to change the hysteresis on the data slicer co mparator (only positive, positive negative, 20mV, 40mV). The slow envelop signal (blue signal in Figure 43 ) represents the average of the demodulated signal, therefore acts as a reference signal for the data slicer. In case the chosen protocol has a duty cycle far away from 50% (for example in the NRZ protocol there can be several consecutive ones or zeros) the slow envelop signal would not be a stable reference signal for the data slicer. In this case the da ta slicer can also work with an absolute threshold ( R1<7> ), as shown in the Figure 46 . Should the absolute threshold be enabled the bits R3<2:0> would not influence the performance. It is even possible to reduce the absolute threshold in case the environment is not particularly noisy ( R2<7> ). As the input signal may be damped due to physical influences of the transmitter environment, the symbol rate needs to be adapted (lowered) if absolute th reshold is enabled to ensure a proper detection of the wake-up signal. The peak level of the signal should be reached within 1/3 of the symbol duration which is defined as two times the bit duration. The bit duration is defined in register R7 <4:0> as a function of the Clock Generator periods. R3<5> R3<4> R3<3> Minimum Preamble Length [ms] 0 0 0 0.8 0 0 1 1.15 0 1 0 1.55 0 1 1 1.9 1 0 0 2.3 1 0 1 2.65 1 1 0 3 1 1 1 3.5
Document Feedback [v1-08] 2015-Sep-02 AS3933 − Detailed Description Figure 46: Envelop Detector Signals - Absolute Threshold Correlator In order to prevent that the AS 3933 wakes up the host system (MCU) from noise or disturbers (LF transmitter within the field) the internal correlator checks that the bit sequence delivered from the data slicer corresponds to stored pattern. The wanted pattern can be stored in the registers R5<7:0> and R6<7:0> . The data correlation is performed only if the correlator is enabled (R1<1> =1) and can start only after frequency detection. The pattern correlation is successful (Wake goes high) only if the bits sequence (pattern) and its timing (duration of the single bit) matches. Pattern: Bit and Symbol De finition in Manchester Code The AS3933 can correlate the incoming pattern without the help of an external unit (MCU). The chosen pattern must be Manchester encoded. In the Manchester code each “Symbol” is defined by a transition (high-to-low for 1 and low-to-high for 0), therefore consists of two “bits” . In the Figure 47 it is shown, as an example, how the encoding technique works. In this sequence a simple message made up by 3 symbols (1 0 1) is Manchester encoded. In the Manchester encoded bit stream there can not be three consecutive zeros or ones (in each symbol there is always a transition). This helps the receiver to recover the clock. Absolute Threshold (blue) Fast Envelop (red) Data Slicer Output
Document Feedback [v1-08] 2015-Sep-02 AS3933 − Detailed Description The user can define the pattern to correlate in the registers R5<7:0> and R6<7:0> and can decide whether the stored pattern is a bit representation (16 Manchester bits corresponds to 8 Symbols) if R0<7> =0 or the symbol representation (16 symbols corresponds to 32 bits) of the pattern if R0<7> =1. The number of different pattern is 2^SYM, where SYM is the number of Manchester symbols. In case the R5<7:0> and R6<7:0> represent the bit sequence of the pattern there are 256 different possible combinations, while in case they are the symbol representation there are 65536 different patterns. 1 0 0 0 1 18 1 0 0 1 0 19 1 0 0 1 1 20 1 0 1 0 0 21 1 0 1 0 1 22 1 0 1 1 0 23 1 0 1 1 1 24 1 1 0 0 0 25 1 1 0 0 1 26 1 1 0 1 0 27 1 1 0 1 1 28 1 1 1 0 0 29 111 0 1 3 0 111 1 0 3 1 111 1 1 3 2 Clock Periods
[v1-08] 2015-Sep-02 Document Feedback AS3933 − Detailed Description Wake-Up Protocol The AS3933 can support different protocols:
- Frequency detection only (no pattern correlation)
- Single pattern detection
- 16-bit pattern
- 32-bit pattern
- Double pattern detection
- 16-bits pattern
- 32-bits pattern The wake-up state can be terminated either by the host system (MCU) with the direct command ‘clear_wake’ sent over SPI (see direct command details in Figure 29 ) or with a time-out option. In case the latter is used the host system (MCU) does not need to take any action to terminate the wake-up state and the chip is set back to listening mode automatically after a predefined time. It is possible to set the duration of the time-out with the register R7<7:5> , as shown in the Figure 49 . Figure 49: Timeout Setup 0 0 0 disabled 0 0 1 50 msec 0 1 0 100 msec 0 1 1 150 msec 1 0 0 200 msec 1 0 1 250 msec 1 1 0 300 msec 1 1 1 350 msec
Document Feedback [v1-08] 2015-Sep-02 AS3933 − Detailed Description Wake-Up Protocol: Frequency Detection Only Figure 50: Wake-Up Protocol Overview Without Pattern Detection In case the pattern correlation is disabled ( R1<1> =0) the AS3933 wakes up upon detection of the carrier frequency only as shown in Figure 50 . The minimum duration of the carrier burst in order to ensure that AS 3933 wakes up and the RSSI is settled is specified in the Figure 52 . In addition the carrier burst does not have to be longer than 155 periods of the Clock Generator (Crystal oscillator or RCO or External Clock). As shown in the Figure 20 , the AS3933 after the de tection of the carrier goes directly from the Listenin g mode to Data receiving mode after settling the RSSI. Wake-Up Protocol: Pattern Detection Enabled In case the pattern correlation is enabled ( R1<1> =1) the AS3933 generates a wake-up interrupt if the wake-up protocol is fulfilled. The communication protocol consists of a carrier burst, a preamble (0101010…. ON/OFF modulated carrier) and the 16-bit pattern. In case the double pattern option is enabled (R1<2> =1) the 16-bit pattern has to be repeated 2 times consequentially (2 times the same pattern). The signal on the WAKE pin goes high one bit after the end of the pattern and the data transmission can get started. Carrier Burst Data Carrier Burst WAKE Clear_wake DAT
Document Feedback [v1-08] 2015-Sep-02 AS3933 − Detailed Description Most wake-up receivers have to deal with environments that can rapidly change. By periodically monitoring the number of false wake-up events it is possible to adapt the system setup to the actual characteristics of the environment and enables a better use of the full flexibility of AS3933. Figure 55: Concept of the False Wake-Up Register Together with the System Frequency Detector Pattern Correlator Wakeup Level 1 Wakeup Level 2 WAKE False wakeup register Unsuccessful pattern correlation Register Setup Microcontroller READ FALSE WAKEUP REGISTER CHANGE SETUP TO MINIMIZE THE FALSE WAKEUP EVENTS
[v1-08] 2015-Sep-02 Document Feedback AS3933 − Detailed Description Clock Generator The Clock Generator can be based on a crystal oscillator (R1<0> =1), the internal RC-oscillator ( R1<0> =0), or an external clock source ( R1<0> =1). The crystal oscillator has higher precision of the frequency with higher current consumption and needs three external components (crystal plus two capacitors). The RC-oscillator is completely integrated and can be calibrated to increase its pr ecision. Should a digital clock already be available it can be applied directly to the XOUT pin (XIN to VDD). Regardless which clock generator is chosen, the frequency of the Clock Generator must be set according to the carrier frequency. Figure 56 shows the dependency of the Clock Generator frequency from the carrier frequency and operating frequency band. Figure 56: Clock Generator Frequency vs Frequency Band It is possible to display the frequency of the clock generator on the CL_DAT pin writing R2<3:2> =11 and R16<7> =1. Carrier Frequency [kHz] Clock Generator Frequency 15 – 23 23-40 40-65 65 – 95 95 - 150 fRC fcarr fRC fcarr 8---⋅= fRC fcarr 8---⋅= fRC fcarr 8---⋅= fRC fcarr
[v1-08] 2015-Sep-02 Document Feedback AS3933 − Detailed Description In case the pattern detection and the Manchester decoder are not enabled ( R1<1> =0 and R1<3> =1) the calibration on the RC-oscillator is not needed. Should this not be the case, the RC-oscillator has to be calibrated. The calibration of the RC-oscillator can be done in two different ways:
- Over SPI, the host system (MCU ) has to be able to provide 65 clock pulses of a reference clock. In this case the host has to have a precise reference clock (quartz, resonator etc.).
- Using the internal calibration procedure based on the antenna resonator. Using th is calibration method the RC-oscillator is automatically trimmed to the proper frequency, according to the operating frequency band. The precision of the calibration depends on the tolerances of the resonator of the first channel (LC connected to LF1P). RC-Oscillator: Calibration via SPI . The calibration gets started with the Calib_RCosc direct command. Since no non-volatile memory is available on the chip, the calibration must be done every time after battery replacement. Since the Clock Generator defines the time base of the frequency detection, the selected frequency depends on the carrier frequency. The choice of the reference clock frequency delivered by the host (MCU) is the same as the choice of the frequenc y in case the crystal oscillator is used and it is shown in the Figure 56 . To trim the RC-Oscillator, set the chip select (CS) to high before sending the direct command Calib_RCosc over SPI. Then 65 digital clock cycles of the reference clock (e.g. 125kHz/4=31.25kHz) have to be sent on the clock bus (SCLK), as shown in Figure 59 . After that the signal on the chip select (CS) has to be pulled down. The calibration is effective after the 65th reference clock edge and it will be stored in a volatile memory. In case the RC-oscillator is switched OFF or a power-on-reset happens (e.g. battery change) the calibration has to be repeated. Figure 59: RC-Oscillator Calibration via SPI CS SCLK SDI XX 65 clock cycles 11 1 00 00 0 DIRECT COMMAND Trim_osc REFERENCE CLOCK
Document Feedback [v1-08] 2015-Sep-02 AS3933 − Detailed Description RC-Oscillator: Self Calibration . This procedure uses the LC-tank (antenna) connected to the channel 1 (LF1P) not as antenna but as resonator for an oscillator. The internal LC oscillator is therefore connected through a multiplexer to the external tank. The LC-oscillator generates a clock which corresponds to the resonance frequency of the LC-tank. In a typical application the user designs the external resona tors such to set the resonance frequency of the external LC-tank as close as possible to the carrier frequency. The mathematical relation between the oscillation frequency and the LC time constant is: Where: L is the inductance and C the capacitance of the external antenna To start the calibration the direct command Calib_RCO_LC must be sent over the SPI and as soon as the bit R14<7> is high, the RC-oscillator will be calibrated. The calibrated frequency of the RC-oscillator depends on the carrier frequency and is automatically set to better pe rform the frequency detection, according to the Figure 56 . External Clock Source To clock the AS3933 with an exte rnal signal, the external clock generator ( R2<6> =1) and the crystal oscillator ( R1<0> =1) need to be enabled. As shown in the Figure 4 the clock can be directly applied on the pin XOUT while the pin XIN must be connected to VDD. The clock characteristics are summarized in Figure 60 . Figure 60: Characteristics of External Clock Note(s): In power down mode the exte rnal clock has to be set to a definite potential (VDD or ground). The frequency of the external clock source must be set according to the Figure 56 . Symbol Parameter Conditions Min Typ Max Units VI Low level 0 0.1* VDD V Vh High level 0.9* VDD V DD V Tr Rise-time 3 μs Tf Fall-time 3 μs (EQ1) FLC 2 π LC⋅⋅⋅
[v1-08] 2015-Sep-02 Document Feedback AS3933 − Detailed Description Antenna Tuning The AS3933 offers the possibility to implement a fine antenna tuning. A block diagram shows how the tuning can be implemented with the help of the host system (MCU). Figure 61: Tuning Implementation Channel Amplifier1 LC R LC R LC R Channel Amplifier2 Channel Amplifier1 LF1P LF2P LF3P LFN LC-Oscillator SPI MCU DAT
[v1-08] 2015-Sep-02 Document Feedback AS3933 − Detailed Description Figure 64: Parallel Tuning Capacitance on the LF3P The Three channels can be tune d separately. The host system (MCU) has to connect the LC-oscillator to the antenna to measure the resonance frequency on the pin DAT. The host should measure the frequency on this pin and just changing register setting fine tune it to get it as close as possible to the nominal value of the carrier frequency. With the bits R16<2:0> it is possible to connect the LC-oscillator to the three different antennas. Channel Selection in Scanning Mode and ON/OFF Mode In case only 2 channels are active and one of the Low Power modes is enabled, then the channels 1 and 3 have to be active. If the chip works in ON-OFF mode and only one channel is active then the active channel has to be the channel 1. Both Low Power modes are not allowed to be enabled at the same time. R19 Capacitance on LF3P R19<0>=1 Adds 1pF to LF3P R19<1>=1 Adds 2pF to LF3P R19<2>=1 Adds 4pF to LF3P R19<3>=1 Adds 8pF to LF3P R19<4>=1 Adds 16pF to LF3P
Document Feedback [v1-08] 2015-Sep-02 AS3933 − Ordering & Contact Information The devices are available as the standard products shown in Figure 69 . Figure 69:
Ordering Information
Note(s) and/or Footnote(s): 1. Dry Pack: Moisture Sensitivity Level (M SL) = 3, according to IPC/JEDEC J-STD-033A. Buy our products or get free samples online at: www.ams.com/ICdirect Technical Support is available at: www.ams.com/Technical-Support Provide feedback about this document at: www.ams.com/Document-Feedback For further information and requests, e-mail us at: ams_sales@ams.com For sales offices, distributors and representatives, please visit: www.ams.com/contact Headquarters ams AG Tobelbaderstrasse 30
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Austria, Europe Tel: +43 (0) 3136 500 0 Website: www.ams.com Ordering Code Type Marking Delivery Form(1) Delivery Quantity AS3933-BTST 16-pin TSSOP AS3933 7 inches Tape & Reel 1000 pcs/reel AS3933-BQFT QFN (4 ×4) 16LD AS3933 7 inches Tape & Reel 1000 pcs/reel AS3933-BSWB DoW AS3933 Wafer Box ca. 8000 dice/wafer Ordering & Contact Information
[v1-08] 2015-Sep-02 Document Feedback AS3933 − RoHS Compliant & ams Green Statement RoHS: The term RoHS compliant means that ams AG products fully comply with current RoHS directives. Our semiconductor products do not contain any chemicals for all 6 substance categories, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, RoHS compliant products are suitable for use in specif ied lead-free processes. ams Green (RoHS compliant and no Sb/Br): ams Green defines that in addition to RoHS compliance, our products are free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material). Important Information: The information provided in this statement represents ams AG knowledge and belief as of the date that it is provided. ams AG bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are unde rway to better integrate information from third parties. ams AG has taken and continues to take reasonable steps to prov ide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ams AG and ams AG suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. RoHS Compliant & ams Green Statement
Document Feedback [v1-08] 2015-Sep-02 AS3933 − Copyrights & Disclaimer Copyright ams AG, Tobelbader Strasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. Devices sold by ams AG are covered by the warranty and patent indemnification provisions appe aring in its General Terms of Trade. ams AG makes no warranty, express, statutory, implied, or by description regarding th e information set forth herein. ams AG reserves the right to ch ange specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with ams AG for current information. This product is intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications , such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by ams AG for each application. This product is provided by ams AG “AS IS” and any express or implied wa rranties, including, but not limited to the implied warranties of merchantability and fitness for a particular purpose are disclaimed. ams AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any th ird party shall arise or flow out of ams AG rendering of technical or other services. Copyrights & Disclaimer
[v1-08] 2015-Sep-02 Document Feedback AS3933 − Document Status Document Status Product Status Definition Product Preview Pre-Development Information in this datasheet is based on product ideas in the planning phase of development. All specifications are design goals without any warranty and are subject to change without notice Preliminary Datasheet Pre-Production Information in this datasheet is based on products in the design, validation or qualification phase of development. The performance and parameters shown in this document are preliminary without any warranty and are subject to change without notice Datasheet Production Information in this datasheet is based on products in ramp-up to full production or full production which conform to specifications in accordance with the terms of ams AG standard warranty as given in the General Terms of Trade Datasheet (discontinued) Discontinued Information in this datasheet is based on products which conform to specifications in accordance with the terms of ams AG standard warranty as given in the General Terms of Trade, but these products have been superseded and should not be used for new designs Document Status
Document Feedback [v1-08] 2015-Sep-02 AS3933 − Revision Information Note(s) and/or Footnote(s): 1. Page and figure numbers for the previous version may diff er from page and figure numbers in the current revision. 2. Correction of typographical er rors is not explicitly mentioned. Changes from 1-07 (2015-Mar-02) to current revision 1-08 (2015-Sep-02) Page Updated text under Figure 45 39 Revision Information
[v1-08] 2015-Sep-02 Document Feedback AS3933 − Content Guide
1 General Description
1 Key Benefits & Features
2 Applications
5 Pin Assignments
5 Pin Description
7 Pin Description
8A b s o l u t e M a x i m u m R a t i n g s