AS3930 AMSCO | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1 General Description
- 2 Key Features
- 3 Applications
- 4 Pin Assignments
- 4.1 TSSOP Package
- 4.1.1 Pin Descriptions
- 4.2 QFN Package
- 4.2.1 Pin Descriptions
- 5 Absolute Maximum Ratings
- 6 Electrical Characteristics
- 7 Typical Operating Characteristics
- 8 Detailed Description
- 8.1 Block Diagram
- 8.2 Operating modes
- 8.2.1 Power Down Mode
- 8.2.2 Listening Mode
- 8.2.3 Preamble Detection / Pattern Correlation
- 8.2.4 Data Receiving
- 8.3 System and Block Specification
- 8.3.1 Main Logic and SDI
- 8.4 Channel Amplifier and Frequency Detector
- 8.4.1 Frequency Detector / AGC
- 8.4.2 Antenna Damper
- 8.5 Demodulator / Data Slicer
- 8.6 Correlator
- 8.7 Wakeup Protocol - Carrier Frequency 125 kHz
- 8.7.1 Without pattern detection (Manchester decoder disabled)
- 8.7.2 Single Pattern Detection (Manchester decoder disabled)
- 8.7.3 Single Pattern Detection (Manchester decoder enabled)
- 8.8 False Wakeup Register
- 8.9 Real Time Clock (RTC)
- 8.9.1 Crystal Oscillator
- 8.9.2 RC-Oscillator
- 8.9.3 External Clock Source
- 9 Package Drawings and Markings
- 10 Ordering Information
Single Channel Low Frequency Wakeup Receiver www.austriamicrosystems.com/AS3930 Revision 1.0 1 - 33 Data Sheet
1 General Description
The AS3930 is a single-channel low power ASK receiver that is able to generate a wakeup upon detection of a data signal which uses a LF carrier frequency between 110 - 150 kHz. The integrated correlator can be used for detection of a programmable 16-bit wakeup pattern. The AS3930 provides a digital RSSI value, it supports a programmable data rate and Manchester decoding with clock recovery. The AS3930 offers a real-time clock (RTC), which is either derived from a crystal oscillator or the internal RC oscillator. The programmable features of AS3930 enable to optimize its settings for achieving a longer distance while retaining a reliable wakeup generation. The sensitivity level of AS3930 can be adjusted in presence of a strong field or in noisy environments. The device is available in 16 pin TSSOP and QFN 4x4 16 LD packages.
2 Key Features
Single channel ASK wakeup receiver Carrier frequency range 110 - 150 kHz Programmable wakeup pattern (16bits) Doubling of wakeup pattern supported Wakeup without pattern detection supported Wakeup sensitivity 100µVRMS (typ.) Adjustable sensitivity level Highly resistant to false wakeups False wakeup counter Periodical forced wakeup supported (1s – 2h) Low power listening modes Current consumption in listening mode 1.37 µA (typ.) Data rate adjustable from 0.5 - 4 kbps (Manchester) Manchester decoding with clock recovery Digital RSSI Dynamic range 64dB 5 bit RSSI step (2dB per step) RTC based on 32kHz XTAL, RC-OSC, or external clock Operating temperature range -40 to +85ºC Operating supply voltage 2.4 - 3.6V (TA = 25ºC) Bidirectional serial digital interface (SDI) Package option 16 pin TSSOP, QFN 4x4 16 LD
3 Applications
The AS3930 is ideal for Active RFID tags, real-time location systems, operator identification, access control, and wireless sensors.
Figure 3. AS3930 Typical Application Diagram with Clock from External Source
4 Pin Assignments
4.1 TSSOP Package
Figure 4. Pin Assignments 16 pin TSSOP Package
4.1.1 Pin Descriptions
Table 1. Pin Descriptions 16 pin TSSOP Package
4.2 QFN Package
Figure 5. Pin Assignments QFN 4x4 16 LD Package
4.2.1 Pin Descriptions
Table 2. Pin Descriptions QFN 4x4 16 LD Package
5 Absolute Maximum Ratings
absolute maximum rating conditions for extended periods may affect device reliability. Table 3. Absolute Maximum Ratings
- The reflow peak soldering temperature (body temperature) is specified according IPC/JEDEC J-STD-020C “Moisture/Reflow Sensitivity
Classification for Nonhermetic Solid State Surface Mount Devices”.
6 Electrical Characteristics
Table 4. Electrical Characteristics Table 5. Electrical System Specifications
7 Typical Operating Characteristics
Figure 6. Sensitivity over Voltage and Temperature Figure 7. Sensitivity over RSSI Figure 8. RC-Osc Frequency over Voltage (calibr.) Figure 9. RC-Osc Frequency over T emperature (calibr.)
8 Detailed Description
registers with the main logic and a real time clock. used to improve its accuracy a calibration can be performed.
8.1 Block Diagram
Figure 10. Block Diagram
instead of the crystal oscillator).
8.2 Operating modes
8.2.1 Power Down Mode
In Power Down Mode AS3930 is completely switched off. The typical current consumption is 400 nA.
8.2.2 Listening Mode
carrier is detected the RSSI can be displayed.
8.2.2.1 Standard Listening mode
The channel amplifier, capable to detect the presence of the carrier frequency, is active all the time.
8.2.2.2 ON/OFF mode (Low Power mode)
The channel amplifier is active for one millisecond to be than switched-off for a certain time. The OFF-time is programmable see R4<7:6>. Figure 11. ON/OFF Mode (e.g. read the false wakeup register, see relator register R13<7:0>) and/or take actions in order to change the setup.
8.2.3 Preamble Detection / Pattern Correlation
first for preamble frequency (constant frequency of Manchester clock defined according to bit-rate transmission) and then for data pattern. internal wake-up is terminated and no IRQ is produced.
8.2.4 Data Receiving
8.3 System and Bl ock Specification
8.3.1 Main Logic and SDI
8.3.1.1 Register T able
8.3.1.2 Register T able Description and Default Values
Table 6. Register Table Table 7. Default Values of Registers
8.3.1.3 Serial Data Interface (SDI)
This 4-wire interface is used by the Microcontroller (µC) to program the AS3930. The maximum clock operation frequency of the SDI is 2 MHz. Note: SDO is set to tristate if CS is low. In this way more than one device can communicate on the same SDO bus. the SDI from the MSB (B15) to the LSB (B0). used), as shown in Table 10. Table 8. Serial Data Interface (SDI) pins Table 9. SDI Command Structure Table 10. SDI Command Structure
00 W R I T E
Table 11. SDI Command Structure
000000 R 0
000001 R 1
000010 R 2
000011 R 3
The last 8 bits are the data that has to be written respectively read. A CS toggle high-low-high terminates the command mode.
- reset_RSSI: resets the RSSI measurement.
The SDI is sampled at the falling edge of CLK (as shown in the following diagrams).
000100 R 4
000101 R 5
000110 R 6
000111 R 7
001000 R 8
001001 R 9
001010 R 1 0
001011 R 1 1
001100 R 1 2
001101 R 1 3
Table 12. List of Direct Commands
Figure 15. Send Direct COMMAND Byte
8.4 Channel Amplifier and Frequency Detector
8.4.1 Frequency Detector / AGC
described in R2<1:0>(see Table 13). decrease the gain. Since the RSSI is directly derived from the VGA gain, the system holds the RSSI peak. When the AGC up and down mode is selected, the RSSI can follow the input signal strength variation in both directions. Regardless which AGC operation mode is used, the AGC needs maximum 35 carrier periods to settle. The RSSI is stored in the register R10<4:0>. following the internal wake-up. Then the AGC (RSSI) is frozen till the wake-up or RSSI reset occurs. detected. If the wake-up IRQ is cleared the chip will go back to listening mode. Table 13. T olerance settings for Wakeup
11 R e s e r v e d
amplifier, according to the Table 14. In this way it is possible to reduce the false frequency detection.
8.4.2 Antenna Damper
doesn't saturate in presence of bigger signals). Table 15 shows the bit setup.
8.5 Demodulator / Data Slicer
The performance of the demodulator can be optimized according to bit rate and preamble length as described in Table 16 and Table 17. Table 14. Bit setting of Gain Reduction Table 15. Antenna Damper Bit Setup Table 16. Bit setup for Envelop Detector for Different Symbol Rates
influence the length of the preamble. Table 17 gives a correlation between data slicer setup and minimum required preamble length. Note: These times are minimum required, but it is recommended to prolong the preamble.
8.6 Correlator
After frequency detection the data correlation is only performed if the correlator is enabled (R1<1>=1). The data correlation consists of checking the presence of a preamble (ON/OFF modulated carrier) followed by a certain pattern. listening mode and the false-wakeup register (R13<7:0>) is incremented by one. To get started with the pattern correlation the correlator needs to detect at least 4 bits of the preamble (ON/OFF modulated carrier). The bit duration is defined in the register R7<4:0> according to the Table 18 as function of the Real Time Clock (RTC) periods. Table 17. Bit setup for Data Slicer for Different Preamble Length Table 18. Bit Rate Setup
represents a symbol "1". If the default code is used (96 [hex]) the binary code is (10 01 01 10 01 10 10 01). MSB has to be transmitted first. coming out from the DAT pin are decoded and the clock is recovered on the pin DAT_CL. The data coming out from the DAT pin are stable (and therefore can be acquired) on the rising edge of the CL_DAT clock, as shown in Figure 16. Table 19. Allowed Pattern Detection Errors
Figure 16. Synchronization of Data with Recovered Manchester clock will be incremented (R13<7:0>). Table 20. Timeout Setup
8.7 Wakeup Protocol - Ca rrier Frequency 125 kHz
8.7.1 Without pattern detectio n (Manchester decoder disabled)
Figure 17. Wakeup Protocol Overview without Pattern Detection (only carrier frequency detection, Manchester decoder disabled)
8.7.2 Single Pattern Detectio n (Manchester decoder disabled)
internal wakeup will be set back to low and the false wakeup counter (R13<7:0>) will be incremented by one. set the chip back to listening mode the direct command clear_false, as well as the time out option (R7<7:5>) can be used.
Figure 18. Wakeup Protocol Overview with Single Pattern Detection (Manchester decoder disabled) Table 21. Preamble Requirements in Standard Mode, Scanning Mode and ON/OFF Mode
8.7.3 Single Pattern Detectio n (Manchester decoder enabled)
out option (R7<7:5>) can be used. In case the On/OFF mode is enabled the Manchester decoder can not be used. Figure 19. Wakeup Protocol Overview with Single Pattern Detection (Manchester decoder enabled)
8.8 False Wakeup Register
- Frequency Detection: in this phase the frequency of the received signal is checked.
- Pattern Correlation: here the pattern is demodulated and checked whether it corresponds to the valid one.
environment and thus avoid false wakeup events.
is possible to adapt the system setup to the actual characteristics of the environment and enables a better use of the full flexibility of AS3930. Note: If the Manchester decoder is enabled, the false wakeup register is not able to store the false wakeup events. Figure 20. Concept of False Wakeup Register together with System
8.9 Real Time Clock (RTC)
Note: The third option for the RTC is the use of an external clock source, which must be applied directly to the XIN pin (XOUT floating).
8.9.1 Crystal Oscillator
8.9.2 RC-Oscillator
or a power-on-reset happens (e.g. battery change) the calibration has to be repeated. Figure 21. RC-Oscillator calibration via SDI
8.9.3 External Clock Source
and C=22pF). In the Table 24 the clock characteristics are summarized. Table 22. Characteristics of XTAL (initial) Overall accuracy ±120 p.p.m. Table 23. Characteristics of RCO Table 24. Characteristics of External Clock
Note: In power down mode the external clock has to be set to VDD.
9 Package Drawings and Markings
The product is available in 16 pin TSSOP and QFN 4x4 16 LD packages. Figure 22. Package Diagram 16 pin TSSOP Table 25. Package Dimensions 16 pin TSSOP
www.austriamicrosystems.com/AS3930 Revision 1.0 30 - 33 AS3930 Data Sheet - Pack age Drawings and Markings Note: 1. Die thickness allowable is 0.279 ± 0.0127. 2. Dimensioning and tolerances conform to ASME Y14.5M-1994. 3. Datum plane H located at mold parting line and coincident with lead, where lead exits plastic body at bottom of parting line. 4. Datum A-B and D to BE determined where center line between leads exits plastic body at datum plane H. 5. D & E1 are reference datum and do not include mold flash or protrusions, and are measured at the bottom parting line. Mold lash or pro- trusions shall not exceed 0.15mm on D and 0.25mm on E per side. 6. Dimension is the length of terminal for soldering to a substrate. 7. Terminal positions are shown for reference only. 8. Formed leads shall be planar with respect to one another within 0.076mm at seating plane. 9. The lead width dimension does not include dambar protrusion. Allowable dambar protrusion shall be 0.07mm total in excess of the lead width dimension at maximum material condition. Dambar cannot be located on the lower radius or the foot. Minimum space between protrusions and an adjacent lead should be 0.07mm for 0.65mm pitch. 10. Section B-B to be determined at 0.10mm to 0.25mm from the lead tip. 11. Dimensions P and P1 are thermally enhanced variations. Values shown are maximum size of exposed pad within lead count and body size. End user should verify available size of exposed pad for specific device application. 12. All dimensions are in millimeters, angle is in degrees. 13. N is the total number of terminals.
Figure 23. Package Diagram QFN 4x4 16 LD
- Die thickness allowable is 0.279 ± 0.0127.
- Dimensioning and tolerances conform to ASME Y14.5M-1994.
- Dimension b applies to metallized terminal and is measured between 0.25mm and 0.30mm from terminal tip. Dimension L1 represents
terminal full back from package edge up to 0.1mm is acceptable.
- Coplanarity applies to the exposed heat slug as well as the terminal.
- Radius on terminal is optional
Table 26. Package Dimensions QFN 4x4 16 LD
www.austriamicrosystems.com/AS3930 Revision 1.0 32 - 33 AS3930 Data Sheet - Revision History
Revision History
Table 27. Revision History
Copyright © 1997-2009, austriamicrosystems AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®. All products and companies mentioned are trademarks or registered trademarks of their respective companies. Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. austriamicrosystems AG rendering of technical or other services. Table 28. Ordering Information
- Dry Pack Sensitivity Level =3 according to IPC/JEDEC J-STD-033A for full reels.
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