AS3900 AMSCO | Alldatasheet
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Technical content
Datasheet sections
- 1 General Description
- 2 Key Features
- 3 Applications
- 4 Pin Assignment
- 4.1 Pin Description
- 5 Absolute Maximum Ratings
- 6 Electrical Characteristics
- 6.1 Electrical System Specification
- 6.1.1 General
- 6.1.2 Modulation Method
- 6.1.3 Transmission Frame
- 6.1.4 Receiver RX
- 6.1.5 Transmitter TX
- 6.1.6 Wakeup RX
- 6.1.8 XREF Crystal Oscillator 27 MHz
- 6.1.9 Battery Level Detector
- 6.1.10 Power-On-Reset Generator
- 7 Typical Operating Characteristics
- 8 Detailed Description
- 8.1 Network Management
- 8.1.1 Network
- 8.1.2 Link Manager or Network Manager
- 8.1.3 Principle of Communication
- 8.2 Operating Modes
- 8.2.1 Power-down
- 8.2.2 Standby
- 8.2.3 Sleep
- 8.2.4 Pairing
- 8.2.5 Wakeup
- 8.2.6 Data Transmit/Receive
- 8.3 Link Manager
- 8.3.1 Establishing Network
- 8.3.2 Handling the Link Manager
- 8.4 Digital Interface
- 8.4.1 SDI Operation Mode Bits
- 8.4.2 Writing of Data to Addressable Registers (WRITE Mode)
- 8.4.3 Reading of Data from Addressable Registers (READ Mode)
- 8.4.4 Send Single COMMAND byte
- 8.4.5 Read Received Data
- 8.4.6 Interrupt Interface Description
- 8.4.7 Microcontroller Clock Interface
- 8.5 Wakeup Procedure
- 8.5.1 Wakeup Receive Mode
- 8.5.2 Wakeup Transmit Mode
- 8.6 Pairing
27MHz Low Power Star Network Transceiver www.austriamicrosystems.com/RF-Transceivers/AS3900 Revision 1.00c 1 - 59 Data Sheet
1 General Description
The AS3900 is a low power FSK transceiver ideal for battery- operated short range devices (SRD) applications in which a limited amount of data (data rate up to 210 kbit/s) need to be transferred. The device can be configured as transceiver, transmitter only or receiver only system and operates in one channel in the worldwide ISM band at 27 MHz. The frequency of the external oscillator determines the operating frequency. Use of 27 MHz is in particular advantageous for communication in close proximity of the human body due to the low absorption of the signal by tissue because of the low specific absorption rate at 27 MHz. The device incorporates a serial digital interface (SDI), which enables bidirectional communication with external system components. The integrated real-time-clock, sophisticated wake-up functionality, and link manager enable current efficient control of all communication events and eliminate the need for an expensive microcontroller. The AS3900 supports data transfer in burst mode (bidirectional, controlled by link manager), semi-continuous (bidirectional, controlled by microcontroller) and continuous mode (unidirectional, controlled by microcontroller) and requires only a small number of external components.
2 Key Features
FSK transceiver Operating frequency 27.12 MHz (ISM - band) Integrated real-time-clock (RTC) based on 32.768kHz XTAL FM deviation selectable (±106 kHz, ±53 kHz) Data transfer in burst mode and (semi-)continuous mode Data rate adjustable to 26.5, 53, 106, 212 kbit/s Low average current consumption in Tx and Rx mode Output power adjustable to 0, +5, +10 dBm Integrated OOK based wake-up system Link manager for control of star network with up to 8 clients Bidirectional serial digital interface (SDI) Main Characteristics Operating temperature range -40ºC to +85ºC Operating supply voltage 2.2V to 3.6V (Functional down to 2.0V) Rx current consumption 3.8 mA (typ.) Tx current consumption 4.9 mA@0dBm, 7.6 mA @10dBm Maximum output power 10 dBm (delivered to matching network and antenna) Receiver sensitivity –88 dBm @ 106 kbit/s Polling mode average current consumption typ. 2.5µA Power down current consumption max. 700nA Typ. communication range using small antenna 1.2m@0dBm, 2.5m@10dBm QFN 28 pin (5x5) package Additional Features Reliable pairing and synchronization of master and clients Automatic 16 bit CRC computation in burst mode Auto-acknowledgement and re-transmit Programmable timers to assign variable communication cycle times Reliable system start due to internal POR Programmable microcontroller clock frequency Separate interrupt request line Battery level detector Digital RSSI value accessible in register User programmable Identification with OTP memory (24 bits)
3 Applications
The AS3900 is ideal for reliable low-power short-range data exchange, data transfer among devices in close proximity of human body (Body Area Networks), simple control networks (home, industry), and interactive remote controls. A typical application can be designed in combination with a microcontroller, an antenna and a few additional passive components.
Figure 1. Typical Application Diagram of Low Power Star Network Transceiver AS3900
www.austriamicrosystems.com/RF-Transceivers/AS3900 Revision 1.00c 4 - 59 AS3900 Data Sheet - Contents
4 Pin Assignment
Figure 2. AS3900 Pin Assignment (T op View)
4.1 Pin Description
Table 1. QFN 28 pin Package GND 1 S Negative RF Supply Voltage. Ground reference point for VDDRF. positive amplitude. Output Impedance can be programmed to 12.5Ω or 25Ω. negative amplitude. Output Impedance can be programmed to 12.5Ω or 25Ω. Transmitter can be programmed to single ended or differential analog outputs. In single ended mode RF2OUT is connected to GND. NC 8 Not connected. Leave the pin floating. NC 10 Not connected. Leave the pin floating. NC 11 Not connected. Leave the pin floating. 100nF are needed for fuse mode.
point for buffer capacitors of VDD_OTP. NC 14 Not connected. Leave the pin floating. bits are clocked in on the falling edge of SCLK. data from the AS3900. Write and read operation is provided by the SCLK. ends a read or write operation and frames the serial data transfer. Serial Digital Interface DATA output. Serial Data Output for reading registers. microcontroller on the falling edge of SCLK. can be adjusted between 188kHz and 3.39MHz. read manually. An interrupt can be triggered on the rising edge of the IRQ pin. NC 21 Not connected. Leave the pin floating. X27_OUT 22 AO 27MHz oscillator output. Analog output for 27.12MHz crystal oscillator. 100nF and 100pF) are recommended. X32_OUT 26 AO 32kHz oscillator output. Analog output for 32.768kHz crystal oscillator.
5 Absolute Maximum Ratings
to absolute maximum rating conditions for extended periods may affect device reliability. Table 2. Absolute Maximum Ratings for Non-Hermetic Solid State Surface Mount Devices”.
6 Electrical Characteristics
Table 3. Electrical Characteristics supply voltage of 3.3V is needed.
6.1 Electrical Syst em Specification
Table 4. General Table 5. Modulation Method Table 6. Transmission Frame
Table 7. Receiver RX
0 MHz Unmodulated interferer -25 dB
0 MHz Modulated interferer 16 dB
0 MHz Modulated interferer 25 dB
Table 8. Transmitter TX Table 9. Wakeup RX Table 10. RTC Crystal Oscillator 32.768 kHz ial) Overall accuracy ±120 p.p.m. ial + temp + ageing) ±120 p.p.m.
Table 12. Battery Level Detector Table 13. Power On Reset Generator
7 Typical Operating Characteristics
Figure 3. Blocking of Interferer vs Frequency Figure 4. Blocking of Interferer vs Frequency Figure 5. Supply Current vs. Impedance of Antenna+Matching Figure 6. Output Power vs. Impedance of Antenna+Matching Figure 7. Output Power vs. Supply Voltage (PA=differential, Figure 8. Output Power vs. Supply Voltage (PA=single ended,
8 Detailed Description
2.0V and has a built in battery level detector, that level can be read via the SDI interface. in order to limit the allocated bandwidth in the ISM band. An integrated low pass filter cuts off additional interference frequencies. impedance of the antenna and the matching network. The AS3900 features a zero-IF receiver. The receiver consists of a differential low noise amplifier (LNA) that amplifies the incoming RF signal. the incoming signal is down converted (I and Q) to the base band by the mixer. The I/Q signal is filtered and fed to the demodulator. the AS3900 enters the normal RX mode. in the MAIN register. A simplified block diagram of the AS3900 is shown in Figure 9. Figure 9. Block Diagram of Low Power Star Network Transceiver AS3900
8.1 Network Management
sent in short packages with higher data rate.
8.1.1 Network
master. The master manages the parameters used for communication. Figure 10. Star Network
8.1.2 Link Manager or Network Manager
in order to set-up and to maintain up to 8 communication links simultaneously.
8.1.3 Principle of Communication
bytes data). The Client sends this packet at a certain time slot that is allocated for this Client. The timing information is part of every frame. Master and Client are re-synchronized automatically by using this timing information.
8.2 Operating Modes
require different current consumptions.
8.2.1 Power-down
Power-down mode is entered after connecting the battery. The POR signal is provided at the POR pin and registers will have their default values. to avoid leakage currents via the digital lines.
8.2.2 Standby
clock or 32 kHz clock). A Clock Interface Mode selection is required.
8.2.3 Sleep
slots. Timers and 32kHz oscillator are active in this mode.
8.2.4 Pairing
Permanent pairing: The device ID of the Clients are permanently stored in the Master (can be overwritten).
8.2.5 Wakeup
After a Wakeup sequence is received, the exchange of time code is performed and master is synchronized to client time base. Figure 11. Pairing and Wakeup Principle
8.2.6 Data Transmit/Receive
features auto-acknowledgement as well as automatic retransmit of lost data.
8.3 Link Manager
8.3.1 Establishing Network
In order to build up a star network the connections between the Master and all available Clients must be established.
8.3.1.1 Permanent Pairing
verification the ID’s are stored in the Master’s ID registers. After that the Clients are paired to the Master and switched to Power-down mode. See detailed description in 8.6 Pairing.
8.3.1.2 Wakeup and Data Transmit/Receive
acknowledge mode. See detailed description in chapter 8.7 Transmission Modes. Figure 12. Time Division Multiplexing Principle
8.3.2 Handling the Link Manager
In general there are three different actions to operate the link manager.
8.3.2.1 Setting Registers
different data buffers as well as an interrupt table.
8.3.2.2 Sending Direct Commands
device can be activated or deactivated. Some of the commands can also be accessed via the register maps.
8.3.2.3 Handling Interrupt
sources can be enabled or disabled by the use of the Interrupt Mask Register. automatically after reading.
8.4 Digital Interface
Figure 13. Microcontroller Interface
8.4.1 SDI Operation Mode Bits
byte operation. An Enable LOW pulse indicates the end of all possible modes. Table 14. SDI Operation Patterns
8.4.2 Writing of Data to Addr essable Registers (WRITE Mode)
command after register has been written. The following example shows a write command. Figure 14. Writing of a Single Byte (falling edge sampling) applied by remaining SEN to HIGH and providing further clock cycles on SCLK (falling edges). Figure 15. Writing of Register Data with Auto-incrementing Address
8.4.3 Reading of Data from Addressable Registers (READ Mode)
transfer edge and sampled by the microcontroller (SDI master) at the sampling edge of SCLK. prepare the Interface to the next command control Byte. clock has to be active as long as data need to be read from the slave. the data remains consistent and each data byte belongs to the given or incremented address. In the following figures two examples for a read command (without and with address self-increment) are given. Figure 16. Reading of a Single Register Byte incrementing Read cycle can be applied by remaining SEN to HIGH and providing further clock cycles on SCLK (falling edges). Figure 17. Reading of Register Data with Auto-incrementing Address
8.4.4 Send Single COMMAND byte
Command mode is entered if the SDI read is started with two leading ONE. After the COMMAND mode code (11), the further mode (e.g. DATA_TRANSMIT) could be provided from the MSB to the LSB or <C5-C0>. If <C5-C0> = 0 no mode change (used for Load Transmitting Data). Figure 18. Single COMMAND byte Table 15. Direct Commands
8.4.5 Read Received Data
After successfully receive of the data the interrupt line is set. The microcontroller reads the interrupt register (with this read the IRQ line is reset). The microcontroller reads the ADDRESS (ID) to which sensor the data belongs. The microcontroller reads the DATALEN register. With this read the received DATA is transferred to the SDI output register and clocked out by means of the SDI Clock (SCLK).
8.4.6 Interrupt Interface Description
If an interrupt condition is met a HIGH level is applied to the IRQ pin. The IRQ level is set to LOW level after reading the Interrupt registers. Figure 19. Interrupt Operation Table 16. Interrupt Electrical Interface Description
Table 17. T able of Interrupts stream_end [4] In client mode it indicates new data should be written into send register. Table 18. T able of Interrupt Mask Registers
0x2B to release the IRQ line again.
8.4.7 Microcontroller Clock Interface
information on the operation modes of the clock output see Table 20. Clock Interface Modes. Table 19. Clock Interface Electrical Description Table 20. Clock Interface Modes Table 21. Clock Division Ratios 1 MCUclk_Off 0 0 No clock is provided to pin MCU_CLK. Output Level is set to LOW.
3 MCUclk_27M 1 0
4 MCUclk_32K/27M 1 1
switches off the MCU_CLK output.
8.5 Wakeup Procedure
Master Wakeup sequences. If the Client (Master) receives a Wakeup sequence the link manager triggers the wake_call interrupt. INTERRUPTS, which need to be read out as soon as an external interrupt on the IRQ line appears.
8.5.1 Wakeup Receive Mode
sumption is defined by the ON to OFF ratio of the Wakeup receiver.
8.5.2 Wakeup Transmit Mode
Wakeup Transmitter On time: The Wakeup call can be applied between 125ms up to 1s in REG 0x04<1:0>. Longwake TX: The Wakeup call can be applied as long as the longwake_tx bit is set in REG 0x04<5>. figure shows the Wakeup procedure. Figure 20. Wakeup Transmit Mode Table 22. Wakeup Procedure Initialized by the Master listening cycle-time is defined by the wakecyc bits, REG 0x04<4:2>. the long wake_tx bit, REG 0x04<5> has to be used).
8.6 Pairing
8.6.1 Procedure
side has to calculate a random delay (less than 1sec). automatic acknowledgement (ACK). Table 23. Pairing Procedure
Note: It i s important that for the Pairing procedure all Timers need to be disabled. Set REG 0x02 to 0.
8.6.2 Master Initializes Pairing (wakeup) Procedure
Table 24. Configuration Registers The following sequence explains the operations that need to be done by the MCU at the Master and Client. nodes pass into Standby Mode again. Pairing” except that no Wakeup call and no handshake are done. Cycletime, period between two TX operations is only defined by the Client. TX_data 0x08… 0x1F Main Data in TX register will be appended to the ID and cycle time information.
Figure 21. Pairing Master
Table 25. Pairing Communication listening time, the Clients transmit randomly their first data.
2 After the MCU defined delay time expires, the Client starts the first
transmission via the command TRANSMIT. sent back to signal the Client that it has been accepted. Interrupt dat_rtx is set and the MCU could read the data. event, because all timers are disabled for the pairing procedure. no information for cycle time and RNG-pointer is available. Client is accepted at the next wake up call. sent to the Client even if the Client tries to connect again. activated data transmission, nothing is changed. MCU can then repeat the TRANSMIT command after a certain delay.
8.7 Transmission Modes
surrounding field. All participants of the network are determined after the pairing procedure. Table 26. Transmission Modes Table 27. Selection Transmission Modes an appropriate application note. acknowledgement 4 bytes of data for the Client (ACP). into the data registers which can be read out by the MCU. of the ID with the ID-table the incoming data is loaded into the data registers.
8.7.1 Packet mode – Bidirectional – Timer Controlled
Figure 22. Acknowledgement
Table 28. Communication listening time, the Clients transmit randomly their first data. stored in the master’s timing table in SREG 0x0C to 0x13. communication and before next. the dedicated bitrate and the payload data length dlen.
error counter (cesX) for the according Client is cleared. error counter (ces0) is cleared. the affected timer is turned off in REG 0x01. generated for the MCU. The cesX counter is not changed. data retransmission from the same Client. the interrupt nar_rtx is generated but no retransmit is initiated.
8.7.2 Scan Procedure
application of these scan modes are Clients that are taken out of range and want to be reconnected again. can be applied by the direct command SCAN. consumes 2.2mA supply current. Figure 23. Reconnecting Client / Updating Actual Time Base guard time is defined by the bits pretm in REG 0x02<7:5>. communication error counter ces0 is increased, due to no reply.
Figure 24. Pairing Clients via Longscan Table 29. Scan / Reconnect / Pair Clients to be enabled via the REG 0x01<7:0>. counter need to be disabled, otherwise the Client timer would stop. The Client transmit one packet via the command TRANSMIT. sent back to signal the Client that it has been accepted. Interrupt dat_rtx is set and the MCU could read the data.
8.8 Data Frames
8.8.1 Frame Structure for Timer Controlled Packet Mode
length value given in the data length byte. ID, Cycle time and Random Generator Pointer are user defined. Table 30. Frame Structure Table 31. Frame Structure Description appropriate application notes.
8.8.2 Frame Structure for ACKNOWLEDGE (ACK)
After data was received successfully (correct ID and no CRC error) ACK will be send. Table 32. Frame Structure new ID via SDI to the ID list REG 0x08 to 0x1F. the command TRANSMIT. The procedure is repeated at Step 2.
8.8.3 Frame structure for ACKNOWLEDGE with appended data (ACP)
After data was received successfully (correct ID and no CRC error) by the Master ACP will be send else NAK or NAP are send. Table 33. Frame Structure
8.8.4 Frame Structure for NOT-ACKNOWLEDGE (NAK)
After any data error at reception time window (incorrect ID and / or CRC error) NAK will be send. value for the separate Clients in SREG 0x14 to 0x17. Table 34. Frame Structure
8.8.5 Frame Structure for NOT-ACKNOW LEDGE and Data Retransmit (NAR)
After a CRC data error at reception time window (correct ID and CRC error) NAR will be send. Table 35. Frame Structure
8.9 Configuration Registers
Main (bit value = 0) or the Shadow (bit value = 1) Register Bank.
8.9.1 Main Register Bank (ADDRESS 0x00 bit<0>=0)
Table 36. Main Register Bank (ADDRESS 0x00 bit<0>=0)
8.9.2 Shadow Register Bank (ADDRESS 0x00 bit<0>=1)
Table 37. Shadow Register Bank (ADDRESS 0x00 bit<0>=1)
8.9.3 Detailed Description
interface in Client and Master mode. registers are directly addressable.
8.9.3.1 Main Register Bank (ADDRESS 0x00 bit<0>=0)
Table 38. Main Register Bank (ADDRESS 0x00 bit<0>=0)
0 Disabled
1 Enabled
0 Enabled
1 Disabled
0 Bidirectional
1 Unidirectional
0 Main Bank selected
1 Shadow Bank selected
00000001 Enable Timer for Client 0
00000010 Enable Timer for Client 1
00000100 Enable Timer for Client 2
00001000 Enable Timer for Client 3
00010000 Enable Timer for Client 4
00100000 Enable Timer for Client 5
01000000 Enable Timer for Client 6
10000000 Enable Timer for Client 7
11111111 Enable all Timers
00000000 Disabled
00000001 Enabled
000 Errors ignored
0 Disabled, pairing / binding duration is 1 sec
1 Enabled; pairing / binding mode as long as bit is 1
00 No retransmit
0 ON for the time set by register waketm<1:0>
1 ON as long as value of longwake_tx is 1
00 OFF
0 Deviation = ± 106 kHz
1 Deviation = ± 53 kHz
0 Analog value (inverted output register bat_ok)
1 Digitally faked set value (output register is lowbatval_tx)
0 Battery OK
1 Battery LOW
manually set if datarate is set to 212kbps for Master and Client.
0 Datarate less than 212 kbit/sec
1 Datarate 212 kbit/sec
automatically during OOK modulation in the signal OFF period.
Signals that the battery voltage is higher than the level defined by bat<1:0>.
0 BATTERY Low
1 BATTERY OK
00000001 Timer for Client 0 is running
00000010 Timer for Client 1is running
00000100 Timer for Client 2 is running
00001000 Timer for Client 3 is running
00010000 Timer for Client 4 is running
00100000 Timer for Client 5 is running
01000000 Timer for Client 6 is running
10000000 Timer for Client 7 is running
11111111 Timers for all Clients are running
00000000 Timer at Client is stopped
00000001 Timer at Client is running
8.9.3.2 Shadow Register B ank (ADDRESS 0x00 bit<0>=1)
Table 39. Shadow Register Bank (ADDRESS 0x00 bit<0>=1)
000 Last packet received successfully
8.10 Feature Description
This chapter describes how to apply certain features of the device.
8.10.1 One Time Programmable Memory (OTP)
documents P2PROM_rev1.322 and PPROM_appl_note_C. The ID data has to be written into the Shadow Register Bank REG 0x08, 0x09, 0x0A.
8.10.1.1 Write to the OTP register
Register Bank register dprom in REG 0x08 to 0x0A. These are already the physical PPROM registers, which are ready to be programmed.
8.10.1.2 Programming of the OTP
values read from the ID0 register must be the same as the programmed ones.
8.10.1.3 Read the Fuses
values are loaded to the ID0 register.
8.10.1.4 Read the Fuses and Load to ID0 Register
The same procedure is performed with the POR Signal automatically.
8.10.2 Communication Er ror Counter (cesmax)
automatic disabling of the Timer at Master and/or Client side. set in cesmax in REG 0x02<2:0>, the according Timer is turned off. error would increase the cesX field starting from the initial value, which allows the disabling of the dedicated Timer at fewer counts. At the Client, the Timer goes inactive that is signaled when the activeTimer0 is reset to ‘0’. REG 0x27<0> is se t to 0. Clients are lost, the Master does not stop its transmission at the dedicated time slots. Table 40. Actual Communication Error Count cesX
8.10.3 Cycle Time and Random Pointer
automatically in the Masters timing table in register REG 0x0C to 0x13<4:0>. dlen in register REG 0x37<4:0>. The data rate is defined in REG 0x06<1:0>. are static. Using the random pointer results in spontaneously changing the time slot, as denoted for Client 1 (yellow packets).
Figure 25. Battery Level Indicator
8.10.4 Battery Level Indicator
0x07<7>. Depending on this setting the comparator output bit is routed to lowbatval_tx in REG 0x07<6> or Lbat_ok in REG 0x23<6>. With this algorithm the reference level is always updated and reflects the actual battery level that can be read out in REG 0x 21<1:0>.
8.10.5 Output Power Selection
The AS3900 has a kind of integrated class D power amplifier that output power can be changed by changing the load impedance seen by the PA. Furthermore the output power can be varied by the switching from differential output to single ended mode.
8.10.5.1 Single Ended / Differential
the crystal oscillator. This adjustment can be set via the single bit in the REG 0x21<2>. Note: It is important to note that the PA switches their output automatically to GND during the AS3900 is in receive mode (LNA is tur ned on). It is possible to set the PA outputs manually to GND via the bit fzero in REG 0x21<0>.
8.10.5.2 Output Impedance
implemented to prevent the AS3900 from burning, if the outputs of the PA are shorted.
8.10.5.3 Calculation of the load impedance for a desired output power
In differential mode peak is equal to VDD, in single ended mode peak is equal to VDD/2. Note: It i s important to note that the overall emitted power of the PA is mainly defined by the VDD and the impedance of the antenna itself. The Rout of the PA gives only a minor change to the emitted power. Figure 26. Power Amplifier Conditions: VDD= 3V, Differential output mode, 10dBm is the desired output power.
8.10.6 RSSI
rssi field provides a digital value for signal strength between 0µVrms and 150µVrms. The rssi field is valid for the Client that communicates currently with the Master, which can be identified via the sid in REG 0x33<2:0>.
9 Application Information
the AS3900 Block, the MCU and an antenna. Figure 27. AS3900 Application diagram
9.1 Microcontroller
internal overvoltage protection circuit could get activated. As system frequency the MCU_CLK can be used, that reduces the BOM of the MCU. An external interrupt input at the MCU is necessary in order to control the link manager.
9.2 Crystal Oscillators
specification of ±120ppm. A small SMD crystal is used in the demo board. Table 41. Recommended Crystal Oscillators
9.3 Power Supply
VDD_OTP). Small-sized X5R or X7R ceramic capacitors are recommended. Note: VDD_OTP is only needed in fuse mode, and requires 3.6V for burning the internal fuses. Otherwise VDD_OTP need not be connect ed.
9.4 Antenna
Pseudo SMD electric antenna: A λ/4 antenna is wound to a coil but acts totally electric.
9.5 Tuning Circuit
mode the PA is shorted to GND. over wide range of voltage and temperature. a PCB loop antenna with a parallel resonance tuning circuit. The AS3900 requires following external components. Table 42. External Components
3 C5, C7,C12 100nF X7R, 25V, 0603, Ceramic capacitor ±10% Supply Voltage de-coupling capacitor
4 C6, C8, C13 100pF X7R, 25V, 0603, Ceramic capacitor ±10% Supply Voltage de-coupling capacitor
5 C12 10µF X5R, 16V, 0805, Capacitor ±10% OTP Fuse Mode only
6 C9, C11 10pF to 47pF COG, 50V, 0603, Ceramic capacitor ±5% PA decoupling capacitor; antenna dependant
The product is available in a QFN 28 pin package. Figure 28. AS3900 Package Diagram terminal full back from package edge to 0.1mm is acceptable. Table 43. Dimensions
Table 44. Ordering Information
- Dry Pack Sensitivity Level =3 according to IPC/JEDEC J-STD-033A for full reels.
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