Power Management

AS3709

ams AG

關PMIC with 5 DCDC and 2 LDOs

Manufacturer: ams AG

Document: 74 Pages / 930Kb

Request Quote Download Datasheet Read online HTML view

Read AS3709 online.

DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM

Document overview

Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 74

Technical content

ams Datasheet, Confidential: 2013-Aug [1-02] AS3709 – 1 AS3709 μPMIC with 5 DCDC and 2 LDOs The AS3709 is an ultra compact μPMIC containing 5 high-efficiency, constant-frequency synchronous buck converters in addition with two universal IO LDOs are available for lower current power rails. The wide input voltage range (2.7V to 5.5V), automatic power-save mode and minimal external component requirements make the AS3709 perfect for any single Li-Ion battery-powered or fixed 3.3V/5V supply application. Typical supply current with no load is 110μA and decreases to ≤ 7μA in shutdown mode. An internal synchronous switch increases efficiency and eliminates the need for an external Schottky diode. The internally fixed switching frequency (2MHz, 3MHz or 4MHz) allows the use of small surface mount external components. Very low output voltages can be delivered with the internal 0.6V feedback reference voltage. The AS3709 is available in a 32-p in QFN 4x4mm package and in a very compact CSP36 with 0.4mm pitch. For further understanding in regards to the contents of the datasheet, please refer to the Reference Guide located at the end of the document. Key Benefits & Features The benefits and features of AS3709, μPMIC with 5 DCDC and 2 LDOs are listed below: Figure 1: Added Value of using AS3709 Benefits Features Compact design due to small coils for IO and memory voltage generation 5 DCDC step down regulators (2-4MHz) Independent voltage rails for general purpose IO supplies 2 universal IO LDOs Flexible and fast adaptation to different processors/applications OTP programmable Boot and Power-down sequence Power saving control according to the processor‘s needs. Stand-by function with programmable sequence and voltages Self-contained start-up and control for single-cell battery applications. Safety shutdown feature. Control Interface I²C/SPI control lines ON key with 4/8s emergency shut-down POR with RESET I/O Dedicated packages for specific applications. Optimization for PCB cost or size. 32-pin QFN (4x4mm), 0.4mm pitch 36-ball WL-CSP 0.4mm pitch General Description

AS3709 – 2 ams Datasheet, Confidential: 2013-Aug [1-02]

Applications

The device is ideal for:

SSDs, mobile communication devices
L a p t o p s a n d P D A s
Ultra-low-power systems
Medical instruments or any other space-limited application with low power-consumption requirements. Block Diagram The functional blocks of this device for reference are shown below: Figure 2: AS3709 Block Diagram GPIOs DCDC1 0.7 – 1A 0.6 – 3.35V 2 – 4MHz LDO1 PMOS 0.6 0.8 – 3.3V 300mA I2C System Control Reference Supervisor (Supply & Temp) POR BOOT ROM OTP AS3709 LDO2 PMOS 0.6 0.8 – 3.3V 300mA SCLK ON XRES V2_5 VSSA GPIO1 LDO1 VIN_LDO2 LDO2 VSS_LDO2 VSUP_SD1 LX_SD1 FB_SD1 PVSS_SD1 2.2uF 1uH 1uF 10uF DCDC2 0.7 – 1A 0.6 – 3.35V 2 – 4MHz VSUP_SD2 LX_SD2 FB_SD2 PVSS_SD2 2.2uF 1uH 10uF DCDC3 0.7 – 1A 0.6 – 3.35V 2 – 4MHz VSUP_SD3 LX_SD3 FB_SD3 PVSS_SD3 2.2uF 1uH 10uF DCDC4 0.7 – 1A 0.6 – 3.35V 2 – 4MHz VSUP_SD4 LX_SD4 FB_SD4 PVSS_SD4 2.2uF 1uH 10uF DCDC5 0.7 – 1A 0.6 – 3.35V 2 – 4MHz VSUP_SD5 LX_SD5 FB_SD5 PVSS_SD5 2.2uF 1uH 10uF VSUP VSUP VSUP VSUP VSUP SD1 SD2 SD3 SD4 SD5 GPIO2 SDA 2.2uF 2.2uF VIN_LDO1 VSS_LDO12.2uF 2.2uF VSUP VSUP

ams Datasheet, Confidential: 2013-Aug [1-02] AS3709 – 3 Pin Assignment The AS3709 pin assignme nts are described below. Figure 3: 36 balls WL-CSP with 0.4mm Pitch Figure 4: 32 pins QFN 4x4 with 0.4mm Pitch Ball Assignments: Shows the top view ball assignment of the AS3709 WL-CSP . Pin Assignment: Shows the top view pin assignment of the AS3709 QFN package. Pin Assignment XRES GPIO2 VSUP SD1 PVSS SD1 LX_SD1 ON VSSA SDA V2_5 GPIO1 LDO1 SCL FB_SD5 FB_SD1 LDO2 Pin A1 indicator PVSS SD5 LX_SD5 LX_SD4 PVSS SD4 VSUP SD5 FB_SD4 VSUP SD2 PVSS SD2 LX_SD2 FB_SD3 VIN LDO1 FB_SD2 VIN LDO2 VSUP SD3 PVSS SD3 LX_SD3 AS3709 QFN 32-pin 4x4mm Exposed Pad: GND VSUP_SD1 SCLLX_SD5 VSUP_SD4 PVSS_SD4 VSUP_SD3 PVSS_SD1 VSUP_SD2 LX_SD1 V2_5 FB_SD1 LX_SD2 VSUP_SD5 LX_SD4 FB_SD4 LX_SD3

28 GPIO2

27 XRES

25 SDA

32 PVSS_SD5

31 FB_SD5

30 VSSA

29 GPIO112LDO2

11VIN_LDO2 10FB_SD3 9PVSS_SD3 16PVSS_SD2 15FB_SD2 14VIN_LDO1 13LDO1

AS3709 – 4 ams Datasheet, Confidential: 2013-Aug [1-02] Pin Assignment Figure 5: Pin Description Pin Number Pin Name Pin Type Description If not Used QFN WLP

1 B5 LX_SD5 DIG OUT DCDC SD5 switch output to coil Open

2 B6 VSUP_SD5 SUP IN DCDC SD5 pos supply terminal Always needed

3 B6 VSUP_SD4 SUP IN DCDC SD4 pos supply terminal Always needed

4 C6 LX_SD4 DIG OUT DCDC SD4 switch output to coil Open

5 D5 PVSS_SD4 GND DCDC SD4 neg supply terminal Always needed

6 C5 FB_SD4 ANA IN DCDC SD4 Feedback pin Open

7 E6 VSUP_SD3 SUP IN DCDC SD3 pos supply terminal Always needed

8 E5 LX_SD3 DIG OUT DCDC SD3 switch output to coil Open

9 F5 PVSS_SD3 GND DCDC SD3 neg supply terminal Always needed

10 E4 FB_SD3 ANA IN DCDC SD3 Feedback pin Open

11 F4 VIN_LDO2 SUP IN Supply pin for LDO2 Always needed

12 D4 LDO2 ANA OUT Output Voltage of LDO2 Open

13 D3 LDO1 ANA OUT Output Voltage of LDO1 Open

14 F3 VIN_LDO1 SUP IN Supply pin for LDO1 Always needed

15 E3 FB_SD2 ANA IN DCDC SD2 Feedback pin Open

16 F2 PVSS_SD2 GND DCDC SD2 neg supply terminal Always needed

17 E2 LX_SD2 DIG OUT DCDC SD2 switch output to coil Open

18 E1 VSUP_SD2 SUP IN DCDC SD2 pos supply terminal Always needed

19 C3 FB_SD1 ANA IN DCDC SD1 Feedback pin Open

20 D2 PVSS_SD1 GND DCDC SD1 neg supply terminal Always needed

21 C2 LX_SD1 DIG OUT DCDC SD1 switch output to coil Open

22 C1 VSUP_SD1 SUP IN DCDC SD1 pos supply terminal Always needed

23 B1 V2_5 ANA OUT Internal 2.5V regulator output Always needed

24 A1 SCL DIG IN 2-wire Serial IF Clock Input Open

25 B2 SDA DIG IO 2-wire Serial IF Data IO Open

26 B3 ON DIG IN Power Up Input Open

27 A2 XRES DIG IO Reset IO, external pull-up resistor needed Always needed

ams Datasheet, Confidential: 2013-Aug [1-02] AS3709 – 5 Pin Assignment

28 A3 GPIO2 ANA IO General Purpose IO 2 Open

29 C4 GPIO1 ANA IO General Purpose IO 1 Open

30 A4 VSSA GND GND Reference for analog blocks Always needed

31 B4 FB_SD5 ANA IN DCDC SD5 Feedback pin Open

32 A5 PVSS_SD5 GND DCDC SD5 neg supply terminal Always needed

33 VSS GND Exposed Pad Always needed

Pin Name Pin Type Description If not Used QFN WLP

AS3709 – 6 ams Datasheet, Confidential: 2013-Aug [1-02] Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under “Operating Conditions” is not im plied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Figure 6: Absolute Maximum Ratings Symbol Parameter Min Max Units Comments Electrical Parameters Supply Voltage to Ground 5V pins -0.5 7.0 V Applicable for pins: VSUP_SDx, VIN_LDOx, SCLK, SDA, ON, XRES, GPIOx, LX_SDx Supply Voltage to Ground 3V pins -0.5 5.0 V Applicable for pins: V2_5, LDOx, FB_SDx Voltage Difference between Ground Terminals -0.3 0.3 V Applicable for pins: VSSA, PVSS_SDx, Exposed Pad Input Current (latch-up immunity) -100 100 mA Norm: JEDEC JESD78 Continuous Power Dissipation (T A = +70°C) PT Continuous power dissipation

1.2 W PT

(1) for QFN32 package (RTHJA ~ 45K/W)

1.1 W PT

(1) for WL-CSP36 package (RTHJA ~ 50K/W) Electrostatic Discharge VESD-HBM Electrostatic Discharge HBM ±2 kV Norm: JEDEC JESD22-A114F Temperature Ranges and Storage Conditions TAMB Operating Temperature -40 +85 °C TJ Junction Temperature +125 °C Storage Temperature Range -55 +150 °C QFN Storage Temperature Range -55 +125 °C WL-CSP Humidity non-condensing 85 % Absolute Maximum Ratings

ams Datasheet, Confidential: 2013-Aug [1-02] AS3709 – 7 Absolute Maximum Ratings Note(s) and/or Footnote(s): 1. Depending on actual PCB layout and PCB used. 2. The reflow peak soldering temperature (body temperature) is specified according IPC/JEDEC J-STD-020 “Moisture/Reflow Sensiti vity Classification for Non hermetic Solid State Surface Mount Devices Temperature (Soldering) 32-pin QFN: Norm IPC/JEDEC J-STD-020 (2) The lead finish for Pb-free leaded packages is matte tin (100% Sn) Norm IPC/JEDEC J-STD-020 (2) MSLQFN Moisture Sensitive Level 3 Represents a maximum floor life time of 168h MSLWL-CSP Moisture Sensitive Level 1 Represents an unlimited floor life time Symbol Parameter Min Max Units Comments

AS3709 – 8 ams Datasheet, Confidential: 2013-Aug [1-02]

Electrical Characteristics

All limits are guaranteed. The parameters with min and max values are guaranteed with production tests or SQC (Statistical Quality Control) methods. Figure 7: Electrical Characteristics: VSUP = 3.7V, VOUT < VIN – 0.5V, TAMB = -40°C to +85°C, typ. values @ TAMB = +25°C (unless otherwise specified) Symbol Parameter Conditions Min Typ Max Unit VIN Input Voltage range Pin VSUP 2.7 5.5 V IQ Quiescent Current Normal operating current. With bit Low_power_on = 0; only V2_5 active 155 200 μAILOWPOWER Low-Power Quiescent Current Normal operating current. With bit Low_power_on = 1; only V2_5 active 110 IPOWEROFF Shutdown Current With bit power_off = 1; only V2_5 is active in power OFF mode. Not tested, guaranteed by design 72 0

ams Datasheet, Confidential: 2013-Aug [1-02] AS3709 – 9 Detailed Description - Power Management Functions Step Down DCDC Converter The step-down converter is a high-efficiency fixed frequency current mode regulator. By using low resistance internal PMOS and NMOS switches, efficiency up to 95% can be achieved. The fast switching frequency allows using small inductors, without increasing the current ripple. The unique feedback and regulation circuit guarantees op timum load and line regulation over the whole output voltage range, up to an output current of 1A, with an output capacitor of only 10μF. The implemented current limitation protects the DCDC Converter and the coil during overload condition. Figure 8: Step Down DC/DC Converter Block Diagram Detailed Description - Power Management Functions Logic +- + S IMIN ILIMIT 250mA 1.2A ISENSEP ISENSEN Zero Comparator PWM Comparator Overvoltage Comparator Ref + 8% Ref - 5% Slope Compensation Softstart Ref = 0.6VSkip Sd_low_noise Clk Sd_lv buck_v FB_SD VSS_SD LX_SD VOUT VSUP 2.2uF 1uH 10uF

AS3709 – 10 ams Datasheet, Confidential: 2013-Aug [1-02] Detailed Description - Power Management Functions Mode Settings To allow optimized performance in different applications, there are bit settings possible, to get the best compromise between high efficiency and low input/output ripple. Low-Ripple, Low-Noise Operation Low-ripple, low-noise operation can be enabled by setting bit sd_low_noise = 1. In this mode there is no minimu m coil current necessary before switching OFF the PMOS. As long as the load current is superior to the ripple current, the device operates in continuous mode. When the load current gets lower, the discontinuous mode is triggered. Resultant the auto-z ero comparator stops the NMOS conduction to avoid load disc harger and the duty cycle is reduced down to t MIN_ON to keep the regulation loop stable. This results in a very low ri pple and noise, but decreased efficiency at light loads, especially at low input to output voltage differences. Only in the case the load curren t gets so small, that less than the minimum on time of the PMOS would be needed to keep the loop in regulation, the regulator will enter low power mode operation. The crossover point is about 15mA for V IN = 3V, V OUT = 1.2V, 1μH, 4MHz. Figure 9: DC/DC Buck Low Noise Mode High-Efficiency Operation (Default Setting) High-efficiency operation is enabled by setting bit sd_low_noise = 0. In this mode there is a minimu m coil current necessary before switching OFF the PMOS. Resultant there are less pulses DC/DC buck burst mode: Shows the DC/DC switching waveforms for low noise operation. VOUT (50mV/div) LX (2V/div) coil current (200mA/div) time (5us/div)

ams Datasheet, Confidential: 2013-Aug [1-02] AS3709 – 11 Detailed Description - Power Management Functions necessary at low output loads, and therefore the efficiency increases. As drawback, this mode increases the ripple up to a higher output current. The crossover point to low power mode is already reached at reasonable high output currents. (e.g. @110mA for V IN = 3V, VOUT = 1.2V, 1μH, 4MHz) Figure 10: DC/DC Buck High Efficiency Mode Low Power Mode Operation (Automatically Controlled) As soon as the output voltage stays above the desired target value for a certain time, some internal blocks will be powered down leaving the output floating to lower the power consumption. Normal operation starts as soon as the output drops below the target value for a similar amount of time. To minimize the accuracy error some internal circuits are kept powered to assure a minimized output voltage ripple. Two addition guard bands, based on comparators, are set at ±5% of the target value to react quickly on large over/undershoots by immediately turning on the output drivers without the normal ti me delays. This ensures a minimized ripple also in very extreme load conditions. DVM (Dynamic Voltage Management) To minimize the over-/undersho ot during a change of the output voltage, the DVM can be enabled. With DVM the output voltage will ramp up/down with a selectable slope after the new value was written to the registers. Without DVM the slew rate of the output voltage is only determined by external components like the coil and load capacitor as well as the load current. DVM can be selected for all step-down converters, but only for one at a time. (see sd_dvm_select and dvm_time description) DC/DC buck burst mode: Shows the DC/DC switching waveforms for high efficiency operation VOUT (50mV/div) LX (2V/div) coil current (200mA/div) time (20us/div)

AS3709 – 12 ams Datasheet, Confidential: 2013-Aug [1-02] Detailed Description - Power Management Functions Fast Regulation Mode This mode can be used to react faster on sudden load changes and thus minimize the over-/unde rshoot of the output voltage. This mode needs a 22uF output capacitor instead the 10uF one to guarantee the stability of the regulator. The mode is enabled by setting sd_fast =1. Selectable Frequency Operation Especially for very low load conditions, e.g. during a sleep mode of a processor, the switching frequency can be reduced to achieve a higher efficiency. The frequency can be set to 2, 3 or 4MHz and this mode is selected by setting sd_freq and sd_fsel to the appropriate values. 100% PMOS ON Mode for Low Dropout Regulation For low input to output voltage difference the DCDC converter can use 100% duty cycle for the PMOS transistor, which is then in LDO mode. Step Down Converter Configuration Modes The step down dc/dc converters have two configuration modes to deliver different output currents for the applications. The operating mode is selected by setting the bit sd2_slave , sd4_slave and sd5_slave (the default is set by the Boot-OTP). Figure 11: DCDC Step Down Normal Operating Mode Normal Operating Mode: sd2_slave = 0, sd4_slave = 0, sd5_slave = 0 DCDC Step Down 3 VSUP_SD3 LX_ SD3 FB_SD3 PVSS_SD3 2. 2 u F 1u H 10 uF VSUP DCDC Step Down 4 VSUP_SD4 LX_ SD4 FB_SD4 PVSS_SD4 2. 2 u F 1u H 10uF VSUP DCDC Step Down 5 VSUP_SD5 LX_ SD5 FB_SD5 PVSS_SD5 2. 2 u F 1u H 10uF VSUP DCDC Step Down 1 VSUP_SD1 LX_ SD1 FB _SD1 PVSS_SD1 VSUP 10uF 2.2 uF SD1 0.6 – 3 .3 V 0. 7 – 1A 1uH DCDC Step Down 2 VSUP_SD2 LX_ SD2 FB _SD2 PVSS_SD2 VSUP 10uF 2.2 uF 1uH 5 x 1A SD2 0.6 – 3 .3 V 0. 7 – 1A SD3 0.6 – 3 .3V 0.7 – 1 A SD4 0.6 – 3 .3V 0.7 – 1 A SD5 0.6 – 3 .3V 0.7 – 1 A

ams Datasheet, Confidential: 2013-Aug [1-02] AS3709 – 21 Detailed Description - Power Management Functions Universal IO LDO Regulators 2 universal IO range LDOs offer a wide input (1.8V to 5.5V) as well as a wide output (0.8 to 3. 3V) voltage range to be used for general purpose peripheral su pply. Up to 300mA possible output currents are offered with good noise and regulation performance and very low quiescent current even suitable for stand-by power supply. Figure 28: Universal IO LDO Block Diagram AS3709 LDO: Shows the detailed Universal IO LDO Block Diagram VIN_LDOx LDOx Error AmplifierVref 2.2uF 2.2uF PMOS Power Device VSS_LDOx

AS3709 – 22 ams Datasheet, Confidential: 2013-Aug [1-02] Detailed Description - Power Management Functions Parameter Figure 29: Universal IO LDO Electrical Characteristics Note: Guaranteed by design and verified by laboratory ev aluation and characterization; not production tested Symbol Parameter Note Min Typ Max Unit VIN Input Voltage Range Pin VIN_LDOx 1.75 5.5 V VOUT_TOL Output Voltage Tolerance Min. 40mV -3 +3 % VOUT Output Voltage Range Pin LDOx IOUT < 150mA, 25mV steps 0.825 3.3 V IOUT_L Output current (Note:) ldoX_ilimit = 0 (150mA) 01 5 0 m A ILIMIT_L Current limit (Note:) 300 mA IOUT_H Output current (Note:) ldoX_ilimit = 1 (300mA) 03 0 0 m A ILIMIT_H Current limit (Note:) 500 mA RON On resistance LDO1, LDO2 0.6 Ω PSRR Power supply rejection ratio f=1kHz 60 dB f=100kHz 30 IOFF Shut down current 100 nA IQ Quiescent Current Without load 30 43 μA tSTART Startup time Low current used during start-up 500 us VLNR Line Regulation Static 0.07 %/V Transient; Slope: tr=15μs; delta 1V 20 mV VLDR Load Regulation Static 0.014 %/m A Transient; Slope: tr=15μs; 1mA -> 300mA 30 mV

AS3709 – 24 ams Datasheet, Confidential: 2013-Aug [1-02] Detailed Description - System Functions Start-up Normal Start-up During a normal reset cycle (e.g. after the battery is inserted), after V2_5 is above V POR and VSUP is above ResVoltRise a normal startup happens:

Configuration of DCDCs (combined mode or separated) is read from the Boot-OTP
Startup State machine read s out the internal Boot-OTP
Reset-Timer is set by the Boot-OTP
The reset is released when the Reset Timer expires (external pin XRES) Parameter Figure 33: ON Input Start-up Condition Symbol Parameter Note Min Typ Max Unit VON_IL ON Low Level Voltage 0.4 V VON_IH ON High Level Voltage 1.4 V ION_PD ON Pull Down Current 4 12 μA Detailed Description - System Functions

ams Datasheet, Confidential: 2013-Aug [1-02] AS3709 – 25 Detailed Description - System Functions Figure 34: Start-up Flowchart Start-Up VSUP connected 1. V2_5 power up 2. Readout ROM fuseauto_off = 1 POWER OFF state V2_5 power up Quiescent current < 10uA Pin ON debounce time=20msec Y on_input = 1 N auto_off = 1 or power_off_at_vsuplow = Y VSUP debounce state Measuring VSUP Quiesent current ~200uA N VSUP > ResVoltRise for more than 5ms N N on_input = 1 N VSUP < ResVoltFall for more than 500ms Y N Y Y Y power_off = 1 OFF delay wait off_delayN Reset all Registers Switch off Regulators reset registers and reload fuses expect: pwr_off_at_vsuplow Y RUN startup sequence regulator startup sequence GPIO programming during sequence startup delay programmable RESET Timer regulator startup executed waiting time to release XRES pin 2..160ms ACTIVE state XRES = 1 standby_mode_on = 1 or GPIOx = 1 if gpiox_iosf = 6 OFF delay wait off_delay N STAND-BY state V2_5 power up all regulators with sdX_stby_on = 1 or ldoX_stby_on = 1 enabled any interrupt applied or on_input = 1 force_reset = 1 or (XRES is low if stdby_reset_disable = 0) or VSUP < ResVoltFall or tco_140_a = 1 N N Y Y remove stand-by force off of all regulators Die temp > 140°C (tco_140_a = 1)Y power_off = 1 or force_reset = 1 or XRES is low or VSUP < ResVoltFall or tco_140_a = 1 or ON long-press N Y Die temp > 110°C (tco_110_a = 1) N Y N any state

AS3709 – 26 ams Datasheet, Confidential: 2013-Aug [1-02] Detailed Description - System Functions Reset XRES is a low active bi-directional pin. An external pull-up to the periphery supply has to be added. During each reset cycle the following states are controlled by the AS3709:

Pin XRES is forced to GND
Normal startup with progra mmable power-on sequence and regulator voltages
Reset is active until the programmable reset timer (set by register bits res_timer<2:0> ) expires
All registers are set to their default values after power-on, except the reset control- and status-registers RESET Reasons Reset can be activated from 7 different sources:
V POR has been reached (V SUP reached POR level)
ResVoltFall was reached (V SUP drops below ResVoltFall)
Software forced reset
Power off mode
External triggered through the pin XRES
Over-temperature
O N - k e y l o n g p r e s s Voltage Detection There are two types of voltage dependent resets: V POR and VXRES . VPOR monitors the voltage on V2_5 and V XRES monitors the voltage on V SUP. The linear regulator for V2_5 is always on and uses the voltage V SUP as its source. The pin XRES is only released if V2_5 is above V POR and V SUP is above ResVoltRise. Power OFF To put the chip into ultralow power mode, write ‘1’ into power_off . The chip stays in power off mode until
The external pin ON is pulled high
T h e VPOR level is touched to start a complete reset cycle The bit power_off is automatically cleared by this reset cycle. During power_off state all circuits are shut-off except the Low Power LDO (V2_5). Thus the current consumption of AS3709 is reduced to less than 7μA. The digital part is supplied by V2_5, all other circuits are turned off in this mode, including references and oscillator. Except the reset control registers, all other registers are set to their default value after power-on.

AS3709 – 28 ams Datasheet, Confidential: 2013-Aug [1-02] Detailed Description - System Functions Note(s) and/or Footnote(s): 1. The selection of the range and level is done via OTP . It’s recommended to set the ResVoltRise level 200mV above the ResVoltF all level to have a hysteresis. 2. 2.7V is the default value, other levels can be set via SW. 3. XRES signal is debounced wi th the specified mask time for rising- and falling slope of VSUP 4. VRES_FALL is only accepted if the reset condition is longer than VRES_MASK. This guard time is used to avoid a complete rese t of the system in case of short drops of VSUP . Figure 37: ResVoltRise/ResVoltFall Levels Note: If bit reslevel_5V is “1” , then the 5.0V mode is selected. VRES_MAS K Mask time for VXRES_fall Duration for VSUP < ResVoltFall until a reset cycle is started (3) FastResEn = 0 3 ms FastResEn = 1 4 μs Mode 000 001 010 011 100 101 110 111 Symbol Parameter Note Min Typ Max Uni t

ams Datasheet, Confidential: 2013-Aug [1-02] AS3709 – 29 Detailed Description - System Functions Stand-by Stand-by allows shutting down a part or the complete system. Stand-by can be terminated by every possible interrupt or GPIO of the PMU. The interrupt has to be enabled and GPIO has to be configured before going to stand-by. Figure 38: Stand-by Internal References Low Power Mode Use bit low_power_on to activate the Low Power Mode. In this mode the on-chip voltage reference and the temperature supervision comparators are operating in pulsed mode. This reduces the quiescent current of the AS3709 by 45μA (typ.). Because of the pulsed function some specifications are not fulfilled in this mode (e.g. in creased noise), but still the full functionality is available. Note(s): Low power mode can be controlled by the serial interface. State Description Enter via GPIO To enter stand-by mode the following settings have to be done:

Enable just these IRQ sources which sh ould lead to leave stand-by mode.
Make sure that IRQ is inactive (IRQ flags get cleared by register reading)
Set the GPIO to input ( gpioX_mode = 0)
Set the GPIO for stand-by control ( gpioX_iosf = 6)
S e t regX_select to define the sequence for going into stand-by for up to 3 regulators
S e t regX_voltage_stby if another voltage is needing during stand-by
Define which regulators should be kept powered during stand-by (sdX_stby_on and ldoX_stby_on)
Activate the selected GPIO Enter via SW To enter stand-by mode the following settings have to be done:
Enable just these IRQ sources which sh ould lead to leave stand-by mode.
Make sure that IRQ is inactive (IRQ flags get cleared by register reading)
Define which regulators should be kept powered during stand-by (sdX_stby_on and ldoX_stby_on)
Set the delay for going into stand-by after the SW command (off_delay)
S e t standby_mode_on to 1 Stand-by V2_5 chip supply is kept ON All other regulators are switched OFF dependent on the bits sdX_stby_on and ldoX_stby_on XRES goes active (can be disabled with standby_reset_disable) and pwr_good goes inactive Leave The chip will come out of stand-by with
IRQ activation or
GPIO control (if entered via GPIO) Start-Up sequence is provided defined by the boot ROM.

ams Datasheet, Confidential: 2013-Aug [1-02] AS3709 – 31 Detailed Description - System Functions Figure 41: GPIO Pin Characteristics GPIO Pins: Shows the key electrical parameter of the GPIO pins. VSUP=2.7 to 5.5V; unless otherwise mentioned. IO Functions Normal IO Operation: If set to input, the logic level of the signal present at the GPIOx pin can be read from gpioX_in . If the output mode is chosen, gpioX_out specifies the logic level of the GPIOx pin. This mode is also used for the on/off control of the DCDC and LDOs. The selection which regu lator is controlled by which GPIO, is done with the gpio_ctrl_sdX or gpio_ctrl_ldoX bits. The gpioX_mode should be set to input. Interrupt Output GPIOx pin logic state is derived from the interrupt signal XINT. Whenever an interrupt is present the GPIOx pin will be pulled high. The gpioX_mode should be set to output. VSUP_low Output GPIOx pin will go high if V SUP falls below ResVoltFall and SupResEn = 0. The gpioX_mode should be set to output. GPIO Interrupt Input A falling or rising edge will set the gpio_int bit. The gpioX_mode should be set to input. Symbol Parameter Note Min Typ Max Unit VGPIO_max Max. voltage on GPIO1/2 pins Pin VSUP is used as supply for the GPIO pins VSUP + 0.3 V VOL Low level output voltage IOL=+1mA digital output +0.4 V VOH High level output voltage IOH=–1mA; digital push-pull output 0.8*VSUP V VIL Low level input voltage Digital input 0.4 V VIH High level input voltage Digital input 1.4 V ILEAKAGE Leakage current High impedance 10 μA Rpull-up Pull-up resistance if enabled; VSUP = 3.6V 300 kΩ Rpull-down Pull-down resistance if enabled; VSUP = 3.6V 300 kΩ

AS3709 – 32 ams Datasheet, Confidential: 2013-Aug [1-02] Detailed Description - System Functions Vselect Input As long as the GPIOx pin is high the DCDC/LDOs operate with the normal register settings. If the GPIOx pin goes low the settings will change to the ones stored in regX_voltage . The gpioX_mode should be set to input. Figure 42: GPIO Vselect Modes IO Functions: Shows the 4 different Vselect modes, depending on the setting of gpioX_iosf Stand-by and Vselect Input This mode is very similar to th e Vselect mode described in the previous paragraph. In addition to switch between 2 register settings of 2 regulators the chip is set into stand-by mode when the GPIOx pin goes low and wakes up again when the pin is pulled high. The gpioX_mode should be set to input. GPIO1 and GPIO2 may be used to control two regulators separately. Figure 43: Stand-by and Vselect Modes IO Functions: Shows the 4 different Vselect and Stand-by control modes, depending on the setting of gpioX_iosf gpio1_iosf gpio2_iosf Vselect mode <> 5 <> 5 No voltage select by GPIO for regulator <> 5 5 GPIO2 controls regulator selected by reg1_select and reg2_select 5 <> 5 GPIO1 controls regulator selected by reg1_select and reg2_select

55 GPIO1 controls regulator selected by reg1_select

GPIO2 controls regulator selected by reg2_select gpio1_iosf gpio2_iosf Vselect Mode Stand-by Control <> 6 <> 6 no voltage select by GPIO for regulator No <> 6 6 GPIO2 controls regulator selected by reg1_select and reg2_select Yes 6< > 6 GPIO1 controls regulator selected by reg1_select and reg2_select Yes

66 GPIO1 controls regulator selected by reg1_select

GPIO2 controls regulator selected by reg2_select Yes

ams Datasheet, Confidential: 2013-Aug [1-02] AS3709 – 33 Detailed Description - System Functions PWRGOOD Output This signal will go high at the end of the start-up sequence. This can be used as a second reset si gnal to the processor to e.g. start oscillators. The gpioX_mode should be set to output. Supervisor All Step-Down DCDCs have an integrated over-current protection. An over-temperature protection of the chip is also integrated which can be switched on with the serial interface signal temp_pmc_on (enabled by default; it is not recommended to disable the over-temperature protection). Temperature Supervision The chip has two signals for the serial interface: ov_temp_110 and ov_temp_140 . The flag ov_temp_110 is automatically reset if the overtemperature condition is removed, whereas ov_temp_140 has to be reset by the serial interface with the signal rst_ov_temp_140 . If the flag ov_temp_140 is set, an automatic reset of the complete chip is initiated. The chip will only start-up when the temperature falls below the T110 level (including hysteresis). The flag ov_temp_140 is not affected by this reset cycle allowing the software to detect the reason for this unexpected shutdown. Figure 44: Over-Temperature Protection Symbol Parameter Min Typ Max Unit T110 ov_temp_110 rising threshold 95 110 125 °C T140 ov_temp_140 rising threshold 125 140 155 °C THYST ov_temp_110 and ov_temp_140 hysteresis 5 °C

AS3709 – 34 ams Datasheet, Confidential: 2013-Aug [1-02] Detailed Description - System Functions Interrupt Generation The interrupt controller generates an interrupt request for the host controller as soon as one or more of the bits in the Interrupt 1…2 register are set by pulling low pin XINT (XINT has to be selected as a GPIO output func tion). All the interrupt sources can be enabled in the Interrupt Mask 1…2 register. The Interrupt 1…2 registers are cleared automatically after the host controller has read them. To prevent the AS3709 device from losing an interrupt event, the register that is read is captured before it is transmitted to th e host controller via the serial interface. As soon as the transm ission of the captured value is complete a logical AND operation with the bit wise inverted captured value is applied to the register to clear all interrupt bits that have already been transmitted. Clearing the read interrupt bits takes 2 clock cyc les, a read access to the same register before the clearing process has completed will yield a value of ‘0’ . Note that an interr upt that has been present at the previous read access will be cleared as well in case it occurs again before the clearing process has completed. During a read access to one of the interrupt registers, the GPIO pin (GPIO output function) will be released. As soon as the transferred bits of the interrupt register have been cleared the GPIO pin (GPIO output function) will be pulled low in case a new interrupt has occurred in th e meantime. By doing so, the interrupt controller will work correctly with host controllers that are edge- and level-sensitive on their interrupt request input. Multiple byte read access is recommended to avoid reading the Interrupt 1 register over and over again in response to a new interrupt that has occurred in the same register (and thus pulling low the GPIO pin) before the Interrupt 2 register has been read. 2-Wire-Serial Control Interface Feature List

Fast-mode capability (max. SCL-frequency is 400 kHz)
7+1-bit addressing mode
60h x 8-bit data register s (word address 0x00 - 0x60)
Write formats: Single- Byte-Write, Page-Write
Read formats: Current-Addr ess-Read, Random-Read, Sequential-Read
SDA input delay and SCL spike filtering by integrated RC-components

ams Datasheet, Confidential: 2013-Aug [1-02] AS3709 – 35 Detailed Description - System Functions I²C Protocol Figure 45: 2-Wire Serial Symbol Definition Symbol Definition RW Note S Start condition after Stop R 1 bit Sr Repeated Start R 1 bit DW Device address for Write R 1000 0010b (80h) DR Device address for Read R 1000 0011b (81h) WA Word address R 8 bit A Acknowledge W 1 bit N No Acknowledge R 1 bit reg_data Register data/write R 8 bit data (n) Register data/read W 8 bit P Stop condition R 1 bit WA++ Increment word address internally R During acknowledge AS3709 (= slave) receive data AS3709 (= slave) transmits data

ams Datasheet, Confidential: 2013-Aug [1-02] AS3709 – 39 Register Description Figure 52: Register Overview 00h SD1Voltage sd1_frequ sd1_vsel <6:0> 01h SD2Voltage sd2_frequ sd2_vsel <6:0> 02h SD3Voltage sd3_frequ sd3_vsel <6:0> 03h SD4Voltage sd4_frequ sd4_vsel <6:0> 04h SD5Voltage sd5_frequ sd5_vsel <6:0> 05h LDO1Voltage ldo1_ilimit ldo1_vsel <6:0> 06h LDO2Voltage ldo2_ilimit ldo2_vsel <6:0> 0ch GPIO1control gpio1_invert gpio1_iosf <6:3> gpio1_mode <2:0> 0dh GPIO2control gpio2_invert gpio2_iosf <6:3> gpio2_mode <2:0> 10h SDcontrol - ldo2_enable ldo1_enabl e sd5_enable sd4_enable sd3_enable sd2_enable sd1_enable 20h GPIOsignal_out -- - gpio2_out gpio1_out 21h GPIOsignal_in -- - gpio2_in gpio1_in 22h Reg1_Voltage reg1_voltage <7:0> 23h Reg2_Voltage reg2_voltage <7:0> 24h Reg_control reg2_select <7:4> reg1_select <3:0> 25h GPIOctrl_sd gpio_ctrl_sd4 <7:6> gpio_ctrl_sd3 <5:4> gpio_ctrl_sd2 <3:2> gpio_ctrl_sd1 <1:0> Register Description

AS3709 – 40 ams Datasheet, Confidential: 2013-Aug [1-02] Register Description 26h GPIOctrl_ldo - - gpio_ctrl_ldo2 <5:4> gpio_ctrl_ldo1 <3:2> gpio_ctrl_sd5 <1:0> 29h SD_control3 sd5_slave sd4_slave sd2_slave sd5_fsel sd5_fast sd5_low_nois e - 30h SD_control1 sd4_low_nois e sd3_low_nois e sd2_low_no ise sd1_low_noi se sd4_fast sd3_fast sd2_fast sd1_fast 31h SD_control2 sd_dvm_select <7:6> dvm_time <5:4> sd4_fsel sd3_fsel sd2_fsel sd1_fsel 32h Supply_voltage_ monitor FastResEn SupResEn ResVoltFall <5:3> ResVoltRise <2:0> 33h Startup_control - reslevel_5v power_off_ at_vsuplow 34h ResetTimer - stby_reset_dis able auto_off off_delay <4:3> res_timer <2:0> 35h ReferenceContro l on_reset_del ay - clk_div2 standby_mo de_on clk_int <3:1> low_power_ on 36h ResetControl onkey_reset reset_reason <6:3> on_input power_off force_reset 37h Overtemperatur eControl tco_140_a tco_110_a temp_test<5:4> rst_ov_temp_ 140 ov_temp_140 ov_temp_1 temp_pmc_ on 39h Reg_standby_m od1 disable_regp d ldo2_stby_on ldo1_stby_ on sd5_stby_on sd4_stby_on sd3_stby_on sd2_stby_o n sd1_stby_on 73h RegStatus - sd5_lv sd4_lv sd3_lv sd2_lv sd1_lv 74h InterruptMask1 LowVsup_int_ m ovtmp_int_m onkey_int_ m sd5_lv_int_ m sd1_lv_int_ m 75h InterruptMask2 - gpio_restar t_int_m gpio_int_m

ams Datasheet, Confidential: 2013-Aug [1-02] AS3709 – 41 Register Description 77h InterruptStatus1 LowBat_int_i ovtmp_int_i onkey_int_i sd5_lv_int_i sd4_lv_int_i sd3_lv_int_i sd2_lv_int_i sd1_lv_int_i 78h InterruptStatus2 - gpio_restar t_int_i gpio_int_i 90h ASIC_ID1 asic_id1<7:0> 91h ASIC_ID2 fab_id<7:4> revision <3:0>

ams Datasheet, Confidential: 2013-Aug [1-02] AS3709 – 45 Register Description Figure 60: GPIO1control Register (Address 0ch) Addr: 0ch GPIO1control Bit Bit Name Default Access Bit Description 7g p i o 1 _ i n v e r t 0 R W Invert GPIO1 input/output 0 : Normal mode 1 : Invert input or output 6:3 gpio1_iosf 'b0000 RW Select the GPIO1 special function .0 : Normal I/O operation .1 : Interrupt output .2 : VSUP_low output .3 : GPIO interrupt input .4 : NA .5 : Vselect input, (apply on reg1_select and reg2_select, if gpio2_iosf =5 then apply on reg1_select only) .6 : standby + Vselect + restart interrupt input .7 : pwr_good output .8 : NA .9 : NA 10 : NA 11 : NA 12 : NA 13 : NA 14 : NA 15 : NA 2:0 gpio1_mode 'b011 RW Selects the GPIO1 mode (I, I/O, Tri, Pulls) 0 : Input 1 : Output (push and pull) 2 : IO (open drain, only NMOS is active) 3 : NA 4 : Input with pullup 5 : Input with pulldown 6 : IO (open drain (NMOS) with pullup) 7 : NA

AS3709 – 46 ams Datasheet, Confidential: 2013-Aug [1-02] Register Description Figure 61: GPIO2control Register (Address 0dh) Addr: 0dh GPIO2control Bit Bit Name Default Access Bit Description 7g p i o 2 _ i n v e r t 0 R W Invert GPIO2 input/output 0 : Normal mode 1 : Invert input or output 6:3 gpio2_iosf 'b0000 RW Select the GPIO2 special function .0 : Normal i/o operation .1 : Interrupt output .2 : VSUP_low output .3 : GPIO interrupt input .4 : NA .5 : Vselect input, (apply on reg1_select and reg2_select, if gpio1_iosf=5 then apply on reg2_select only) .6 : standby + Vselect + restart interrupt input .7 : pwr_good output .8 : NA .9 : NA 10 : NA 11 : NA 12 : NA 13 : NA 14 : NA 15 : NA 2:0 gpio2_mode 'b011 RW Selects the GPIO2 mode (I, I/O, Tri, Pulls) 0 : Input 1 : Output (push and pull) 2 : IO (open drain, only NMOS is active) 3 : NA 4 : Input with pullup 5 : Input with pulldown 6 : IO (open drain (NMOS) with pullup) 7 : NA

AS3709 – 50 ams Datasheet, Confidential: 2013-Aug [1-02] Register Description Figure 69: GPIOctrl_ldo Register (Address 26h) Addr: 26h GPIOctrl_ldo Bit Bit Name Default Access Bit Description 7:6 - 'b00 N/A - 5:4 gpio_ctrl_ldo2 'b00 RW Enable GPIO control of LDO2. GPIO ctrl only enabled, if ldo2_vsel > 0 0 : No GPIO control 1 : Controlled by GPIO1 2 : Controlled by GPIO2 3 : NA 3:2 gpio_ctrl_ldo1 'b00 RW Enable GPIO control of LDO1. GPIO ctrl only enabled, if ldo1_vsel > 0 0 : No GPIO control 1 : Controlled by GPIO1 2 : Controlled by GPIO2 3 : NA 1:0 gpio_ctrl_sd5 'b00 RW Enable GPIO control of SD5. GPIO ctrl only enabled, if sd5_vsel > 0 0 : No GPIO control 1 : Controlled by GPIO1 2 : Controlled by GPIO2 3 : NA

ams Datasheet, Confidential: 2013-Aug [1-02] AS3709 – 51 Register Description Figure 70: SD_control3 Register (Address 29h) Addr: 29h SD_control3 Bit Bit Name Default Access Bit Description 7 sd5_slave 0 RW Enables slave mode of SD5 0 : Normal mode of SD5 1 : SD5 is slave of SD3 7 sd4_slave 0 RW Enables slave mode of SD4 0 : Normal mode of SD4 1 : SD4 is slave of SD3 5 sd2_slave 0 RW Enables slave mode of SD2 0 : Normal mode of SD2 1 : SD2 is slave of SD1 4s d 5 _ f s e l 0 R W Selects between high and low frequency range 0 : 2 or 3MHz frequency (selectable by sd5_frequ) 1 : 3 or 4MHz frequency (selectable by sd5_frequ) 3s d 5 _ f a s t 0 R W Selects a faster regulation mode for SD5 suitable for larger load changes. 0 : Normal mode, Cext=10μF 1 : Fast mode, Cext=22μF required 2 sd5_low_noise 0 RW Enables low noise mode of SD5. If enabled smaller current pulses and output ripple is activated. 0 : Normal mode. Minimum current pulses of >100mA applied in skip mode. 1 : Low noise mode. Only minimum on time applied in skip mode. 1:0 - 'b00 N/A -

AS3709 – 52 ams Datasheet, Confidential: 2013-Aug [1-02] Register Description Figure 71: SD_control1 Register (Address 30h) Addr: 30h SD_control1 Bit Bit Name Default Access Bit Description 7 sd4_low_noise 0 RW Enables low noise mode of SD4. If enabled smaller current pulses and output ripple is activated. 0 : Normal mode. Minimum current pulses of >100mA applied in skip mode. 1 : Low noise mode. Only minimum on time applied in skip mode. 6 sd3_low_noise 0 RW Enables low noise mode of SD3. If enabled smaller current pulses and output ripple is activated. 0 : Normal mode. Minimum current pulses of >100mA applied in skip mode. 1 : Low noise mode. Only minimum on time applied in skip mode. 5 sd2_low_noise 0 RW Enables low noise mode of SD2. If enabled smaller current pulses and output ripple is activated. 0 : Normal mode. Minimum current pulses of >100mA applied in skip mode. 1 : Low noise mode. Only minimum on time applied in skip mode. 4 sd1_low_noise 0 RW Enables low noise mode of SD1. If enabled smaller current pulses and output ripple is activated. 0 : Normal mode. Minimum current pulses of >100mA applied in skip mode. 1 : Low noise mode. Only minimum on time applied in skip mode. 3s d 4 _ f a s t 0 R W Selects a faster regulation mode for SD4 suitable for larger load changes. 0 : Normal mode, Cext=10μF 1 : Fast mode, Cext=22μF required 2s d 3 _ f a s t 0 R W Selects a faster regulation mode for SD3 suitable for larger load changes. 0 : normal mode, Cext=10μF 1 : fast mode, Cext=22μF required 1s d 2 _ f a s t 0 R W Selects a faster regulation mode for SD2 suitable for larger load changes. 0 : Normal mode, Cext=10μF 1 : Fast mode, Cext=22μF required 0s d 1 _ f a s t 0 R W Selects a faster regulation mode for SD1 suitable for larger load changes. 0 : Normal mode, Cext=10μF 1 : Fast mode, Cext=22μF required

ams Datasheet, Confidential: 2013-Aug [1-02] AS3709 – 53 Register Description Figure 72: SD_control2 Register (Address 31h) Addr: 31h SD_control2 Bit Bit Name Default Access Bit Description 7:6 sd_dvm_select 'b00 RW Apply DVM counter to the following DCDC converter 0 : Select SD1 for DVM 1 : Select SD2 for DVM 2 : Select SD3 for DVM 3 : Select SD5 for DVM 5:4 dvm_time 'b00 RW Time steps of DVM voltage change of selected step down, if voltage of step Down is changed during operation (sdx_vsel) voltage is decreased/increased by single steps 12.5mV 0 : 0 μsec, immediate change (no DVM) 1 : 4 μsec time delay between steps 2 : 8 μsec time delay between steps 3 : 16 μsec time delay between steps 3s d 4 _ f s e l 0 R W Selects between high and low frequency range 0 : 2 or 3MHz frequency (selectable by sd4_frequ) 1 : 3 or 4MHz frequency (selectable by sd4_frequ) 2s d 3 _ f s e l 0 R W Selects between high and low frequency range 0 : 2 or 3MHz frequency (selectable by sd3_frequ) 1 : 3 or 4MHz frequency (selectable by sd3_frequ) 1s d 2 _ f s e l 0 R W Selects between high and low frequency range 0 : 2 or 3MHz frequency (selectable by sd2_frequ) 1 : 3 or 4MHz frequency (selectable by sd2_frequ) 0s d 1 _ f s e l 0 R W Selects between high and low frequency range 0 : 2 or 3MHz frequency (selectable by sd1_frequ) 1 : 3 or 4MHz frequency (selectable by sd1_frequ)

AS3709 – 54 ams Datasheet, Confidential: 2013-Aug [1-02] Register Description Figure 73: Supply_voltage_monitor Register (Address 32h) Addr: 32h Supply_voltage_monitor Bit Bit Name Default Access Bit Description 7F a s t R e s E n 0 R W 0 : ResVoltFall debounce time = 3msec 1 : ResVoltFall debounce time = 4μsec (tbd) 6S u p R e s E n 0 R W 0 : A reset is generated if VSUP falls below 2.7V 1 : A reset is generated if VSUP falls below ResVoltFall If VSUP falls below ResVoltFall only an interrupt is generated (if enabled) and the μProcessor can shut down the system 5:3 ResVoltFall 'b000 RW This value determines the reset level ResVoltFall for falling VSUP. It is recommended to set this value at least 200mV lower than ResVoltRise (the levels differ between 3.3V and 5V supply) 0 : 2.7V / 3.6V 1 : 2.8V / 3.7V 2 : 2.9V / 3.8V 3 : 3.0V / 3.9V 4 : 3.1V / 4.0V 5 : 3.2V / 4.1V 6 : 3.3V / 4.2V 7 : 3.4V / 4.4V 2:0 ResVoltRise 'b000 RO (OTP) This value determines the reset level ResVoltRise for rising V SUP. It is recommended to set this value at least 200mV higher than ResVoltFall (the levels differ between 3.3V and 5V supply) 0 : 2.7V / 3.6V 1 : 2.8V / 3.7V 2 : 2.9V / 3.8V 3 : 3.0V / 3.9V 4 : 3.1V / 4.0V 5 : 3.2V / 4.1V 6 : 3.3V / 4.2V 7 : 3.4V / 4.4V

ams Datasheet, Confidential: 2013-Aug [1-02] AS3709 – 55 Register Description Figure 74: Startup_Control Register (Address 33h) Addr: 33h Startup_Control Bit Bit Name Default Access Bit Description 7:2 - ‘b000

0000 N/A Do not use

1 reslevel_5v 0 RW Selects the 5V supply reset level (see ResVoltRise and ResVoltFall) 0 : 3.3V level 1 : 5.0V level 0 power_off_ at_vsuplow 0R W Switch on Power off mode if low V SUP is detected during active or standby mode (Pin ON= low and bit auto_off=0) 0 : If low V SUP is detected, VSUP is continuously monitored and chip startup initiated if VSUP is above ResVoltRise 1 : If low VSUP is detected, enter power off mode

AS3709 – 56 ams Datasheet, Confidential: 2013-Aug [1-02] Register Description Figure 75: ResetTimer Register (Address 34h) Addr: 34h ResetTimer Bit Bit Name Default Access Bit Description 7- ' b 0 N / A D o n o t u s e 6 stby_reset_disa ble 0R W Disable Reset output signal (pin XRES) in standby mode. 0 : Normal mode, reset is active in standby mode 1 : No reset in standby mode and during exit of stand-by mode 5a u t o _ o f f 0 R O Defines startup behavior at first V SUP connection 0 : Startup of chip if VSUP>ResVoltRise 1 : Enter power off mode (Startup with ON key) 4:3 off_delay 'b01 RW Set delay between I²C command, GPIO or Reset signal for power_off, standby mode or reset and execution of that command. 0 : No delay 1 : 8 msec 2 : 16 msec 3 : 32 msec 2:0 res_timer 'b000 RW Set Reset Time, after the last regulator has started 0 : RESTIME = 2ms 1 : RESTIME = 4ms 2 : RESTIME = 8ms 3 : RESTIME = 16ms 4 : RESTIME = 32ms 5 : RESTIME = 64ms 6 : RESTIME = 128ms 7 : RESTIME = 160ms

ams Datasheet, Confidential: 2013-Aug [1-02] AS3709 – 57 Register Description Figure 76: ReferenceControl Register (Address 35h) Addr: 35h ReferenceControl Bit Bit Name Default Access Bit Description 7o n _ r e s e t _ d e l a y 0 R W Sets the on reset delay time 0 : 8 sec (if onkey_reset=1) 1 : 4 sec (if onkey_reset=1) 6- 0 R W - 5 clk_div2 0 RW Divide internal clock oscillator by 2 to reduce quiescent current for low power operation 0 : Normal mode 1 : Internal clock frequency divided by two. All timings are increased by two. Switching frequency of all DCDC converters are divided by two. Reduced transient performance of DCDC converters. 4 standby_mode _on 0R W Setting to 1 sets the PMU into standby mode. All regulators are disabled except those regulators enabled by register Reg standby mode. XRES will be pulled to low. A normal startup of all regulators will be done with any interrupt (has to be enabled before entering standby mode). During this startup, regulators defined by Reg standby mode register are continuously on. 3:1 clk_int 'b000 RW Sets the internal CLK frequency f CLK used for fuel gauge, DCDCs, PWM, ... 0 : 4 MHz (default) 1 : 3.8 MHz 2 : 3.6 MHz 3 : 3.4 MHz 4 : 3.2 MHz 5 : 3.0 MHz 6 : 2.8 MHz 7 : 2.6 MHz All frequencies, timings and delays in this datasheet are based on 4MHz clk_int 0 low_power_on 0 RW Enable low power mode of internal reference. 0 : Standard mode 1 : Low power mode - all specification except noise parameters are still valid. Iq reduced by approx. 30μA

AS3709 – 58 ams Datasheet, Confidential: 2013-Aug [1-02] Register Description Figure 77: ResetControl Register (Address 36h) Addr: 36h ResetControl Bit Bit Name Default Access Bit Description 7 onkey_reset 0 RW 0 : Reset after 4/8 seconds ON pressed disabled 1 : Reset after 4/8 seconds ON pressed enabled 6:3 reset_reason 'b0000 RW Flags to indicate to the software the reason for the last reset .0 : VPOR has been reached (VSUP connection from scratch) .1 : ResVoltFall was reached (VSUP drop below 2.75V) .2 : Software forced by force_reset .3 : Software forced by power_off and ON was pulled high .4 : Software forced by power_off and charger was detected .5 : External triggered through the pin XRES .6 : Reset caused by overtemperature T140 .7 : NA .8 : Reset caused by 4/8 seconds ON press .9 : NA 10 : NA 11 : Reset caused by interrupt in standby mode 12 : Reset caused by ON pulled high in standby mode 2 on_input 0 R_PUSH Read: This flag represents the state of the ON pad directly Write: Setting to 1 resets the 4/8 sec. onkey_reset timer 1 power_off 0 RW Setting to 1 starts a reset cycle, but waits after the Reg_off state for a falling edge on the pin ON 0 force_reset 0 RW Setting to 1 starts a complete reset cycle

AS3709 – 60 ams Datasheet, Confidential: 2013-Aug [1-02] Register Description Figure 80: RegStatus Register (Address 73h) Figure 81: InterruptMask1 Register (Address 74h) Addr: 73h RegStatus Bit Bit Name Default Access Bit Description 7:5 - ‘b000 N/A Do not use 4s d 5 _ l v 0 R O Bit is set when voltage of SD5 drops below low voltage threshold (-5%) (1msec debounce time default) 3s d 4 _ l v 0 R O Bit is set when voltage of SD4 drops below low voltage threshold (-5%) (1msec debounce time default) 2s d 3 _ l v 0 R O Bit is set when voltage of SD3 drops below low voltage threshold (-5%) (1msec debounce time default) 1s d 2 _ l v 0 R O Bit is set when voltage of SD2 drops below low voltage threshold (-5%) (1msec debounce time default) 0s d 1 _ l v 0 R O Bit is set when voltage of SD1 drops below low voltage threshold (-5%) (1msec debounce time default) Addr: 74h InterruptMask1 Bit Bit Name Default Access Bit Description

7 LowVsup_int_m 1 RW Set to 0 to enable the interrupt

6 ovtmp_int_m 1 RW Set to 0 to enable the interrupt 5 onkey_int_m 1 RW Set to 0 to enable the interrupt 4 sd5_lv_int_m 1 RW Set to 0 to enable the interrupt 3 sd4_lv_int_m 1 RW Set to 0 to enable the interrupt 2 sd3_lv_int_m 1 RW Set to 0 to enable the interrupt 1 sd2_lv_int_m 1 RW Set to 0 to enable the interrupt 0 sd1_lv_int_m 1 RW Set to 0 to enable the interrupt

ams Datasheet, Confidential: 2013-Aug [1-02] AS3709 – 61 Register Description Figure 82: InterruptMask2 Register (Address 75h) Figure 83: InterruptStatus1 Register (Address 77h) Figure 84: InterruptStatus2 Register (Address 78h) Addr: 75h InterruptMask2 Bit Bit Name Default Access Bit Description 7:2 - ‘b0000 00 N/A Do not use 1 gpio_restart_int_m 1 RW Set to 0 to enable the interrupt 0 gpio_int_m 1 RW Set to 0 to enable the interrupt Addr: 77h InterruptStatus1 Bit Bit Name Default Access Bit Description

7 LowBat_int_i 0 POP Bit is set when VSUP drops below vres_fall rising edge

6 ovtmp_int_i 0 POP Bit is set when 110deg is exceeded rising edge only 5 onkey_int_i 0 POP Rising and falling edge 4 sd5_lv_int_i 0 POP Rising edge only 3 sd4_lv_int_i 0 POP Rising edge only 2 sd3_lv_int_i 0 POP Rising edge only 1 sd2_lv_int_i 0 POP Rising edge only 0 sd1_lv_int_i 0 POP Rising edge only Addr: 78h InterruptStatus2 Bit Bit Name Default Access Bit Description 7:2 - ‘b0000 00 N/A Do not use 1 gpio_restart_int_i 0 POP Falling edge 0 gpio_int_i 0 POP Rising and falling edge

ams Datasheet, Confidential: 2013-Aug [1-02] AS3709 – 63

Application Information

Figure 87: Application Schematic LDO113 VIN_LDO114 FB_SD2 15 GNDSENSE30 FB_SD531PVSS_SD532VIN_LDO211 FB_SD3 10 LDO212 VSUP_SD3 7 FB_SD46 LX_SD3 8 PVSS_SD45 VSUP_SD52 VSUP_SD43LX_SD44 SCLK24 SDA25 VSUP_SD1 22 LX_SD1 21 GPIO228 XRES27 ON26 VSUP_SD2 18 FB_SD1 19 LX_SD2 17 PVSS_SD2 16 LDOs DCDC SD 1-5 Logic & Control AS3709 uPMIC EP_VSS33 GPIO129 LX_SD51 PVSS_SD3 9 PVSS_SD1 20 V2_523 AS3709 2.2μF 2.2μF 2.2μF 2.2μF 2.2μF 2.2μF 2.2μF 2.2μF2.2μF 10μF 10μF 10μF 10μF10μF GND GND GND GND VSUP VSUP 1μH 1μH 1μH 1μH1μH GND GND VSUP GND GND GND GND VSUP VSUP Vsup Vsup GND GND GND GND GND 1μF GND SCLK SDA XRES GPIO1 GPIO2 8k2 8k2 VSUP401-1426-1-ND KMR211GLFS 401-1426-1-ND KMR211GLFS 10k GND V2_5 V2_5 VSUP GND ON SD1 SD2 SD3 SD4 SD5 LDO1 LDO2

AS3709 – 64 ams Datasheet, Confidential: 2013-Aug [1-02] Figure 88: Layout Guidelines 1/2 Layout Guidelines 1/2: This figure shows the recommended layout and placement of the external components for the 5 x 1A application circuit. Red lines and areas are connections on TOP layer. Grey lines and areas are GND and PVSS connections on TOP layer. Light blue lines and areas are connections on an inner layer or BOTTOM layer. Black round dots are vias. VSUP areas should be connected to an inner VSUP plane via vias. GND and PVSS areas should be connected to an inner GND plane via vias. A AS3709 QFN 32-pin 4x4mm Exposed Pad: GND 29 12 V2_5 SCLK VSSA GPIO1 GPIO2 XRES ON SDA VSUP _SD5 VS UP_SD4 LX_SD4 PVSS_SD4 VSUP_SD3 LX_SD3 PVSS _SD3 FB_SD3 VIN_LDO2 LDO2 LDO1 VIN_LDO1 FB_SD2 LX_SD2 VSUP_SD2 FB_SD1 PVSS_SD1 FB_SD5 PVSS_SD5 FB_SD3FB_SD4 FB_SD2 FB_SD1 COUT_SD5 COUT_SD4 COUT_SD3 COUT_SD1 COUT_SD2 CIN_SD5 CIN_SD4 CIN_SD3 CIN_SD1 CIN_SD2 CIN_LDO2 COUT_LDO2 COUT_LDO1 CIN_LDO1 LX_SD5 LX_SD1 LX_SD2 PVSS_ SD2 SD5 SD4 SD3 SD2 SD1 FB_SD4 FB_SD2

ams Datasheet, Confidential: 2013-Aug [1-02] AS3709 – 65 PCB with minimum 4 layers is recommended. Figure 89: Layout Guidelines 2/2 Layout Guidelines 2/2: Layout Guidelines 2/2: This figure shows the recommended layout and placement of the external components for the 1 x 2A & 1 x 3A application circuit. Red lines and areas are connections on TOP layer. Grey lines and areas are GND and PVSS connections on TOP layer. Light blue lines and areas are connections on an inner layer or BOTTOM layer. Black round dots are vias. VSUP areas should be connected to an inner VSUP plane via vias. GND and PVSS areas should be connected to an inner GND plane via vias. A PCB with minimum 4 layers is recommended. AS3709 QFN 32-pin 4x4mm Exposed Pad: GND 29 12 V2_5 SCLK VSSA GPIO1 GPIO2 XRES ON SDA LX_SD5 LX_SD4 VSUP_SD3 LX_SD3 PVSS_SD VIN_LDO2 LDO2 LDO1 VIN_LDO1 PVS S_SD2 VSUP_SD2 FB_SD1 PVSS_SD1 LX_SD1 PVSS_SD5 FB_SD3 LX_SD2 PVSS_SD4 SD3 & SD4 & SD5 SD1 & SD1 VSUP SD4+SD5 CIN_SD1 COUT_SD1/2 COUT_SD1/2 CIN_SD2 CIN_LDO2 COUT_LDO2 COUT_LDO1 CIN_LDO1 COUT_SD3/4/5 COUT_SD3/4/5 COUT_SD3/4/5 CIN_SD5 CIN_SD4 CIN_SD3 VSUP_SD1 LX_SD1 FB_SD1 FB_SD3

AS3709 – 66 ams Datasheet, Confidential: 2013-Aug [1-02] Package Drawings & Markings Figure 90: QFN32 4x4 0.4mm Pitch Package Drawing Note(s) and/or Footnote(s): 1. Dimensioning and tolerancing conform to ASME Y14.5M-1994. 2. All dimensions are in millimeters. Angles are in degrees. 3. Dimension b applies to metallized term inal and is measured between 0.25mm and 0.30mm from terminal tip. Dimension L1 represents terminal full back from package edge up to 0.15mm is acceptable. 4. Coplanarity applies to the exposed heat slug as well as the terminal. 5. Radius on terminal is optional. 6. N is the total number of terminals. Package Drawings & Markings REF. MIN NOM MAX A 0.80 0.90 1.00 A1 0 0.02 0.05 A3 0.20 REF L 0.35 0.40 0.45 L1 0 - 0.15 b 0.15 0.20 0.25 D4 . 0 0 B S C E4 . 0 0 B S C e0 . 4 0 B S C D2 2.60 2.70 2.80 E2 2.60 2.70 2.80 aaa - 0.10 - bbb - 0.07 - ccc - 0.10 - ddd - 0.05 - eee - 0.08 - fff - 0.10 - N3 2

ams Datasheet, Confidential: 2013-Aug [1-02] AS3709 – 67 Package Drawings & Markings Figure 91: WLP36 0.4mm Pitch Package Drawing Note(s) and/or Footnote(s): 1. Pin 1 = A1 2. ccc Coplanarity 3. A1 dimensions are in μm

AS3709 – 70 ams Datasheet, Confidential: 2013-Aug [1-02] RoHS Compliant & ams Green Statement RoHS: The term RoHS compliant means that ams products fully comply with current RoHS directive. Our semiconductor products do not contain any chemicals for all 6 substance categories, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, RoHS compliant products are suitable for use in specif ied lead-free processes. ams Green (RoHS compliant and no Sb/Br): ams Green defines that additionally to RoHS compliance, our products are free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material). Important Information: The information provided in this statement represents ams knowledge and belief as of the date that it is provided. ams bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are unde rway to better integrate information from third parties. ams has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ams and ams suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. RoHS Compliant & ams Green Statement

ams Datasheet, Confidential: 2013-Aug [1-02] AS3709 – 71 Ordering & Contact Information Figure 98:

Ordering Information

Note: On request. Buy our products or get free samples online at: www.ams.com/ICdirect Technical Support is available at: www.ams.com/Technical-Support For further information and requests, e-mail us at: ams_sales@ams.com For sales offices, distributors and representatives, please visit: www.ams.com/contact Headquarters ams AG Tobelbaderstrasse 30

8141 Unterpremstaetten

Austria, Europe Tel: +43 (0) 3136 500 0 Website: www.ams.com Ordering Code Marking Sequence Description Delivery Form Package AS3709- BQFR-ES K2V0-ES Sequence programmable on request μPMIC with 5 DCDC and 2 LDOs Tray 32-pin QFN 4x4 AS3709- BQFM-00 K2V0-00 Default sequence μPMIC with 5 DCDC and 2 LDOs Tape & Reel 32-pin QFN 4x4 AS3709- BQFM-xx K2V0-xx Customer specified sequence μPMIC with 5 DCDC and 2 LDOs Tape & Reel 32-pin QFN 4x4 AS3709- BWLR-ES (Note:) K2V0-ES Sequence programmable on request μPMIC with 5 DCDC and 2 LDOs Tray 36-pin WL-CSP 0.4mm pitch AS3709- BWLT-xx (Note:) K2V0-xx Customer specified sequence μPMIC with 5 DCDC and 2 LDOs Tape & Reel 36-pin WL-CSP 0.4mm pitch Ordering & Contact Information

AS3709 – 72 ams Datasheet, Confidential: 2013-Aug [1-02] Copyrights & Disclaimer Copyright ams AG, Tobelbader Strasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. Devices sold by ams AG are covered by the warranty and patent indemnification provisions appear ing in its Term of Sale. ams AG makes no warranty, express, statutory, implied, or by description regarding the inform ation set forth herein. ams AG reserves the right to change specifications and prices at any time and without notice. Theref ore, prior to designing this product into a system, it is necessary to check with ams AG for current information. This product is intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications , such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by ams AG for each application. This Product is provided by ams “AS IS” and any express or implied warranties, including, but not limited to the implied warranties of merc hantability and fitness for a particular purpose are disclaimed. ams AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any th ird party shall arise or flow out of ams AG rendering of technical or other services. Copyrights & Disclaimer