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Technical content
The technical content of this austriamicrosystems datasheet is still valid. Contact information: Headquarters: ams AG Tobelbaderstrasse 30
8141 Unterpremstaetten, Austria
Tel: +43 (0) 3136 500 0 e-Mail: ams_sales@ams.com Please visit our website at www.ams.com
Power and Audio Management Unit for Portable Devices Data Sheet Confidential www.austriamicrosystems.com Revision 1v13 1 - 157
1 General Description
The AS3658 is highly integrated power and audio management unit. The AS3658 is designed to include sophisti cated audio features like high performance audio DAC and ADC. It has several analog and digital audio interface which are explained in detail in the following sections. The AS3658 is an integrated solution for p ower supply generation and monitoring, battery management including charging.
2 Key Features
System Control - Serial Control Interface - On/Off Control Module with Boot-ROM / GPIO - Reset Generation for system controller - Programmable Interrupt Controller and Watchdog - Low power off mode (9µA; 2.5V LDO on) - 88 bit unique ID or Boot fuse array - Reset with long ON-Keypress (SW-Interuptable) - Touchscreen Interface (10 bit, interrupt) Supply Voltage Generation - 2 RF Programmable Low Noise LDOs (250mA) (1 LD O can be a current controlled switch for hotplug (200mA ± 40%)) - 1 RF Programmable Low Noise LDO (400mA) - 4 Programmable Dig. Low Power LDOs(200mA) - 2 General Purpose PWM DC/DC step up converter wi th three programmable current sinks (e.g. for- white led); for current mode feedback is automati- cally slected (DCDC_CURR1,2,3) - 3 General Purpose high efficiency DC/DC step do wn converter (DCDC 1 support DVM) - 1 Low noise charge pump with 5V output voltage - 1 Ultra Low Power 2.5V LDO (always on) Current sinks - 4 programmable(8-bit) from 0.15mA to 38.25mA (±5% ) optional useable as GPIOs - 3 programmable high voltage (15V) (8-bit) from 15mA to 38.25mA (±5% ) - internal PWM generator (extended time range) (can co ntrol DCDC_CURR1,2,3) 10-bit 40µs Successive Approximation ADC - Two external Inputs (ADC_IN1, ADC_IN2) Battery Management - Full featured chemistry independent step down charger with Ga s Gauge and Current limitation - High Current (1.0A) Linear Charger with external pass transistor (no step down charger) -0 . 1 Ω Battery switch for start-up and trickle charge - Integrated USB charger up to 880mA (can be used as w all adapter charger); current accuracy 440- 500mA for USB specification, in-circuit trimmable (±1.2% trimsteps) - Autonomous Battery Temperature Sup ervision (0ºC-45ºC or 0ºC- 50ºC) for 10k and 100k NTC - Charging Timeout (1h-8h in 30min steps) - Charging in Stanby mode - Completely Autonomous (no SW) Power Management Features - Wide Battery Supply Range 3.0…5.5V - On-Chip Bandgap Tuning for High Accuracy (±1%) - Thermal and Current Protection (int. sensor) - Standby Mode exit by interrupt e.g. Onkey/RTC Audio - 94dB Audio DAC, 16-48kHz sampling rate - Two Digital Audio Inputs (2 x I2S interface) - 2.9V low Noise LDO for Audio DAC - Two Headphone Amplifier Output with GND sep aration - Two I2S Inputs and one I2S Output - I2S master mode with programmable sample rate ontrolled by internal PLL) - GND Buffer for Headphone Amplifier - Line/ Headphone outputs with GND separation - Audio ADC, 82dB SNR with 16ksps - Microphone Bias Supply and Amplifier (mono) - 5 Band Adjustable Audio Equalizer (± 12dB in 3dB gain step - SPDIF Output - Audio Mixer and Gain Stages - PCM Interface Real Time Clock (RTC) - Alarm and Time function - Repeated Wakeup (every second or minute) - 32kHz output - Backup Battery Charger and Switchover Programmable System clock - 1.6 MHz to 2.3 MHz with 100 kHz steps Package - BGA124 8x8mm, 0.5mm pitch (can be assembled without micro via board ams AG Technical content still valid
3 Applications
The AS3658 is ideal for PDA, PMP, GPS-Navigation Systems and 1 Cell Li+ or 3 Cell NiMH powered devices. Figure 1. Blockdiagram AS3658
Figure 2. Application Diagram
www.austriamicrosystems.com Revision 1v13 4 - 157 AS3658 Data Sheet Confidential - Applications Table of Contents ams AG Technical content still valid
Table 1. Revision History
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4 Pin Assignments
123456789 1 0 1 1 1 2 1 3 1 4 A NC/ VSS _CP LRC LK1 SCL K3 VI2S SDO VCP VCP VCP _OU T VDI G34 _IN VDI G1_I N LOU T_R LINE _CM HPL NC/ BV SS B SDI2 SCLK1 SDI1 SDA VSS_C P VCP_I N VDIG_ VDIG2 _IN VDIG_ LOUT_ L HP_C M HPR C Q32k SCLK2 HPR1 HPL2 D DCDC _SENS E_P1 MCLK
2 SDO3 SCL VDIG_
VDIG_ MCLK LRCLK ALVD D HP_ CM_ PWR E VSUP PLY_4 DCDC _SENS E_N1 LRCLK
3 BVSS AVDD LINR
PLY_3 DCDC _GATE SPDIF XRES ET XINT MICS VDAC LINL G LX3 DCDC _GATE DCDC _SENS E_N2 DCDC _SENS E_P2 VSSA MICN VSUP PLY_6 VSU P_S W12 H PGND PGND DCDC _FB1 FB3 VSSA MICP VBAT_ SW12 VSU P_S W12 J LX2 VSS_C H DCDC _FB2 FB2 VSSA VREF BAT_S W VBAT _SW K VSUP PLY_1 VSUP PLY_2 FB1 AGND ISENS N ISEN SP L LX1 VOFF_ B CURR 4_GPI DCDC _CUR DCDC _CUR GND_ SW RPRO GRAM CREF GND_ SENS E RBIA S M PGND VGAT E V_BAT VBA CK N PGAT VSUP PLY_5 XON CURR 1_GPI CURR 3_GPI DCDC _CUR ADC_I ADC_I N2 VRF_2 VCHA RGER V2_5 XOU T32 P NC/ VSSA CH_S ENSE_ P CH_S ENSE_ N VCUR R_GPI O VSS_C URR CURR 2_GPI VSUP_ USB V_USB VRF1_ IN VRF_1 VRF23 _IN VRF_3 XIN32 NC/ VSS A ams AG Technical content still valid
4.1 Pin Description
Table 2. Pin list CTBGA124, 8x8MM (AS3658)
8 P USB voltage supply input
V_BAT M13 P V BAT Battery supply for Reference blocks. RPROGRAM L9 A V2_5 Select register setup at startup.
LINL F14 A VDAC Line input left channel.
5 Absolute Maximum ratings
Table 3. Absolute Maximum Ratings
- The following pins are connected to ESD setup:
0.72 W TA = 84ºC
- austriamicrosystems strongly recommends to use underfill.
6 Electrical Characteristics
Table 4. Electrical Characteristics
- With register bit low_power_on = 0, All regulators switched off, no additional external loads
- After setting register bit xon_enable=1 and power_off=1; only V2_5 is active in Power Off mode
- During startup from the AC/DC adapter, the battery voltage can be below 3.0V
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7 Typical Operating Characteristics
see individual block description ams AG Technical content still valid
8 Detailed Description-Power Management Functions
dropout regulators (LDOs) and 5V charge pump.
8.1 Step Up DC/DC Converters
Figure 3. DC/DC step-up Converter 1
Figure 4. DC/DC step-up Converter 2 Table 5. DC/DC Converter parameters
2 MHz internal CLK frequency/2
low noise on supply and output voltage.
8.1.1 Feedback selection
For step up DCDC 1, the feedback is always DCDC_FB1. feedback path can be supported.
Figure 5. DC/DC step up 2 converter with regulation of LED string on pin DCDC_CURR1,2 or 3
Figure 6. DC/DC step up 1 converter with regulated output voltage of 5V. Feedback is at pin DCDC_FB1 ble voltage feedback at pin DCDC_FB2. Bit stepX_res (X = 1 or 2) should be set to 1 in voltage feedback mode using two resistors.
Table 6. Step Up Output Voltage (Voltage mode or protection voltage)
Figure 7. DC/DC step up converter 1 with regulated output voltage (15V), and switch off function of output R1, R2 and the connected output circuit. Note: A similar circuit can be used for step up converter 2.
8.1.2 StepUp1 Load Detection and Overcurrent Protection Circuit
This circuit protects the DCDC step up1 converter during short circuit and startup, by regulation of the output current. converter is not in Pulseskip for more than 1 millisecond, the stepup1_det bit will be set. Table 7. StepUp1 protection/detection circuit parameters
Figure 8. StepUp 1 Load Detection and Overcurrent Protection Application Circuit
8.1.3 Step Up DCDC Converter Registers
Table 8. Step Up DC/DC Bit definitions Table 9. Step Up DC/DC Bit definitions
0 Use positive edge of internal clk
1 Use negative edge of internal clk
1 Select 1 if DCDC_FB1 or DCDC_FB2 is used with
Table 10. Step Up DC/DC Bit definitions
0 No protection and load detection
1 Short protection and load detection enabled
Table 11. Step Up DC/DC Bit definitions
00 DCDC_FB enabled (external resistor divider)
01 DCDC_CURR1 feedback enabled (feedback
10 DCDC_CURR2 feedback enabled (feedback
11 DCDC_CURR3 feedback enabled (feedback
Table 12. stpup1_det and stpup1_oc Bit definitions
8.2 Current Sinks
current sink has an integrated protection against over voltage and can therefore also drive inductive loads (VPROTECT). functions optional (described in section General Purpose Input / Output (CURR1_GPIO1 … CURR4_GPIO4) ).
0 Overvoltage protection disabled
1 Switch off DCDC step up 2 if the voltage on
0 VRsense < VOVCURRENT
1 VRsense > VOVCURRENT for more than 5 msec (latched
8.2.1 High voltage Current Sinks (DCDC_CURR1, DCDC_CURR2 and DCDC_CURR3)
Table 13. Current Sinks Characteristics Table 14. DCDC_CURR1 Current sink current bit definition Table 15. DCDC_CURR2 Current sink current bit definition
Table 16. DCDC_CURR3 Current sink current bit definition Table 17. Current sink control bit definition
00 Current sink is turned off
01 Current sink is active
10 Current sink is active and LED string connected to
11 Controlled by PWM generator (do not set pwm_div)
8.2.2 Low voltage Current Sink (CURR1_GPIO1 … CURR4_GPIO4)
the current sinks must not exceed the supply VCURR_GPIO (can be connected e.g. to VSUPPLY). (CURR1_GPIO1 … CURR4_GPIO4) on page 30) for enabling/disabling of the current sinks / gpio functions. Table 18. Current Sinks Characteristics Table 19. CURR1 Current sink current Bit definition Table 20. CURR2 Current sink current Bit definition
Table 21. CURR3 Current sink current Bit definition Table 22. CURR4 Current sink current Bit definition
8.3 General Purpose I nput / Output (CURR1_GPIO1 … CURR4_GPIO4)
Figure 9. CURR1_GPIO1 … CURR4_GPIO4 block diagram output the output source can be a register bit, or the PWM generator, furthermore the output signal can be inverted.
down resistor can be enabled.
0.3 V Pin VCURR_GPIO is used as supply for
Table 24. CURR1_GPIO1 Bit definition
5 GPIO1Invert ROM R/W
Table 25. CURR2_GPIO2 Bit definition
5 GPIO2Invert ROM R/W
Table 26. CURR3_GPIO3 Bit definition
5 GPIO3Invert ROM R/W
Table 27. CURR4_GPIO4 Bit definition
5 GPIO4Invert ROM R/W
Table 28. GPIO Signal Bit definition
0 GPIO1 0 R/W This bit determines the output signal of the GPIO1 pin when
1 GPIO2 0 R/W This bit determines the output signal of the GPIO2 pin when
2 GPIO3 0 R/W This bit determines the output signal of the GPIO3 pin when
3 GPIO4 0 R/W This bit determines the output signal of the GPIO4 pin when
Table 29. PWM Frequency Control High Time Registers Table 30. PWM Frequency Control Low Time Registers Table 31. PWM Divider Registers bits
00 Divide by 1
01 Divide by 2
10 Divide by 4
11 Divide by 16
Note: The original digital interface on/off signal is used to switch between CURR3_GPIO3 and CURR4_GPIO4; e.g. CURR4_GPIO4 (ldo_rf1_on=0) as input. Table 32. Regulator GPIO Control Registers
0 Controlled by software (ldo_rf1_on)
0 Controlled by software (ldo_rf2_on)
0 Controlled by software (ldo_dig1_on)
0 Controlled by software (ldo_dig2_on)
0 Controlled by software (sd1_on)
0 Controlled by software (sd2_on)
8.4 Backup Battery Charger
“Off” as well; the device will check VVBACK every minute to determine if charging is required.
0 Controlled by software (sd3_on)
0 Controlled by software (ldo_dig3_on)
Figure 10. Backup Battery Charger Block Diagram Table 33. Backup Battery Charger Characteristics
30 BBCResOff=’1’
0.5 BBCPwrSave=’1’; backup battery
Table 34. Backup Battery Charger Register Off mode”, “standby mode” and “Active mode”.
2 BBCResOff 0 R/W
0 Enable output resistor
1 Bypass output resistor
This value determines the charge current IBBC.
Figure 11. Backup Battery Charger Characteristics
5 BBCVolt 0 R/W
6 BBCPwrSave 1 R/W 0 Normal operation of the backup battery charger
8.5 Smooth switchover Power Management Overview
Figure 12. Power Source Management Architecture system power supply VSUPPLY and its power requirements. VBAT. Because of the very low impedance of the switches the energy losses are minimized.
- The active charger can deliver more current than the system requires
source between VSUPPLY and VBAT delivers the trickle current to the battery.
- The current limited (e.g. for USB with 500mA) charge r cannot deliver the current, the system requires
The blocks are described in more detail in the following sections.
8.6 Battery switch SINT (Vsupply, Battery)
Figure 13. Battery Switch Diagram PMOS is switched on if VBAT is greater then ResVolt. defined by constant_current[2:0]. connection between VBAT and VSUPPLY. Table 35. Battery switch parameters
Table 36. USB-Charger Bit definitions
1 Over temperature protection of battery switch
0 External battery switch disabled (Pin BAT_SW =
Table 37. Battery switch status Bit definitions
0 Battery switch off
1 Battery switch on (Mode defined by batsw_mode)
8.7 External Step Down/Linear Charger
Figure 14. Step Down Charger Application Diagram with optio nal reverse polarity and short protection
Figure 15. Charger Block Diagram for voltages >15V (Protection up to 50V; minimum Vcharger voltage 8V)
Figure 16. External Linear Charger Application Diagram (VOFF_B connected to GND) Table 38. Charger External Components
Figure 17. Step down charger Efficiency (Measured) VSupply=4.4V
8.7.1 External Step Down/Linear Charger Characteristics
The battery charge controller controls the external Step Down/ Linear charger. During Trickle charge of the deeply discharged battery the ste p down/Linear converter regulates the Vsupply to Vchlimit. to Vsupply. The battery current is regulated to the value defined in ConstantCurrent register. regulated by the battery switch to the value defined in the constant current register. If isolate_battery = 1 and EOC the output is regulated to Vchlimit. If isolate_battery = 0 and EOC the output is not allowed to drop below VEOC (3.6V). Table 39. Step down Charger parameters
Table 40. Step down Charger Bit definitions
8.8 USB Charger
Figure 18. USB Charger Block Diagram
0 Disable 100% PMOS on mode for step down charger
1 Enable 100% PMOS on mode to reduce voltage drop
0 Normal mode of step down charger mode
mode with max. 5.5V charger only. Vsupply=Vcharger in that mode, if no_charging=1.
s to be done by e.g. the uProcessor directly) a different current setting can be set to speed up charging (e.g. If ChEn=1 and chdet=1 (external charger enabled and connected) the usb_ charger will be deactivated automatically. Tricklecurrent [1:0] register. Table 41. USB-Charger Bit definitions ts the USB input current limit.
Table 42. Charger status Bit definitions The Charger will be detected by comparison of the V_ USB voltage with the Vsupply voltage. If V_USB is 50mV higher than VSupply voltage or V_USB > 4.3V or the USB_ChDet is set to 1. Table 43. USB Charger Characteristics,VUSB=4.3…5 .5V; Tamb=–20…+85°C; unless otherwise specified.
1 Overtemperature protection of battery switch
0 Normal battery charger operation (usb
VSUPPLY , but battery switch is open.
0 External battery switch disabled (Pin
0 USB_ChDet NA R set to 1 if charger is detected
4 Ch_overvoltage NA R Set to 1 if overvoltage on pin VCHARGER is applied
Table 44. USB-Charger additional trimming
8.9 Battery Charge Controller
8.9.1 Charge Controller Operating Modes and Building Blocks
www.austriamicrosystems.com Revision 1v13 52 - 157 AS3658 Data Sheet Confidential - Detailed Description-Power Management Functions above the battery voltage. In case the AS3658 device is reset the charge controller will also be reset, even if a charge adapter is applied to the VCHARGER or V_USB pin. Charging deeply discharged batteries To be able to charge even completely discharged batteries the AS3658 device contains an internal voltage regulator that uses the voltage of the external charge adapter at pin VCHARGER or V_USB to generate a bootstrap voltage V2_5V to supply the internal circuitry necessary for charging. As soon as the battery voltage exceeds 2.5V, the bootstrap regulator is disabled and the battery voltage will be used to generate the internal supply voltage to supply the charger circuitry. Low current (trickle) charging Trickle charge mode is started when an external charge adapter has been detected and ChEn or usb_chgEn is set, and the battery voltage at pin V_BAT is below the ResVoltRise threshold VRESRISE. The Battery switch is open in that case (batsw_on=1 batsw_mode=0). Bits ChAct and/or USBChAct and Trickle will be set in the Charger Status registers. In this mode the charge current into the battery will be limited to TrickleCurrent (set in the Charger Current register) by the battery switch to prevent undue stress on either the battery or any of the charger components in case of deeply discharged batteries. if Vsupply drops below V supply_min threshold the trickle current is regulated down, to keep the Vsupply voltage up, even with an current limited charger (e.g.:USB charger). Once VRESRISE has been exceeded, the battery switch will be closed and the charge controller will proceed to constant current charge mode. The Vsupply voltage of the step down charger will be set to Vcurr_preset to prevent undervoltage on vsupply during the transition between Trickle and constant current charging. Constant current charging Constant current charging is initiated by setting bit ChEn and/or USBChEn in the Charger Control register, and resetting the No_charging bit. Note that ChEn and/or USBChEn should be set by default to enable operation of the device without a battery connected to the system. The ChAct and/or USBChAct bit is set when the charger has started, and the charge current into the battery will be limited to ConstantCurrent (set in the Charger Current register) by the battery charge controller. When the battery approaches full charge, its instantaneous voltage will exceed the charge termination threshold VCHOFF. VCHOFF depends on the ChVoltEOC.The top-off charge mode will be started (bit CVM will be set). Constant voltage charging Constant voltage charge mode is initiated and the CVM bit will be set when the VCHOFF threshold has been exceeded for the first time and bit Pulse is not set. In the following the charge controller will act to regulate the battery voltage to a value set by ChVoltEOC in the Charger Config register. The charge current is monitored during co nstant voltage charging. It will be decreasing from its initial value during constant current charging and eventually drop below the value set by TrickleCurrent in the Charger Current register. If the measured charge current is less than or equal to TrickleCurrent and the battery voltage is larger than VCHRES, the charging cycle is terminated and EOC is set. Then the charge controller starts the EOC operation. EOC operation There are two possibilities: 1. If isolate_bat=1 the battery switch will be switch of f and the battery charger regulates to its highest voltage Vchlimit.. The advantage of this mode is a longer lifetime of the Li+ battery, because there is no discharging after the EOC condition. If autoresume=1 and the battery voltage drops below VCHRES the battery charger continues charging, by checking in trickle charge mode, if there is a battery connected, and then starting with constant voltage. 2. If isolate_bat=0 the battery switch remain s closed for step down charger or will be closed for linear and usb charger, and the power to the system is supplied by the battery. The battery charger and the USB charger regulates to VEOC, in case the battery is removed. If autoresume=1 and the battery voltage drops below VCHRES the battery charger continues charging, by checking in trickle charge mode, if there is a battery connected, and then starting with battery charging. ams AG Technical content still valid
NoBat bit is cleared and charging is restarted, if a NTC resistor with normal or high temperature is detected. the pin VCHARGER drops below VVCHIN,MAX fall, the charger is re-enabled. Figure 19. Typical charging cycle (step down charger)
Figure 20. Typical charging cycle (External linear charger or USB charger) Table 45. Charger Characteristics VVBAT=3.0…5. 5V; Tamb=–20…+85°C; unless otherwise specified
6.0 V ChOVDetEn=’1’ for external linear
Table 46. Charger status Bit definitions
3 Trickle NA R Bit is set when charger is in trickle charge mode
is set or charging is resumed. is set and/or when ChEn is cleared.
7 ChLinear NA R
Table 47. Charger control Bit definitions
0 Disable step down charger (Independent of bit
1 Enable step down charger (default) (Independent
1 Ch_pwroff_en ROM R/W
0 Startup of AS3658 if charger is connected in
autonomous charging upon static charger detect.
2 CHOVDetEn ROM R/W
0 Overvoltage detection with linear external charger
3 AutoResume ROM R/W
0 Charging does not restart automatically in EOC
1 Charging will restart automatically in EOC when bit
0 Normal charge_detect operation
6 Ch_det_500ms ROM R/W
0 VCHARGER debounce timer is 3msec
1 VCHARGER debounce timer is 500msec
Table 48. Battery, supply voltage Bit definitions
6 SupResEn ROM
A reset is generated if Vsupply falls below 2.7V.
7 FastResEn ROM R/W
0 Vresetfall debounce time = 3msec
1 Vresetfall debounce time = 4µsec
8.9.2 Fuel Gauge
of the battery using a voltage-to-frequency converter. current accumulators to accurately reflect the total charge that has gone into or out of the battery. Table 49. Charger Config Register Sets the end-of-charge voltage level VCHOFF.
(battery is discharged) will cause the integrator output voltage to decrease. Table 50. Fuel Gauge parameters cleared automatically and the charge current accumulator together with the sign bit will be reset. will be ambiguous in that case. It is the responsibility of the host to read the counter before rollover occurs. automatically and the elapsed time counter will be reset.
www.austriamicrosystems.com Revision 1v13 60 - 157 AS3658 Data Sheet Confidential - Detailed Description-Power Management Functions transferred to the DeltaCharge register. The CalReq bit is cleared automatically after the calibration has completed successfully and FGOffCal has been written to the register. Please note that offset calibration is not p ossible while the charger is active. If the CalReq bit is set while the charger is active the calibration will start automatically after the charger has been disabled by clearing the ChEn bit or if the external charge adapter has been removed. If during an offset calibration procedure the charger is enabled the offset calibration mode is terminated, the CalReq bit is cleared, the current value of the elapsed time counter is transferred to the ElapsedTime register and the DeltaCharge register is loaded with (FFFF)h. Calculation of Battery Status The host system can calculate all the parameters necessary for estimating the remaining battery capacity by evaluating ElapsedTime, DeltaCharge and FGOffCal. Calculating Elapsed Time The host system can evaluate the change in time Δt by setting the UpdReq bit in the FuelGauge register and reading ElapsedTime after UpdReq has been automatically cleared. The change in time in seconds is given by: Δt = ElapsedTime x 3600 / 4096.60 [s] (EQ 1) Note that the absolute accuracy of Δt is directly related to the absolute accuracy of the internal reference oscillator. To cancel the error associated with the accuracy of the oscillator, a correction factor CV can be introduced. CV can be evaluated by comparing the change in time calculated by (1) with some reference value ΔtREF obtained from a RTC or measured during system calibration. CV is given by: CV = ΔtREF / Δt( EQ 2) By multiplying Δt and CV the correct value for the change in time can be calculated: ΔtCORR = CV x Δt [s] (EQ 3) Calculating Average Current The host system can calculate the average current du ring the last time period by setting the UpdReq bit in the FuelGauge register and reading DeltaCharge and ElapsedTime after UpdReq has been automatically cleared. Together with FGOffCal determined during offset calibration mode the average current is given by: IAVG = DeltaCharge / (Δt x AVFC x Rsense) – FGOffCal x 3.05µV / Rsense [A] (EQ 4) Δt is the chang e in time in seconds calculated by (1), AVFC is the gain of the VFC in Hz/V, Rsense is the value of the sense resistor in Ω and F GOffCal is the offset calibration value. As DeltaCharge and Δt both are proportional to the oscillator frequency, no correction factor needs to be introduced in the formula. Calculating Accumulated Current Accumulated current is used to calcu late the absolute remaining capacity of the battery. It is given by: IACC = IAVG x ΔtCORR [A] (EQ 5) Calculating the Remaining Capacity Remaining capacity is the entire goal of fuel gauging. It is given by: RC = RC + IACC [As] (EQ 6) ams AG Technical content still valid
Table 51. Fuel Gauge Bit definitions Table 52. Delta Charger MSB bit definitions
0 FGEn ROM R/W
0 Disable Fuel Gauge
1 Enable Fuel Gauge
1 UpdReq ROM R/W
0 Update of registers complete
1 Request update of registers
2 CalReq ROM R/W
0 Calibration complete OR terminate offset
1 Request offset calibration
00 Connect inputs to ground internally
01 Use ISENSP and ISENSN (do not use)
scale value of 1.999Ah. Sign is set for negative values. Register will be updated after setting bit UpdReq to “1”.
Table 53. DeltaChargerLSB bit definitions Table 54. ElapsedTimeMSB bit definitions Table 55. ElapsedTimeLSB bit definitions
8.9.3 Charger Operation
step down charger and the battery switch between VSUPPLY and VBAT. a resolution of 0.625mV or 12.5mA when using a sense resistor of 50mΩ. Table 56. Charge Current Regulator parameters scale value of 1.999Ah. Sign is set for negative values. Register will be updated after setting bit UpdReq to “1”. resolution of 0.8788s and a full-scale value of 15.997 hours. Register will be updated after setting bit UpdReq to “1”. resolution of 0.8788s and a full-scale value of 15.997 hours. Register will be updated after setting bit UpdReq to “1”.
Table 57. Charger Current Bit definitions
8.10 Charger supervision functions
In addition there is a charge timer that stops charging after a defined time, as additional security feature. charging only (Trickle charging, Constant current charging, Constant voltage charging). charging_tmax=0 in the charger_control1 register.
Figure 21. Charger Supervision functions – internal circuit Table 58. NTC Chargersupervision Characteristics, VVBAT=3.0…5.5V; Tamb=–20… +85°C; unless otherwise
1.8 V On pin ADC_IN1, if ntc_on<1:0>=1
Table 59. Charger supervision bit definitions
Table 60. FuelGauge
00 Disable NTC supervision
01 Enable NTC supervision
10 Enable NTC for ADC measurement high temp
11 Enable NTC for ADC measurement low temp
8.11 Step Down DC/DC Converters
8.11.1 Step Down DC/DC Converters Operating Modes
operating mode is selected by setting the register sdx_1A_mode (the default is set by the Boot ROM). Figure 22. DC/DC step-down SD1, SD2, SD3 Normal Operating Mode; sdx_1A_mode = 0000b Figure 23. DC/DC step-down SD1, SD2, SD3 1A Operating Mode; sdx_1A_mode = 1010b
Figure 24. DC/DC step-down SD3 (as example) not used Note: VCURR_ GPIO has to be connected to VSUPPLY if the external controler mode is used.
Figure 26. DC/DC step-down SD1, SD2, SD3 External Controller Operating Mode and SD2 in 1A mode; External Controller’ operating mode configuration. VCURR_GPIO has to be connected to VSUPPLY if the external controler mode is used.
8.11.2 Step Down DC/DC Converter Characteristics
Figure 27. Step Down DC/DC Converter Block diagram only 10µF. The implemented current limitation protects the DCDC and the coil during overload condition.
can be set, to allow 100% duty cycle of the PMOS transistor. blocks during pulseskip mode, which results in a better efficiency at light output loads. Table 61. Step Down DC/DC Converter parameters
100 Low power mode current
0.1 Shutdown current
2.2 SD1 external controller mode; use
Table 62. Step Down DC/DC Bit definitions Table 63. Step Down DC/DC Bit definitions
0 Increased current consumption in pulseskip mode
1 Decreased current consumption in pulseskip
always on) if output voltage drops more than 4%. Increased output ripple in that operation.
1 PON feature disabled: Maximum dutycycle=1-
always on) if output voltage drops more than 4%. Increased output ripple in that operation. always on) if output voltage drops more than 4%. Increased output ripple in that operation.
Table 64. Step Down DC/DC Bit definitions Table 65. Step Down DC/DC Reg Power1 ctrl Bit definitions
0 Step Down DC/DC 1 off
1 Step Down DC/DC 1 on
0 Step Down DC/DC 2 off
1 Step Down DC/DC 2 on
Table 66. Step Down Voltage1 Bit definitions Table 67. Step Down Voltage2 Bit definitions
0 Step Down DC/DC 3 off
1 Step Down DC/DC 3 on
Table 68. Step Down Voltage3 Bit definitions Table 69. Step down1 high current and DVM definitions
Table 70. Step Down DC/DC Bit definitions
8.11.3 Typical Performance Chara cteristics
Figure 30. DC/DC step-down Efficiency (sdX_dis_curmin=0, sdX_lpo=0) Figure 31. PCB Layout recommendation 1 Enable SD1 undervoltage limit.
0 Normal operation
1 Enable SD3 undervoltage limit. 1 Enable SD3 undervoltage limit.
8.12 Low Dropout Re gulators (LDO)
The low dropout regulators are linear high performance regulators with programmable output voltage. Table 71. LDO_RF1 voltage bit definitions Table 72. LDO_RF2 voltage bit definitions Table 73. LDO_RF3 voltage bit definitions
Table 74. LDO_DIG1 voltage bit definitions Table 75. LDO_DIG2 voltage bit definitions Table 76. LDO_DIG3 voltage bit definitions Table 77. LDO_DIG4 voltage bit definitions Table 78. LDOs Reg Power1 ctrl Bit definitions in external controller mode (if sd1_1A_mode = 1100b).
Table 79. LDOs Reg Power2ctrl Bit definitions
8.12.1 RF LDO’s (VRF_1, VRF_2, VRF_3)
performance for battery powered devices. nearly discharged batteries without any decrease of performance.
Figure 32. Analog LDO Block diagram Table 80. Analog LDO (VRF_1, VRF_2, VRF_3) Characteristics, Vx_IN=4V; ILOAD=150mA; Tamb=25ºC;
8.12.2 Digital LDO’s (VDIG_1, VDIG_2, VDIG_3, VDIG_4)
is required. The 5V charge pump will be switched on automatically, if one of the digital LDO’s are switched on. Figure 33. Digital LDO Block diagram
- Guaranteed by design and verified by laboratory evaluation and characterization; not production tested.
Table 81. Digital LDO (VDIG1, VDIG2, VDIG3, VDIG4) Characteristics,VSUPPLY=4V; ILOAD=200mA; Tamb=25ºC;
- Guaranteed by design and verified by laboratory evaluation and characterization; not production tested
Table 82. Digital LDO (VDIG_1.4) Programming voltage table
8.12.3 Low power LDO (V2_5)
Table 83. Low power LDO (V2_5) Characteristics,VBAT=4V; ILOAD_ext=0; Tamb=25ºC; CLOAD =2.2 µF (Ceramic);
Figure 34. 5V Charge Pump Block diagram this level. In this mode the supply current is reduced, but the output ripple is increased. Table 84. Charge Pump External Components chip internal load for measurements.
1 A Peak current of schottky Diode
Make the connections of the external capacitors as short as possible. Table 85. Charge Pump Characteristics Table 86. CP Power1 ctrl Bit definitions Table 87. Charge Pump Bit definitions
0 Normal fixed frequency mode
1 Pulse skip, low power mode (Set cp_frequ=1 in
9 Detailed Description- Audio Functions
Figure 35. AS3658 Au dio Functions
9.1 Audio Paths
Figure 36. AS3658 I2S I/O 1 or I2S I/O2 Playback interface or I2S Output 3 and SPDIF Output 4 can be used at the same time.
Figure 39. AS3658 Microphone Recording and I2S I/O Playback (either I2S 1 or I2S 2/PCM) Figure 40. AS3658 Recording of the Mixed output signal and parallel playback (either I2S 1 or I2S 2/PCM)
9.2 Common mode voltage generation of HP_CM, LINE_CM
startup, PSRR of the amplifiers and sense path of the GND cancellation circuit. Table 88. common mode voltage, Audio start-up and PSRR
9.3 Audio Setup Registers
Audio LDO has to be switched on first (aud_ldo_on=1), and enables all other functions. Table 89. AudioSet1 Register
1 Line input enabled
0 DAC disabled
1 DAC enabled (Switch on, if I2S signal valid only)
0 Mixer switched off
1 Mixer switched on
0 GND switch off 0V at pin GND_SW
1 GND switch on Vsupply at pin GND_SW
0 Audio LDO off
1 Audio LDO on
0 Change of LRCLK at falling edge of MCLK
1 Change of LRCLK at rising edge of MCLK
0 MCLK = LRCLK* 128
1 MCLK = LRCLK* 256
0 Equalizer switched off (bypassed)
1 Equalizer switched on
Table 90. AudioSet2Register
01 Don't use
10 Don't use
11 Don't use
3 I2S_3_on 0 R/W
0 Switch off I2S_3 output
1 Switch on I2S_3 output
9.4 ADC, DAC and Di gital Audio Input
9.4.1 General
generate the analog audio signal. The stage is set to mute by default; If the DAC input is not enabled.
9.4.2 Signal Description
rates the bit pll_mode has to be set (for sample rates between 8kHz and 12kHz). This audio input interfaces uses an I2S synchronizer to be able to handle audio sample length of 24bits or less.
6 I2S_select 0 R/W
0 Select I2S_1 input
1 Select I2S_2 input
7 I2S_mclk_en 0 R/W
0 Generation of the master clock by the internal PLL
1 Use Pin MCLK_1, MCLK_2 as masterclock input
Figure 41. I2S Control Diagram Figure 42. I2S Timing Diagram Table 91. PLL,MCLK Settings
000 I2S_1 selected (PLL used)
001 I2S_1 selected (PLL used)
010 I2S_2 selected (PLL used)
011 I2S_2 selected (PLL used)
18 Bit DAC
14 Bit ADC
9.4.3 Parameter
Table 92. Audio DAC/ADC Parameter Table 93. I2S Parameter Table 94. DAC_L Register
0 DAC input is set to mute
Table 95. DAC_R Register Table 96. ADC_L Register
0 ADC disabled
1 ADC enabled
0 ADC input is set to mute
Table 97. ADC_R Register
9.5 I2S master mo de and PCM Mode
The digital audio interface can also operate in master mode by using I2S1 interface. aster Mode operation SCLK1 as output has 32 clock cycles for each sam ple word. master clock and sample ratio a certain deviation is system inherent.
00 Microphone
01 Line In
11 Audio Sum (Output of Mixer)
Table 98. PLL,i2s_clk_divider settings
Table 99. i2s master control1 Register Table 100. i2s master control2 Register
0 LRCLK1 and SCLK1 are used as input (slave
0 MCLK1 used as input (slave mode)
0 Normal operation of MCLK1 (input or output
1 MCLK1 used as SDO output (e.g. for audio ADC).
9.5.1 PCM mode settings
Figure 43. Short Frame Sync (shown with 16-bit Sample) Note: Internally the right channel is copied to the right and left channel.
0 Normal I2S mode
In short Frame Sync the falling edge of PCM_SYNC indicate the start of the PCM word. PCM_Sync is always one clock cycle long.
9.6 Line Input
9.6.1 General
AS3658 includes one stereo single ended inputs. Figure 44. LineIn Block Diagram Table 101. Line Inputs Parameter Table 102. LINE_IN_R Register
9.7 Five Band Equalizer
+6dB amplification of each band. Figure 45. Equalizer Block Diagram Table 103. LINE_IN_L Register
Figure 48. EQ Filter frequency response -3dB Each band has a range from -12 to +12 dB with each increment equal to ±3dB. For sample frequencies of the I2S stream different from 44.1kHz, the filter frequencies are shifted (ratiometric). Table 104. EQ_LP Register
Table 105. EQ_Band1 Register Table 106. EQ_Band2 Register
Table 107. EQ_Band3 Register Table 108. EQ_HP Register
Table 109. EQ_preamp Register
9.8 Microphone Input
activation, microphone connect detection and push button remote control. Figure 49. Microphone Input Block diagram and External Circuit ON by default but can be disabled by a microphone register bit. be set from –40.5dB to +6dB. values. Changing the volume and mute control can only be done after enabling the input. external voltage the 30kΩ pull-up can be disabled.
Table 110. Microphone Inputs Parameter, TA= 25oC unless otherwise mentioned
Table 111. MIC_R Register Table 112. MIC_L Register
9.9 Audio Output Mixer
9.9.1 General
This stage features an automatic gai n control (AGC), which automatically avoids clipping.
9.9.2 Register Description
Table 113. AudioSet_3 Register
0 Pulldown disabled if hp_on=1
1 Pulldown of the not used HP1/2 output
9.10 Line Output
9.10.1 General
The line output is designed to provide the audio signal on 600 Ω min. can be set from –40.5dB to +6dB.
9.10.2 No-Pop Function
shutdown, have to be waited before starting up again.
9.10.3 Ground Noise Cancellation
The purpose of the ground cancellation circuit is to compensate noise (ground noise) between different grounds (e.g. cancellation circuit can be used for line and headphone amplifiers. RGND_SEP (20Ω) to the battery ground.
e instead of the car amplifier is connected to the output jack. Note: A similar cicuit can be used for the headphone amplifier.
9.10.4 Power Save Options
To save power, a reduction of the bias current can be selected. Table 114. Line Power-Save Options
9.10.5 Parameter
Table 115. Line out Block Characteristics
9.10.6 Register Description
other Line/headphone driver settings are controlled by the following two registers. Table 116. LINE_OUT_R Register
0 Line_out amplifier input connected to mixer
Table 117. LINE_OUT_L Register
9.11 Headphone Output
can be set from –40.5dB to +6dB.
9.11.1 Phantom Ground
HP_CM_PWR pin is the buffered HP_CM output. It can be used to drive the common mode level with a load of 2kΩ. ntom ground can be switched off to save power if not needed.
9.11.2 No-Pop Function
to be waited before starting up again.
9.11.3 Over-current Protection
0 Line stage not powered
1 Line output set to mute (mute is on during
9.11.4 Power Save Options
To save power, especially when driving 32 Ω loads, a reduction of the bias current can be selected.
9.11.5 Parameters
Table 118. Power Amplifier Parameter
9.11.6 Register Description
To get an interrupt on an over-current event, the corresponding bit in the Interrupt enable register has to be set. settings are controlled by the following two registers.
Table 119. HPH_OUT_R Register Table 120. HPH_OUT_L Register
9.12 SPDIF output
Table 121. SPDIF Register
00 SPDIF output OFF
01 SPDIF output ON
0 Select adc_output
1 Select Equalizer output
0 Normal mode
1 Invert SCLK1 or SCLK2 input
10 Detailed Description - System Functions
programming, the watchdog, internal references, the ON-key detect and the real time clock module. Table 122. I2C SDA,SCL Characteristics
10.1.1 Feature List
10.1.2 Transfer Formats
Figure 51. I Figure 52. I Byte-Write and Page-Write are used to write data to the slave.
Figure 55. I acknowledge following the last data byte and a subsequent STOP condition.
10.2 Reset generator and XON-Key
XRESET is a low active bi-directional pin. An external pull-up to the periphery supply has to be added. All registers are set to their default values after power-on, except the reset control- and status-registers. Table 123. XRESET,XON Characteristics
10.2.1 Reset Conditions
VCHARGER, VBAT or V_USB as its source. The pin RESET is only released if V2_5 is above VPOR and VSUPPLY is above VXRESETRISE. Table 124. Reset Levels complete reset of the system in case of short drops of VBAT. reset control registers all other registers are set to their default value after power-on.
2.7 V Monitor voltage on VSupply; falling
- VRESET signal is debounced with the specified mask time for rising- and falling slope of VBAT.
10.2.2 Reset Control Bits
Table 125. Reset Timer Register
000 RESTIME=10ms
001 RESTIME=20ms
010 RESTIME=35ms
011 RESTIME=50ms
100 RESTIME=65ms
101 RESTIME=80ms
110 RESTIME=95ms
111 RESTIME=110ms
Table 126. Reset Control Register
0000 VPOR has been reached (battery or charger
0001 VRESETFALLING was reached (battery voltage
7 Onkey_reset_5s 1 R/W
0 Reset after 5 seconds ON pressed disabled
1 Reset after 5 seconds ON pressed enabled
Table 127. Internal references Bit definitions regulators enabled by reg.81h “Reg standby mode”. register are continuously on.
5 Clk_div2 0 R/W
Table 128. Reg standby mode Bit definitions
6 Reg_low_bias_mode 0 R/W
0 RF1 LDO is disabled in standby mode
1 RF1 LDO is enabled in standby mode
0 RF2 LDO is disabled in standby mode
1 RF2 LDO is enabled in standby mode
0 DIG1 LDO is disabled in standby mode
1 DIG1 LDO is enabled in standby mode
0 DIG2 LDO is disabled in standby mode
1 DIG2 LDO is enabled in standby mode
0 Step down 1 is disabled in standby mode
1 Step down 1 is enabled in standby mode
0 Step down 2 is disabled in standby mode
1 Step down 2 is enabled in standby mode
0 Step down 3 is disabled in standby mode
1 Step down 3 is enabled in standby mode
0 Charge pump is disabled in standby mode
1 Charge pump is enabled in standby mode
Table 129. Charger supervision Table 130. Fuel Gauge
10.2.3 Reset Cycle
happens (see Startup on page 129), the reset is active until the reset timer (set by register bits re s_timer<2:0>) expires.
10.2.4 Reset Control: res_con
supervisor. Additionally Reset can be forced by software.
0 Startup of all regulators if battery is inserted,
charger insertion, onkey pressed or rtc alarm.
1 If low battery is detected, enter power off
10.3 Interrupt Controller
read access will be cleared as well in case it occurs again before the clearing process has completed. XINT) before the Interrupt 2,3 register has been read. Table 131. Interrupt Status 1 Register 3 usb_chdet_i NA R Bit is set when the USB_ChDet Bit is set or reset. 4 chdet_i NA R Bit is set when the ChDet Bit is set or reset. 5 Onkey_i NA R Bit is set when status XON bit is set or reset.
7 Lowsup NA R Bit is set when the main supply voltage VSUPPLY has
dropped below VRESFALL for longer than tRESMASK. Table 132. Interrupt Status 2 Register
Table 133. Interrupt Status 3 Register 7 stpup1_i NA R Bit is set when stpup1_oc or stpup1_det is set. Table 134. Interrupt mask 1 Register
0 Interrupt is enabled
1 Interrupt is disabled
Table 135. Interrupt mask 2 Register
7 LowSup_int_mask 1b R/W
Table 136. Interrupt mask 3 Register Table 137. Low voltage status1 Register1 Table 138. Low voltage status2 Register1
10.4 Startup
Figure 56. Startup flow chart
10.4.1 Normal Startup
10.4.2 Startup from Charger
allows the battery to be charged (even from deeply discharged batteries) and finally a normal startup to happen. Table 139. Charger Startup Conditions
10.4.3 Programmable Startup Sequences—Boot ROM
Note: For detailed startup sequences see austriami crosystems AG document AS3658_BootROM_*. Table 140. Boot ROM Bits definitions
10.4.4 Additional Startup Settings
Table 141. Boot ROM Bits definitions
10.4.5 Programmable Startup Sequences with fuse registers—Boot OTP
Table 142. ROMF Bit definitions Table 143. ROMF Bit definitions Table 144. ROMF Bit definitions
0 Normal reset pulse
0 Normal startup of LDOs defined in boot rom
1 Startup of all LDOs defined by boot rom with a
1 Feasible startup of rom enabled
0 Use data of ROM table during startup for the
Table 145. ROMF Bit definitions Table 146. ROMF Bit definitions Table 147. ROMF Bit definitions Table 148. ROMF Bit definitions Table 149. ROMF Bit definitions
Table 150. ROMF Bit definitions Table 151. ROMF Bit definitions Table 152. ROMF Bit definitions Table 153. ROMF Bit definitions
10.5 Protection Functions
condition is removed, whereas ov_temp_140 has to be reset by the serial interface with the signal rst_ov_temp_140. affected by this reset cycle allowing the software to detect the reason for this unexpected shutdown. Table 154. Overtemperature Detection Table 155. Overtermperature detection Bit definition
10.5.1 Temperature Supervision
software can react and can shutdown power consuming functions to decrease temperature. down mode and stops charging, and performs the reset cycle of the AS3658. overtemperature activation (ov_temp_140 is set). This flag is only resetable by writing ‘1’ to rst_ovtemp_140.
10.6 Watchdog
pin, which can be used e.g. as an interrupt to the processor. The complete block can be switched on by wtdg_on = 1 and off by wtdg_on = 0. The watchdog time window is defined by the register wtdg_min_timer and wtdg_max_timer. Table 156. Watchdog Register definitions Table 157. Watchdog minimum timer definitions Table 158. Watchdog max timer definitions e.g. a reset or interrupt for a processor.
0 Use the register bit wtdg_sw_signal as trigger
Table 159. Watchdog software signal definitions Figure 57. Watchdog timing diagram
10.7 General Purpose 10 Bit ADC
Table 160. ADC Characteristics
Table 161. ADC control Registers bits Table 162. ADC MSB result register
0111 ADC test channel – do not use
7 start_conversion 0b R/W Writing a 1 into this bit starts one ADC conversion.
0 D3 NA R ADC result register
4 NA R ADC result register
2 D5 NA R ADC result register
3 D6 NA R ADC result register
4 D7 NA R ADC result register
5 D8 NA R ADC result register
6 D9 NA R ADC result register
Table 163. ADC LSB result register Table 164. ADC IDAC register Figure 58. ADC Timing-diagram
0 D0 NA R ADC result register
1 D1 NA R ADC result register
2 D2 NA R ADC result register
10.8 Internal References (V, I, f clk)
Table 165. Reference External Components Table 166. References Parameters interface bit ‘low_power_on’. All specification parameters except the noise parameters are still valid for this mode. Table 167. Internal references Bit definitions
10.8.1 Low Power Mode
in this mode (e.g. increased noise), but still the full functionality is available. Note: Low p ower mode can be controlled by the serial interface.
1 Low power mode – all specification except
gauge, DCDCs, PWM, charge pump.
10.9 Real-Time Clock (RTC) Module
To start the RTC, rtc_mode bits have to be set to a non ze ro value, and the RTC registers have to be set. The RTC stops automatically at its highest value (3F,FF,FF,FF) to prevent overrun. Table 168. RTC Second Register Table 169. RTC Minute1 Register Table 170. RTC Minute2 Register Table 171. RTC Minute3 Register
Table 172. RTC Alarm second Register Table 173. RTC Alarm minute1 Register Table 174. RTC Alarm minute2 Register Table 175. RTC Alarm minute3Register
Table 176. RTCT Register Table 177. Reset Timer Register by removing or adding two clock cycles.
0 Disables
1 Enable RTC alarm wakeup in power off mode
0 Disables RTC repeated wakeup in power off
1 Enable RTC repeated wakeup in power off
10.10 Touchpen Interface
the SPDIF and the I2S Output 3 cannot be used (and has to be disabled). Note: Th e touchpen interface and the ‘General Purpose 10 Bit ADC’ can be used at the same time. Figure 59. Touchpen Block diagram
Figure 60. Touchpen State diagram
10.10.1 Software guidelines
- Setup the configuration registers (tpen – control 1..3) according the hardware
- Enable receiving of touchpen interrupts (either th rough XINT or GPIO4_CURR4)
- Upon receiving of a touchpen interrupt, readout tpen_xmsb, tp en_ymsb (and if required tpen_pressmsb and
- Perform all the required proce ssing with the data (e.g. accept a pen-down only if the pen is forced onto the
10.10.2 Touchpen Registers
Table 178. Touchpen Register Map Table 179. Touchpannel Result Register Bits Table 180. Touchpannel Result Register Bits Table 181. Touchpannel Result Register Bits Table 182. Touchpannel Result Register Bits
Table 183. Touchpannel Control Register Bits
0 OFF (No wakeup on pen down)
00 No delay between conversions
0 No Conversion if pen down detected
0 TP in Power down or Conversion ongoing
Table 184. Touchpannel Control Register Bits Table 185. Touchpannel Control Register Bits
00000 Do not use this Setting
0 Do not wait until tpen_xmsb is readout
1 Start next ADC – conversion after data is
0 Start conversion only if tpen_st_pen is 1
1 Measure regardless of pen Status (only if
0 Pen-down Debounce Time 100µs
1 Pen-down Debounce Time = 3ms
1 GPIO3_CURR3 can be configured as input
11 Register map
Table 186. Register Map
Figure 61. CTBGA124 8x8 0.5mm pitch
1 OF 2
- GENERAL TOLERANCE : ± 0.10
Figure 62. CTBGA124 Marking
12.1 Pinout Drawing (T op view) CTBGA 8x8mm
Figure 63. Pinout drawing Table 187. Package Code AYWWZZZ Table 188. Boot ROM revison
The device is available as the standard products listed in Table 189. Table 189. Ordering Information
www.austriamicrosystems.com Revision 1v13 157 - 157 AS3658 Data Sheet Confidential - Ordering Information Copyrights Copyright © 1997-2010, austriamicrosystems AG, Schloss Premstaetten, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or reg istered trademarks of their respective companies. Disclaimer Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. The information furnished here by austriamicrosystems AG is bel ieved to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to pe rsonal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services. Contact Information Headquarters austriamicrosystems AG A-8141 Schloss Premstaetten, Austria Tel: +43 (0) 3136 500 0 Fax: +43 (0) 3136 525 01 For Sales Offices, Distributors and Representatives, please visit: http://www.austriamicrosystems.com/contact B ams AG Technical content still valid