AS3606 AMSCO | Alldatasheet
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Technical content
Datasheet sections
- 1 General Description
- 2 Key Features
- 3 Application
- 4 Pin Assignments
- 4.1 Pin Descriptions
- 5 Absolute Maximum Ratings
- 6 Electrical Characteristics
- 7 Typical Operating Characteristics
- 8 Detailed Description - Power Management Functions
- 8.1 Low Drop Out Regulators
- 8.1.1 LDO5
- 8.1.2 LDO 1, LDO2, LDO3 & LDO4
- 8.1.3 Parameter
- 8.2 DCDC Step-Down Converter
- 8.2.1 Functional Description
- 8.2.2 Parameter
- 8.3.1 Voltage Feedback and OV Protection
- 8.3.2 Voltage Feedback
- 8.3.3 DLS & Dimming
- 8.3.4 Current Sinks
- 8.3.5 Parameter
- 8.4 Charger
- 8.4.1 Soft Charge/Trickle Charge
- 8.4.2 End of Charge Detection
- 8.4.3 VSUPSW and Temperature Supervision
- 8.4.4 Battery Temperature Supervision
- 8.4.5 No Battery Detection
- 8.4.6 Charger Modes
- 8.4.7 Parameter
- 9 Detailed Description - SYSTEM Functions
- 9.1 SYSTEM
- 9.1.1 Power Up/Down Conditions
- 9.1.2 Start-up Sequence
- 9.2 Hibernation
- 9.3 Supervisor
- 9.3.1 VSUP Supervision
- 9.3.2 VDD27 Supervision
- 9.3.3 Junction Temperature Supervision
- 9.3.4 Power Rail Monitoring
- 9.4 Interrupt Generation
- 9.4.1 IRQ Source Interpretation
- 9.4.2 Interrupt Sources
- 9.5.1 Input Sources
The technical content of this austriamicrosystems datasheet is still valid. Contact information: Headquarters: ams AG Tobelbaderstrasse 30
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System PMU with HV Back Light Driver www.austriamicrosystems.com Revision 1.03 1 - 70 Data Sheet
1 General Description
The AS3606/07 is an ultra compact System PMU with integrated battery charger and HV back light driver. The device offers advanced power management functions. All necessary ICs and peripherals in a battery powered mobile device are supplied by the AS3606/07. It features 3 DCDC converters as well as 5 low noise LDOs. The different regulated supply voltages are programmable via the serial control interface. The step-up converter for the backlight can operate up to 30V. Both constant voltage (OLED supply) as well as constant current (white LED backlight) operations with 2 current sinks are possible. An internal voltage protection is limiting the output voltage in the case of external component failures. AS3606/07 also contains a Li-Ion battery charger with constant current and constant voltage. The maximum charging current is 1A. An integrated battery switch and an optional external switch are separating the battery during charging or whenever an external power supply is present. With this switch it is also possible to operate with no or deeply discharged batteries. A programmable current limit can be used to control the maximum current used from a USB supply. The single supply voltage may vary from 2.7V to 5.5V.
2 Key Features
3 DCDC step down regulators - DVM (0.61V-3.3V, 700mA) - 50µA quiescent current - Selectable switching frequency (2 or 1MHz) - 1.4A with combined DCDC 2 & 3 1 LDO low noise 2.7V (2.3-3.5V), 100mA 3 or 4 LDOs low noise - 30µA quiescent current (low power mode) Power supply supervision (LDO5) 4sec and 8sec emergency shut-down Hibernation function HV Backlight Driver Step up for 30V backlight with internal transistor Voltage control mode and over-voltage protection 2 programmable current sink (max. 38mA) Max. 20mA@50V (with ext. transistor) or 500mA@5V Possible external PWM dimming input Battery Charger Prog. trickle charging (25-265mA) Prog. constant current charging (94-1060mA) Prog. constant voltage charging (3.9V-4.25V) Charger time-out and temperature supervision Selectable current limitation for USB mode Integrated battery switch & ideal diode External battery switch control output General Battery and Temperature Supervisor 2 or 4 General Purpose IOs 10bit general purpose ADC input PWM dimming input or wake-up input Status output for: charger, low battery, power good and power- up key OTP Programmable BOOT Sequence Programmable regulator default voltages Programmable start-up sequence Applicable for LDO 1-4 and DCDC 1-3 Control Interface I2C control lines, including watchdog Power-Up input Interrupt output Bidirectional reset, with selectable delay Low power standby mode, 160µA with LDO5 on Power-On Reset Circuit Packaging QFN32 5x5mm or QFN36 6x6mm, 0.5mm pitch
3 Application
The devices are ideal for Portable Media Players and Portable Navigation Devices, e-Books, Tablet PCs, etc ams AG Technical content still valid
www.austriamicrosystems.com Revision 1.03 4 - 70 AS3606 AS3607 2v2 Data Sheet - Contents ams AG Technical content still valid
4 Pin Assignments
Figure 3. Pin Assignments (T op View)
4.1 Pin Descriptions
Note: Pin description may change in preliminary data sheets. Table 1. Pin Description for AS3606/07
5 Absolute Maximum Ratings
Table 2. Absolute Maximum Ratings
- Depending on actual PCB layout and PCB used
- The reflow peak soldering temperature (body temperature) is specified according IPC/JEDEC J-STD-020 “Moisture/Reflow Sensitivity
6 Electrical Characteristics
Table 3. Electrical Characteristics
Table 3. Electrical Characteristics (Continued)
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7 Typical Operating Characteristics
VSUPx = +3.6V, TA = +25ºC, unless otherwise specified. ams AG Technical content still valid
8 Detailed Description - Power Management Functions
8.1 Low Drop Out Regulators
device to deliver up to 150mA even at nearly discharged batteries without any decrease of performance. Figure 4. LDO Block Diagram
8.1.1 LDO5
This LDO generates the digital supply voltage used for the PMU itself. operation. The default voltage cannot be changed in the boot ROM.
8.1.2 LDO 1, LDO2, LDO3 & LDO4
Cards, NAND-Flashes, FM-Tuner …). LDO4 is only available on AS3607.
8.1.3 Parameter
VSUPx=3.6V, TA= 25ºC, unless otherwise specified. Table 4. LDO Parameter
Figure 5. LDO Characteristics
8.2 DCDC Step-D own Converter
Figure 6. DCDC Step-Down Block Diagram
8.2.1 Functional Description
of 700mA, with an output capacitor of only 10µF. The implemented current limitation protects the DCDC and the coil during overload condition. low input to output voltage differences. In the case of an inverted coil current the regulator will not operate in pulse skip mode. Figure 7. DCDC Buck with Disabled Current Force / Pulse Skip Mode the output voltage ripple increases, and the noisy pulse skip operation is on up to a higher output current. Figure 8. DCDC Buck with Enabled Current Force / Pulse Skip Mode It’s also possible to switch between these two modes dynamically during operation.
DVM (Dynamic Voltage Management). To minimize the over-/undershoot during a change of the output voltage, the DVM can be enabled. rate of the output voltage is only determined by external components like the coil and load capacitor as well as the load current. voltage. FRM needs an 22uF output capacitor instead the 10uF one to guarantee the stability of the regulator. reduced to achieve a higher efficiency. cycle for the PMOS transistor, which is than in LDO mode.
8.2.2 Parameter
VSUP=3.6, TA= 25ºC, unless otherwise specified. Table 5. DCDC Parameter
Figure 9. DCDC Step-down Performance Characteristics
switching-frequency results in a low noise on supply and output voltages. due to the internal automatic feedback selection. and an internal current sink. has to be used to avoid an exceeding of the operation conditions in a no load situation. Figure 10. DCDC15 Block Diagram
8.3.1 Voltage Feedback
Setting bit SU_CURR_FB = 0 enables voltage feedback at pin FBSU.
Note: The voltage on CURR1 and CURR2 must not exceed 30V.
8.3.2 Over Voltage Protection (OVP)
described in the chapter above.
8.3.3 DLS & Dimming
controller for DLS (dynamic luminance scaling). Manual dimming can be done at any time by setting the sink current via I2C commands.
8.3.4 Current Sinks
Table 6. Voltage Feedback Example Values
8.3.5 Parameter
VSUPx=3.6V, TA= 25ºC, unless otherwise specified. Figure 11. 30V Step-Up Performance Characteristics Table 7. DCDC Parameter
8.4 Charger
charging currents (94 to 1000mA) and maximum charging voltage (3.9 to 4.25V). EOC (end of charge) and the battery switch, which is controlling the current into the battery. Per default the USB current limit is set to 470mA and the charger is switched off. The current battery and charger input voltage can be measured with the general purpose ADC. Figure 12. Charger Block Diagram
Figure 13. Charger States
8.4.1 Soft Charge/Trickle Charge
265mA. After reaching the 3V level the charger switches to the constant current mode with the programmed charging current.
8.4.2 End of Charge Detection
EOC level is reached an interrupt can be generated, but it is also possible to poll the charger status bits at any time.
8.4.3 VSUPSW and Temperature Supervision
temperature return to their normal operating range.
8.4.4 Battery Temperature Supervision
start charging again. This is forming a temperature hysteresis of about 3 to 5°C to avoid an oscillation of the charger. temperature supervision via the NTC can be switched off (NTC_ON = 0). The supply for the NTC will be only on when a charger is detected and NTC_ON bit is set.
8.4.5 No Battery Detection
After this a sensing current of 1uA is applied to the BATTEMP pin to detect if a battery is reconnected.
8.4.6 Charger Modes
Figure 14. Charger Modes
8.4.7 Parameter
VDD27=2.7, TA= 25ºC, unless otherwise specified. Table 8. Charger Parameter
9 Detailed Description - SYSTEM Functions
9.1 SYSTEM
The system block handles the power up, power down and regulator voltage settings of the PMU.
9.1.1 Power Up/Down Conditions
9.1.2 Start-up Sequence
The start-up sequence is defined in the boot ROM and will be fixed during the production test. VDD27 will always start-up, after a ~5ms delay the sequencer will start-up the other chosen regulators with either 0, 1 or 4ms delay each. A maximum of 6 regulators (no matter of DCDC or LDO) or 5 regulators and a changed GPIO configuration can be chosen for the start-up. PWRGOOD will be activated ~3ms after the last regulator. XRES will be released 10ms to 110ms (set in the boot ROM) after the last regulator started up. Table 9. Power UP Conditions
1 PWRUP PwUp ON_KEY High Level at PWRUP pin of >= 1/3 VBATSW
Table 10. Power DOWN Conditions
1 SERIF MAJOR PwDn Power-Down by SERIF writing 0h to register 20h
2 Emergency PwDn Power-Down if PWRUP pin is HIGH for 8sec. This has to be enabled in register 21h, per default a reset cycle is initiated. It can also be changed to 4s. Power-Down if no SERIF read is seen for 500ms.
4 Junction-Temp PwDn
Power-Down if junction temperature rises up to 140degC. This threshold can be lowered with bits <4:0> in reg 21h. This supervisor can be disabled with bit 2 in reg. 20h. 5 VDD27 LOW PwDn Power-Down if VDD27 LDO5 has 10% under-voltage for more than 680µs. This supervisor can get disabled with bit 6 in reg. 21h. CVDD1 DCDC has 10% under-voltage for more than 680µs. CVDD2 DCDC has 10% under-voltage for more than 680µs. CVDD3 DCDC has 10% under-voltage for more than 680µs.
9 VSUP LOW PwDn Power-Down if VSUPx goes below the defined level in Reg22h (bits <3:1>)
This supervisor has to be enabled with bit 4 in reg. 22h.
9.2 Hibernation
interrupt has to be enabled before going to hibernation.
9.3 Supervisor
This supervisor function can be used for automatic detection of VSUP brown out or junction over-temperature condition.
9.3.1 VSUP Supervision
The VSUP supervision has a selectable level. If the shutdown is not enabled an interrupt can be generated.
9.3.2 VDD27 Supervision
9.3.3 Junction Temperature Supervision
The temperature supervision level can also be set by 5 bits (120 to –15ºC). If the temperature reaches this level, an interrupt can be generated. The over-temperature shutdown level is always 20ºC higher. This shutdown can be disabled in Reg. 20h.
9.3.4 Power Rail Monitoring
programmed value for more than 3ms. Table 11. Hibernation
- Enable just these IRQ sources which should lead to leave hibernation mode.
- Make sure that IRQ is inactive (IRQ flags get cleared by Reg 23h-26h readings.
- Drive the selected GPIO to LOW.
are part of the power-up sequence.
- Enable just these IRQ sources which should lead to leave hibernation mode.
- Make sure that IRQ is inactive (IRQ flags get cleared by Reg 23h-26h readings.
are part of the power-up sequence. Start-Up sequence is provided defined by the boot ROM.
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9.4 Interrupt Generation
All interrupt sources can get enabled or disabled by corresponding bits in the 4 IRQ-bytes. By default no interrupt source is enabled. The XIRQ pin can be configured to operate in push/pull (2 different driver strengths), open-drain mode or to be tri-state. The signal polarity can be defined as active-low or active-high. Default state is open-drain active-low.
9.4.1 IRQ Source Interpretation
There are 3 different modules to process interrupt sources: LEVEL. The IRQ output is kept active as long as the interrupt source is present and this IRQ-Bit is enabled. EDGE. The IRQ gets active with a high going edge of this source. The IRQ stays active until the corresponding IRQ-Register gets read. STATUS CHANGE. The IRQ gets active when the source-state changes. The change bit and the status can be read to notice which interrupt was the source. The IRQ stays active until the corresponding interrupt register gets read.De-bouncer There is a de-bounce function implemented, a de-bounce time of 3ms is selected per default in the IRQ_ENRD_3 register (26h).
9.4.2 Interrupt Sources
These IRQ events will activate the XIRQ pin: 10bit ADC end of conversion Charger end of charge, connect/disconnect, no battery Battery temperature high (at 45ºC or 50ºC with 100/10kΩ NTC) Junction temperature high Battery low (Brown-out voltage reached) Power-up key (pin PWRUP) pressed Current sink low voltage Power rail monitor: over-voltage CVDD1, CVDD2, CVDD3 Power rail monitor: under-voltage CVDD1, CVDD2, CVDD3, VDD27 ams AG Technical content still valid
supervision, button press detection, etc.
9.5.1 Input Sources
9.5.2 Parameter
VDD27=2.7, TA= 25ºC, unless otherwise specified. Table 12. ADC10 Input Sources Table 13. ADC10 Parameter
9.6 GPIO Pins
AS3607 features 4 GPIO pins, AS3606 has 2 GPIO pins. the different input/output options. GPIO pins have a 200kOhm pull-down resistor activated when they are used as an input. (HiZ-mode). Table 14. GPIO Configuration
11 PWRGOOD xCharging (1Hz pulses) xEOC / xCharger_active
Table 15. GPIO Output Functions xCharger_active The output will be high when the charger is no active or in EOC; it will be low if the charger is active. xEOC The output will be high when the charger active; it will be low if the charger is has reached EOC. The output will return back to high if the charger enters resume state. xPWRUP The output will get low if the PWRUP pin is high. will be high as long as the GPIOs are default inputs. xVSUP_low The output will get low if the VSUP undervoltage level is reached. HIGH The output will be high.
There is an I2C slave block implemented to have access to 64 byte of setting information.
9.7.1 Protocol
Figure 15. Byte Write Table 16. 2-Wire Serial Symbol Definition
9.7.2 Parameter
Figure 20. 2-Wire Serial Timing DVDD =2.9V, Tamb=25ºC, unless otherwise specified. Table 17. 2-Wire Serial Parameter
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10 Register Definition
T able 18. I2C Register Overview Addr Name b7 b6 b5 b4 b3 b2 b1 b0 PMU Register 17h-1 CVDD1 CVDD1_fast 0: Cext=10µF 1: Cext=22µF VSEL_CVDD1<6:0> 0 … OFF 0x01 – 0x40: 0.6V + VSEL * 12.5mV -> (0.6125V – 1.400V) 17h-2 CVDD2 CVDD2_fast 0: Cext=10µF 1: Cext=22µF VSEL_CVDD2<6:0> 0 … OFF 0x01 – 0x40: 0.6V + VSEL * 12.5mV -> (0.6125V – 1.400V) 17h-3 CVDD3 CVDD3_fast 0: Cext=10µF 1: Cext=22µF VSEL_CVDD3<6:0> 0 … OFF 0x01 – 0x40: 0.6V + VSEL * 12.5mV -> (0.6125V – 1.400V) 17h-4 Hibernation - KEEP_PVDD4 KEEP_PVDD3 KEEP_PVDD2 KEEP_PVDD1 KEEP_CVDD3 KEEP_CVDD2 KEEP_CVDD1 17h-5 DCDC_Cntr CFM_CVDD23_OF F 0: pulse skip on 1: pulse skip off CFM_CVDD1_OFF 0: pulse skip on 1: pulse skip off CVDD23_FREQ 0: 2MHz 1: 1MHz CVDD1_FREQ 0: 2MHz 1: 1MHz DVM_CVDD23<1:0> 0: immediate; 1: 42µs/step; 2: 166µs/step; 3: 666µs/step DVM_CVDD1<1:0> 0: immediate; 1: 42µs/step; 2: 166µs/step; 3: 666µs/step 17h-7 GPIO_Cntr MUX_GPIO43<1:0> 0: HiZ/HiZ; 1: xVSUP_low/xCharging; 2: xPWRUP/PWRGOOD; 3: xEOC/xCharger_active DRIVE_GPIO2 0: opend drain 1: HiZ MUX_GPIO2<1:0> 0: LOW; 1: xVSUP_low; 2: HIGH; 3: xCharging DRIVE_GPIO1 0: HiZ 1: opend drain MUX_GPIO1<1:0> 0: xCharging; 1: xVSUP_low; 2: xPWRUP; 3: PWRGOOD 18h-1 PVDD1 PVDD1_ON ILIM_H_PVDD1 0: 150mA 1: 250mA LP_PVDD1 0: normal mode 1: low power mode VSEL_PVDD1<4:0> 0x00 – 0x0F: 1.2V + VSEL * 50mV → (1.2V – 1.95V) 18h-2 PVDD2 PVDD2_ON ILIM_H_PVDD2 0: 150mA 1: 250mA LP_PVDD2 0: normal mode 1: low power mode VSEL_PVDD2<4:0> 0x00 – 0x0F: 1.2V + VSEL * 50mV → (1.2V – 1.95V) 18h-3 PVDD3 PVDD3_ON ILIM_H_PVDD3 0: 150mA 1: 250mA LP_PVDD3 0: normal mode 1: low power mode VSEL_PVDD3<4:0> 0x00 – 0x0F: 1.2V + VSEL * 50mV → (1.2V – 1.95V) ams AG Technical content still valid
www.austriamicrosystems.com Revision 1.03 36 - 70 AS3606 AS3607 2v2 Data Sheet - Register Definition 18h-4 PVDD4 PVDD4_ON ILIM_H_PVDD4 0: 150mA 1: 250mA LP_PVDD4 0: normal mode 1: low power mode VSEL_PVDD4<4:0> 0x00 – 0x0F: 1.2V + VSEL * 50mV → (1.2V – 1.95V) 18h-5 VDD27 PRG_VDD27 0: boot ROM 1:register defined ILIM_H_VDD27 0: 100mA 1: 200mA LP_VDD27 - VSEL_VDD27<3:0> 0x0 – 0x2: 2.3V 0x3 – 0xF: 2.0V + VSEL* 100mV → (2.3V – 3.5V) 19h-0 CHG_Cntr BAT_DET_OFF AUTO_R ESUME BAT_CHARGE_ON USB_CURRLIM <3:0> 0: 94mA; 1: 141mA; 2: 189mA; 3: 237mA; 4: 285mA; 5: 332mA; 6: 380mA; 7: 428mA; 8: 470mA; 9: 517mA; A: 599mA; B: 760mA; C: 882mA; D: 1060mA; E-F: not defined USB_PREREG_ON 19h-1 CHG_VCntr CHG_V_RESUME <2:0> VSUP_MIN<1:0> 0: 3.9V; 1: 3.6V; 2: 4.2V; 3: 4.5V CHG_V_EOC <2:0> 19h-2 CHG_ICntr CHG_I_CONSTANT <3:0> 0: 94mA; 1: 141mA; 2: 189mA; 3: 237mA; 4: 285mA; 5: 332mA; 6: 380mA; 7: 428mA; 8: 470mA; 9: 517mA; A: 599mA; B: 760mA; C: 882mA; D: 1060mA; E-F: not defined CHG_I_TRICKLE <3:0> 0: 25mA; 1: 35mA; 2: 47mA; 3: 59mA; 4: 71mA; 5: 83mA; 6: 95mA; 7: 107mA; 8: 118mA; 9: 129mA; A: 150mA; B: 190mA; C: 221mA; D: 265mA; E-F: not defined 19h-3 CHG_Conf - CHG_I_EOC<1:0> 0: 8%; 1: 15%; 2: 10%; 3: 20% VSUP_EOC <2:0> 19h-4 CHG_NTC - NTC_MODE 0: 55°C; 1: 45°C NTC_10K 0: 100k; 1: 10K; NTC_ON 19h-5 CHG_TIME - TMAX_TIMER CHG_TIMEOUT <3:0> 19h-6 CHG_STAT1 NO_BAT BATTEMP_HIGH EOC CV TRICKLE RESUME CC CHG_DET 19h-7 CHG_STAT2 - BATSW_MODE <1:0> 1Ah-1 Out_Cntr DCDC23_1.4A GPIO_HBN_ON HBN_DELAY<1:0> 0: 0ms; 1: 8ms; 2: 16ms; 3: 32ms DRIVE_XIRQ<1:0> 0: 6mA OD; 1: 6mA PP; 2: 1mA PP; 3: HiZ MUX_XIRQ<1:0> 0: XIRQ; 1: CLKINT1; 2: CLKINT2; 3: IRQ 1Ah-2 Clk_Cntr CLKINT2<1:0> 0: LOW; 1: CLK1Hz (charger); 2: do not use; 3: HIGH CLKINT1<1:0> 0: 2MHz; 1: 1MHz; 2: 1kHz; 3: 125Hz 0: LOW; 1: GPIO1; 2: GPIO2; 3: GPIO3 1Bh-1 Boost_Cntr1 SU_ON - SU_SLOWDIM 0: tbd 1: tbd SU_EXTDIM<1:0> 0: no dimm; 1: CURR1; 2: CURR2; 3: GPIO1/2/3 SU_OVP_OFF SU_CURR_FB SU_FASTSKIP 1Bh-2 Boost_Cntr2 SU_IFB<4:0> 0x00 - 0x1F: 1µA * SU_IFB; SU_CURRLIM SU_GAIN SU_FREQ T able 18. I2C Register Overview Addr Name b7 b6 b5 b4 b3 b2 b1 b0 ams AG Technical content still valid
www.austriamicrosystems.com Revision 1.03 37 - 70 AS3606 AS3607 2v2 Data Sheet - Register Definition 1Bh-3 CURR1 ICURR1<7:0> 0x00 - 0xFF: 150µA * ICURR; 1Bh-4 CURR2 ICURR2<7:0> 0x00 - 0xFF: 150µA * ICURR; 1Ch PMU_Enable DC_TEST_MUX <3:0> 0: open; 1: PVDD1; 2: PVDD2; 3: PVDD3; 4: PVDD4; 5: VDD27; 6: CVDD1; 7: CVDD2; 8: CVDD3; 9-F: not defined PMU_GATE PMU_ENABLE <2:0> SubRegister addresses for registers: 0x17: DCDC regulators 0x18: LDOs regulators 0x19: Charger 0x1A: IO_clock_control 0x1B: BackLight_DCDC System Register 20h SYSTEM Design_Version<3:0> - JTEMP_SUP_OFF I2C _WD_ON PWR_HOLD 21h SUPERVISOR1 PWRUP_SD_XRES <1:0> 0: XRES; 1: -; 2: SD; 3: SD SD_XRES_TIME 0: 8s; 1: 4s JTEMP_SUP<4:0> Temp_ShutDown = 140ºC - JTEMP_SUP*5ºC → (140ºC...5ºC) Temp_IRQ = 120ºC - JTEMP_SUP*5ºC → (120ºC...-15ºC) 22h SUPERVISOR2 - - VDD27low_SD_OF F VSUPlow_SD_ON VSUPlow_SUP <2:0> VSUPlow_SUP_OFF 23h IRQENRD_0 CVDD1_SD CVDD1_IRQ CVDD2_SD CVDD2_IRQ CVDD3_SD CVDD3_IRQ - CVDD1_under CVDD1_over CVDD2_under CVDD2_over CVDD3_under CVDD3_over - 24h IRQENRD_1 PWRUP_IRQ GPIO1_IRQ GPIO2_IRQ GPIO3_IRQ GPIO4_IRQ 25h IRQENRD_2 CHG_TEMP_IRQ CHG_EOC_IRQ CHG_NoBAT_IRQ CHG_DE T_IRQ - ICURR_LV_IRQ VSUP_LOW_IRQ VDD27_LOW_IRQ CHG_TEMP CHG_EOC CHG_NoBat CHG_DET 26h IRQENRD_3 T_DEB<1:0> 0: 3ms; 1: off; JTEMP_HIGH - ADC_EOC 2Eh ADC10_0 ADC10_MUX<3:0> 0: VSUP; 1: GPIO3; 2: GPIO4; 3: VSUPSW; 4: VUSB 5: DC_TEST; 6: BATTEMP; 7: GPIO1; 8: GPIO2; 9: PWRUP; A,B: -; C: VBE_1µA; D: VBE_2µA; E,F: - --ADC10<9:8> 2Fh ADC10_1 ADC10<7:0> T able 18. I2C Register Overview Addr Name b7 b6 b5 b4 b3 b2 b1 b0 ams AG Technical content still valid
Table 19. CVDD1 Register This is an extended register and needs to be enabled by writing 001b to Reg. 1Ch first. This register is reset at a VDD27-POR or XRES input. 7 CVDD1_fast 0 R/W Selects a faster regulation mode for CVDD1 suitable for larger load changes. Table 20. CVDD2 Register This is an extended register and needs to be enabled by writing 010b to Reg. 1Ch first. This register is reset at a VDD27-POR or XRES input. 7 CVDD2_fast 0 R/W Selects a faster regulation mode for CVDD2 suitable for larger load changes.
Table 21. CVDD3 Register This is an extended register and needs to be enabled by writing 011b to Reg. 1Ch first. This register is reset at a VDD27-POR or XRES input. 7 CVDD3_fast 0 R/W Selects a faster regulation mode for CVDD3 suitable for larger load changes. Table 22. Hibernation Register Hibernation starts when writing this register, except hibernation via GPIO is selected. This is an extended register and needs to be enabled by writing 100b to Reg. 1Ch first. 6 KEEP_PVDD4 0 W Keeps the programmed PVD D4 level during hibernation. 5 KEEP_PVDD3 0 W Keeps the programmed PVD D3 level during hibernation. 4 KEEP_PVDD2 0 W Keeps the programmed PVD D2 level during hibernation. 3 KEEP_PVDD1 0 W Keeps the programmed PVD D1 level during hibernation. 2 KEEP_CVDD3 0 W Keeps the programmed CVDD3 level during hibernation. 1 KEEP_CVDD2 0 W Keeps the programmed CVDD2 level during hibernation. 0 KEEP_CVDD1 0 W Keeps the programmed CVDD1 level during hibernation.
Table 23. DCDC_Cntr Register This is an extended register and needs to be enabled by writing 101b to Reg. 1Ch first. This register is reset at a VDD27-POR or XRES input.
7 CFM_CVDD23_OFF 0 R/W Disables pulse skip mode for DCDC2 and DCDC3
6 CFM_CVDD1_OFF 0 R/W Disables pulse skip mode for DCDC1
5 CVDD23_FREQ 0 R/W Selects the switch ing frequency for DCDC2 and DCDC 3
4 CVDD1_FREQ 0 R/W Selects the switching frequency for DCDC1
Table 24. GPIO_Cntr Register This is an extended register and needs to be enabled by writing 111b to Reg. 1Ch first. This register is reset at a VDD27-POR or XRES input.
5 DRIVE_GPIO2 0 R/W Configures GPIO2 as input or output
2 DRIVE_GPIO1 0 R/W Configures GPIO1 as input or output
Table 25. PVDD1 Register This is an extended register and needs to be enabled by writing 001b to Reg. 1Ch first. This register is reset at a VDD27-POR or XRES input.
7 PVDD1_ON 0 R/W Enables PVDD1 regulator
6 ILIM_H_PVDD1 0 R/W Selects the hi gher current limit for PVDD1
5 LP_PVDD1 0 R/W Selects the low power mode for PVDD1
Table 26. PVDD2 Register This is an extended register and needs to be enabled by writing 010b to Reg. 1Ch first. This register is reset at a VDD27-POR or XRES input.
7 PVDD2_ON 0 R/W Enables PVDD2 regulator
6 ILIM_H_PVDD2 0 R/W Selects the hi gher current limit for PVDD2
5 LP_PVDD2 0 R/W Selects the low power mode for PVDD2
Table 27. PVDD3 Register This is an extended register and needs to be enabled by writing 011b to Reg. 1Ch first. This register is reset at a VDD27-POR or XRES input.
7 PVDD3_ON 0 R/W Enables PVDD3 regulator
6 ILIM_H_PVDD3 0 R/W Selects the hi gher current limit for PVDD3
5 LP_PVDD3 0 R/W Selects the low power mode for PVDD3
Table 28. PVDD4 Register This is an extended register and needs to be enabled by writing 100b to Reg. 1Ch first. This register is reset at a VDD27-POR or XRES input.
7 PVDD4_ON 0 R/W Enables PVDD4 regulator
6 ILIM_H_PVDD4 0 R/W Selects the hi gher current limit for PVDD4
5 LP_PVDD4 0 R/W Selects the low power mode for PVDD4
Table 29. VDD27 Register This is an extended register and needs to be enabled by writing 101b to Reg. 1Ch first. This register is reset at a VDD27-POR or XRES input.
7 PRG_VDD27 0 n/a Selects the output voltage control mode for VDD27
6 ILIM_H_VDD27 0 R/W Selects the higher current limit for VDD27
5 LP_VDD27 0 R/W Selects the low power mode for VDD27
Table 30. CHG_Cntr Register This is an extended register but does not need to be enabled as Reg. 1Ch is 000b per default. This register is reset at a VDD27-POR or XRES input.
7 BAT_DET_OFF 1 R/W Disables the battery detection
6 AUTO_RESUME 1 R/W Defines the behavior after end of charge (EOC)
5 BAT_CHARGE_ON 0 R/W Enables the battery charging
1000 R/W Sets the USB pre-regulator current limit
0 USB_PREREG_ON 1 R/W Enables the USB pre-regulator and current limiter
Table 31. CHG_VCntr Register This is an extended register and needs to be enabled by writing 001b to Reg. 1Ch first. This register is reset at a VDD27-POR or XRES input.
001 R/W Sets the charger auto resume voltage threshold
110 R/W Sets the charger end of charge voltage threshold
Table 32. CHG_ICntr Register This is an extended register and needs to be enabled by writing 010b to Reg. 1Ch first. This register is reset at a VDD27-POR or XRES input.
0010 R/W Sets the current during constant current charging
0001 R/W Sets the current during constant current charging
Table 33. CHG_Config Register This is an extended register and needs to be enabled by writing 011b to Reg. 1Ch first. This register is reset at a VDD27-POR or XRES input. the current drops below the threshold. 101 R/W Defines VSUP voltage after EOC and isolated battery. Table 34. CHG_NTC Register This is an extended register and needs to be enabled by writing 100b to Reg. 1Ch first. This register is reset at a VDD27-POR or XRES input.
2 NTC_MODE 0 R/W Defines the temperature level for the battery temperature supervisor to stop
1 NTC_10K 0 R/W Defines the type of NTC used for battery temperature supervisor. 0 NTC_ON 1 R/W Enables the battery temperature supervisor via NTC resistor.
Table 35. CHG_TIME Register This is an extended register and needs to be enabled by writing 101b to Reg. 1Ch first. This register is reset at a VDD27-POR or XRES input.
4 TMAX_TIMER 0 R Returns the time-out supervision status
0111 R/W Sets the current during constant current charging
Table 36. CHG_STAT1 Register This is an extended register and needs to be enabled by writing 110b to Reg. 1Ch first. This register is reset at a VDD27-POR or XRES input.
7 NO_BAT x R Status if a battery is detected to the system, by measuring the NTC value on
6 BATTEMP_HIGH x R Only valid if a charger is deducted.
4 CV x R 1: if charger is in constant voltage (top-off charge) mode
3 TRICKLE x R 1: if charger is in trickle charging mode
2 RESUME x R 1: if VBATSW dropped below resume threshold
1 CC x R 1: if charger is in constant current charging mode
0 CHG_DET x R 1: if a charger adapter is detected on VUSB pin
Table 37. CHG_STAT2 Register This is an extended register and needs to be enabled by writing 111b to Reg. 1Ch first. This register is reset at a VDD27-POR or XRES input. This is an extended register and needs to be enabled by writing 110b to Reg. 1Ch first. This register is reset at a VDD27-POR or XRES input.
Table 38. Out_Cntr Register This is an extended register and needs to be enabled by writing 001b to Reg. 1Ch first. This register is reset at a VDD27-POR or XRES input.
6 GPIO_HBN_ON 0 R/W 0: Hibernation enable via GPIOs disabled
Table 39. Clk_Cntr Register This is an extended register and needs to be enabled by writing 010b to Reg. 1Ch first. This register is reset at a VDD27-POR or XRES input. be multiplexed to the XRES output.
00 R/W Selects input for external dimming or hibernation control
Table 40. BOOST_Cntr1 Register This is an extended register and needs to be enabled by writing 001b to Reg. 1Ch first. This register is reset at a VDD27-POR or XRES input.
7 SU_ON 0 R/W Enables the DCDC step-up regulator
5 SU_SLOWDIM 0 R/W Selects the DCDC step-up regulator external dimming mode
2 SU_OVP_OFF 0 R/W Disables the DCDC step-up over-voltage protection
1 SU_CURR_FB 0 R/W Selects the DCDC step-up feedback mode
0 SU_FASTSKIP 0 R/W Defines the DCDC step-up regulator output voltage at low loads, when pulse
This is an extended register and needs to be enabled by writing 010b to Reg. 1Ch first. This register is reset at a VDD27-POR or XRES input.
Table 41. BOOST_Cntr2 Register This is an extended register and needs to be enabled by writing 010b to Reg. 1Ch first. This register is reset at a VDD27-POR or XRES input. 7:3 SU_IFB<4:0> 0 0000 R/W Defines the tuning current at pin FBSU.
2 SU_CURRLIM 0 R/W Selects the DCDC step -up converter coil current limit
1 SU_GAIN 0 R/W DCDC step-up converter feedback gain is selected automatically depending
alternative feedback gain setting.
0 SU_FREQ 00 R/W Defines the DCDC step-up switching frequency
Table 42. CURR1 Register This is an extended register and needs to be enabled by writing 011b to Reg. 1Ch first. This register is reset at a VDD27-POR or XRES input.
Table 43. CURR2 Register This is an extended register and needs to be enabled by writing 100b to Reg. 1Ch first. This register is reset at a VDD27-POR or XRES input. Table 44. PMU_Enable Register This register is reset at a VDD27-POR or XRES input.
0000 R/W Allows multiplexing internal and external supply voltages to one DC test
changes are activated as soon as they are written to the related register. has to be set before every read or write even if the selection is not changing.
Table 45. SYSTEM Register This register is reset at a VDD27-POR or XRES input.
2 JTEMP_SUP_OFF 0 R/W Junction temperature supervision (level can be set in register 21h)
1 I2C_WD_ON 0 R/W 2-wire serial interface watchdog
0 PWR_HOLD 1 R/W 0: power up hold is cleared and PMU will power down
Table 46. SUPERVISOR1 Register This register is reset at a VDD27-POR or XRES input.
00 R/W Applying a high signal on PWRUP pin for about 8s will
5 SD_XRES_TIME 0 R/W Halfs the time from pulling PWRUP high to XRES or SD
Table 47. SUPERVISOR2 Register This register is reset at a VDD27-POR or XRES input.
5 VDD27low_SD_OFF 0 R/W 0: VDD27low (VDD27 -10%) shut down enabled
4 VSUPlow_SD_ON 0 R/W 0: VSUPlow shut down enabled
0 VSUPlow_SUP_OFF 0 R/W 0: VSUPlow supervision enabled
Table 48. First Interrupt Register reset at a VDD27-POR or XRES input.
7 CVDD1_SD 0 W Invokes shut-down of the PMU when a –10% under-voltage spike at CVDD1
6 CVDD1_IRQ 0 W Enables interrupt for over-voltage/under-voltage supervision of CVDD1
5 CVDD2_SD 0 W Invokes shut-down of the PMU when a –10% under-voltage spike at CVDD2
4 CVDD2_IRQ 0 W Enables interrupt for over-voltage/under-voltage supervision of CVDD2
3 CVDD3_SD 0 W Invokes shut-down of the PMU when a –10% under-voltage spike at CVDD3
2 CVDD3_IRQ 0 W Enables interrupt for over-voltage/under-voltage supervision of CVDD3
Table 49. Second Interrupt Register reset at a VDD27-POR or XRES input.
7 PWRUP_IRQ 0 W Enables interrupt which is invoked whenever a high signal at the PWRUP
6 GPIO1_IRQ 0 W Enables interrupt which is invoked whenever a high signal at the GPIO1
5 GPIO2_IRQ 0 W Enables interrupt which is invoked whenever a high signal at the GPIO2
4 GPIO3_IRQ 0 W Enables interrupt which is invoked whenever a high signal at the GPIO3
3 GPIO4_IRQ 0 W Enables interrupt which is invoked whenever a high signal at the GPIO4
Table 50. Third Interrupt Register reset at a VDD27-POR or XRES input.
7 CHG_TEMP_IRQ
0 W Battery over-temperature interrupt setting
6 CHG_EOC_IRQ
0 W Charger end of charge interrupt setting. current, charger was turned off.
5 CHG_NoBAT_IRQ
0 W Charger no battery interrupt setting
4 CHG_DET_IRQ
0 W Charger detect interrupt setting.
2 ICURR_LV_IRQ
0 W Current sink undervoltage interrupt setting.
1 VSUP_LOW_IRQ
0 W VSUP under-voltage supervisor interrupt setting
register (22h). If the shutdown is enabled the interrupt will not occur.
0 VDD27_LOW_IRQ
0 W VDD27 undervoltage supervisor interrupt setting
1: VDD27 has reached threshold level (VDD27-10%). If the shutdown is enabled the interrupt will not occur. reset at a VDD27-POR or XRES input.
Table 51. Fourth Interrupt Register reset at a VDD27-POR or XRES input.
5 T_DEB<1:0> 0 R/W Sets the de-bounce time all interrupt inputs:
0 W Supervisor junction over-temperature interrupt setting
0 W ADC end of conversion interrupt setting
Table 52. ADC10_0 Register Writing to this register will start the measurement of the selected source. Table 53. ADC10_1 Register This register is reset at a VDD27-POR.
11.1 Pad Cells
Figure 21. Pad Cells Equivalant Circuit
11.2 Application Schematics
Figure 22. Typical AS3606 Application Schematic
Figure 23. Typical AS3607 Application Schematic
Figure 24. AS3606 QFN32, 0.5mm Pitch
Figure 25. AS3607 QFN36, 0.5mm Pitch
Figure 26. QFN Marking Table 54. Package Code YYWWZZZ Table 55. Start-up Revision Code
www.austriamicrosystems.com Revision 1.03 68 - 70 AS3606 AS3607 2v2 Data Sheet - Revision History
Revision History
Note: Typos may not be explicitly mentioned under revision history. Revision Date Owner Description 1.00 7.2010 pkm first official release 1.01 9.2010 pkm corrected GPIO2 bit description & GPIO hibernation description updated package drawings 1.02 11.2010 pkm corrected charger block diagram, updated package drawings 1.03 3.2011 pkm added NTC supply description, added USB rising edge specification ams AG Technical content still valid
The devices are available as the standard products shown in Table 56. Note: All products are RoHS compliant and austriamicrosystems green. Table 56. Ordering Information
www.austriamicrosystems.com Revision 1.03 70 - 70 AS3606 AS3607 2v2 Data Sheet - Copyright Copyright Copyright © 1997-2010, austriamicrosystems AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies. Disclaimer Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services. Contact Information Headquarters austriamicrosystems AG Tobelbaderstrasse 30 A-8141 Unterpremstaetten, Austria Tel: +43 (0) 3136 500 0 Fax: +43 (0) 3136 525 01 For Sales Offices, Distributors and Representatives, please visit: http://www.austriamicrosystems.com/contact ams AG Technical content still valid