AS3421 AMSCO | Alldatasheet
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Low P ower Am bient No ise-Can cell ing Speaker Dri ver www.austriamicrosystems.com Revision 0.90 1 O 61 Datasheet
1 General Description
The AS3421/22 are speaker driver with Ambient Noise Cancelling function for headsets, headphones or ear pieces. It is intended to improve quality of e.g. music listening, a phone conversation etc. by reducing background ambient noise. The fully analog implementation allows the lowest power consumption, lowest system BOM cost and most natural received voice enhancement otherwise difficult to achieve with DSP implementations. The device is designed to be easily applied to existing architectures. An internal OTPOROM can be optionally used to store the microphone gain calibration settings as well as all application specific settings. The AS3421/22 can be used in different configurations for best tradeOoff of noise cancellation, required filtering functions and mechanical designs. The simpler feedOforward topology is used to effectively reduce frequencies typically up to 2O3kHz. The feedOback topology with either 1 or 2 filtering stages has it strengths especially at very low frequencies. The typical bandwidth for feedback system is from 20Hz up to 1kHz which is a little bit lower than with feed forward systems. The filter loop for both systems is determined by measurements, for each specific headset individually, and depends very much on mechanical designs. The gain and phase compensation filter network is implemented with cheap resistors and capacitors for lowest system costs. AS3421/22 features also an audio playback only mode which allows the user to easily switch between ANC on and off mode. In ANC off mode unused blocks are automatically switch off to guaranty lowest power consumption in each operating mode.
2 Key Features
/square6 128 gain steps @ 0.375dB and MUTE with AGC /square6 Differential, low noise microphone amplifier /square6 Single ended or differential mode /square6 Improved supply for electret microphone /square6 MIC gain OTP programmable High Efficiency Headphone Amplifier /square6 2x23mW, 0.1% THD+N @ 32 Ω , 1.5V supply, 100dB SNR /square6 Bridged mode for e.g. 300 Ω loads /square6 Click and pop less startOup and mode switching Line Input /square6 Volume control via serial interface or push buttons /square6 64 steps @ 0.75dB and MUTE, popOfree gain setting /square6 Fully differential stereo line inputs ANC processing /square6 FeedOforward cancellation /square6 FeedOback cancellation with filter loop transfer function definable via simple RC components /square6 Simple in production SW calibration /square6 12O30dB noise reduction (headset dependent) /square6 10O3000Hz wide frequency active noise attenuation (headset dependent) Monitor Function /square6 For assisted hearing, i.e. to monitor announcements /square6 Fixed (OTP prog.) ambient sound amplification to compensate headphone passive attenuation Incremental Functions /square6 ANC with or without music on the receiving path /square6 Music Playback mode for lowest power consumption /square6 OTP ROM for automatic trimming during production (4 times programmable) Performance Parameter /square6 7mA @ 1.5V stereo ANC; <1µA quiescent /square6 Extended PSRR for 217Hz /square6 Increased TDMA noise immunity Interfaces /square6 2Owire serial control mode & volume inputs /square6 Calibration via LineOIn or 2Owire serial interface /square6 Fixed 1.0O1.8V supply with internal CP Package /square6 AS3421 QFN24 [4x4mm] 0.5mm pitch /square6 AS3422 QFN32 [5x5mm] 0.5mm pitch
3 Applications
The devices are ideal for wireless devices like stereo Bluetooth headsets as well as stereo wireless headsets.
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4 Contents
5 Pin Assignments
Note: Pin assignment may change in preliminary data sheets. Figure 3. Pin Assignments (Top View)
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5.1 Pin Descriptions
Note: Pin description may change in preliminary data sheets. T able 1. Pin Description for AS3421 AS3422 Pin Name Pin Number Type Description AS3421 AS3422 IOP1L 24 1 ANA IN Filter OpAmp1 Input Left Channel QLINL 2 ANA OUT Line In Gain Stage Output Left Channel QMICL 1 3 ANA OUT MIC GainS tage Output Right Channel AGND 2 4 ANA IN Analog Reference LINL_N 3 5 ANA IN Negative Line In pin of Left Channel LINL_P 4 6 ANA IN Positive Line In pin of Left Channel LINR_P 5 7 ANA IN Positive Line In pin of Right Channel LINR_N 6 8 ANA IN Negative Line In pin of Right Channel ANC_CSDA 7 9 MIXED IO Serial Interface Data ANC Pin (Enable/Disable ANC function) MODE_CSCL 8 10 DIG IN Mode Pin (Power Up/Down, Monitor) Serial Interface Clock MICL 9 11 ANA IN Microphone In Left Channel MICS 10 12 ANA OUT Microphone Supply MICR 11 13 ANA IN Microphone Input Right Channel QMICR 12 14 ANA OUT MIC Gain Stage Output Right Channel QLINR 15 ANA OUT Line In Gain Stage Output Right Channel IOP1R 13 16 ANA IN FilterOpAmp1 Input Right Channel QOP1R 14 17 ANA IN Filter OpAmp1 Output Right Channel IOP2R 18 ANA IN Filter OpAmp2 Input Right Channel QOP2R 19 ANA OUT Filter OpAmp2 Output Right Channel VSS 20 SUP IN VSS supply terminal HPL 15 21 ANA OUT Headphone Output Left Channel HPVSS 22 SUP IN Headphone amplifier VSS supply terminal HPR 16 23 ANA OUT Headphone Output Right Channel HPVDD 17 24 SUP IN Headphone VDD Supply VBAT 18 25 SUP IN Positive supply terminal of IC CPP 19 26 ANA OUT VNEG ChargePump Flying Capacitor Positive Terminal GND 20 27 GND VNEG ChargePump Negative Supply CPN 21 28 ANA OUT VNEG ChargePump Flying Capacitor Negative Terminal VNEG 22 29 SUP IO VNEG ChargePump Output QOP2L 30 ANA OUT Filter OpAmp2 Output Left Channel IOP2L 31 ANA IN Filter OpAmp2 Input Left Channel QOP1L 23 32 ANA OUT Filter OpAmp1 Output Right Channel VNEG 25 33 SUP IN Exposed Pad: connect to VNEG or leave it unconnected
www.austriamicrosystems.com Revision 0.90 6 O 61 AS3421 AS3422 Datasheet O Absolute Maximum Ratings
6 Absolute Maximum Ratings
Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in Electrical Characteristics on page 7 is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The device should be operated under recommended operating conditions. T able 2. Absolute Maximum Ratings Parameter Min Max Units Comments Reference Ground Defined as in GND Supply terminals O0.5 2.0 V Applicable for pin VBAT, HPVDD Ground terminals O0.5 0.5 V Applicable for pins AGND Negative terminals O2.0 0.5 V Applicable for pins VNEG, VSS, HPVSS Voltage difference at VSS terminals O0.5 0.5 V Applicable for pins VSS, HPVSS Pins with protection to VBAT VNEG O0.5 5.0 VBAT+0.5 V Applicable for pins CPP, CPN Pins with protection to HPVDD VSS O0.5 5.0 HPVDD+0.5 V Applicable for pins LINL_P/N, LINR_P/N, MICL/ R, HPR, HPL, QMICL/R, QLINL/R, IOPx, QOPx other pins VSS O0.5 5 Applicable for pins MICS, ANC_CSDA, MODE_CSCL Input Current (latchOup immunity) O100 100 mA Norm: JEDEC 17 Continuous Power Dissipation (T A = +70ºC) Continuous Power Dissipation O 200 mW PT1 for QFN16/24/32 package 1. Depending on actual PCB layout and PCB used Electrostatic Discharge Electrostatic Discharge HBM +/O2 kV Norm: JEDEC JESD22OA114C Temperature Ranges and Storage Conditions Junction Temperature +110 ºC Storage Temperature Range O55 +125 ºC Humidity nonOcondensing 5 85 % Moisture Sensitive Level 3 Represents a max. floor life time of 168h Package Body Temperature 260 ºC The reflow peak soldering temperature (body temperature) specified is in accordance with IPC/ JEDEC J-STD-020“Moisture/Reflow Sensitivity Classification for Non-Hermetic Solid State Surface Mount Devices”.
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7 Electrical Characteristics
The parameters with min and max values are guaranteed with production tests or SQC (Statistical Quality Control) methods. T able 3. Electrical Characteristics Symbol Parameter Condition Min Max Unit TA Ambient Temperature Range O20 +85 °C Supply Voltages GND Reference Ground 0 0 V VBAT, HPVDD Battery Supply Voltage normal operation with MODE pin high 1.0 1.8 V Two wire interface operation 1.4 1.8 V VNEG ChargePump Voltage O1.8 O0.7 V VSS Analog neg. Supply Voltages HPVSS, VSS, VNEG O1.8 O0.7 V VDELTA O Difference of Ground Supplies GND, AGND To achieve good performance, the negative supply terminals should be connected to low impedance ground plane. O0.1 0.1 V VDELTA OO Difference of Negative Supplies VSS, VNEG, HPVSS Charge pump output or external supply O0.1 0.1 V VDELTA + Difference of Positive Supplies VBATOHPVDD O0.25 0.25 V Other pins VMICS Microphone Supply Voltage MICS 0 3.6 V VHPVDD Pins with diode to HPVDD MICL/R, HPR, HPL, QMICL/R, QLINL/R, IOPx, QOPx VSS 3.6 V VVBAT Pins with diode to VBAT CPP, CPN VNEG VBAT V VCONTROL Control Pins MODE_CSCL, ANC_CSDA VSS 3.7 V VTRIM Line Input & Application Trim Pins LINL_P, LINL_N, LINR_P, LINR_N VNEG O0.5 or O1.8 HPVDD +0.5 or 1.8 V Symbol Parameter Condition Min Typ Max Unit Ileak Leakage current VBAT<0.8V 20 µA VBAT<0.6V 10 µA Block Power Requirements @ 1.5V VBAT IOFF Off mode current MODE pin low, device switched off 1 µA ISYS Reference supply current Bias generation, oscillator, ADC6, VNEG 0.25 mA ILIN LineIn gain stage current no signal, stereo 0.5 mA IMIC Mic gain stage current no signal, stereo 2.10 mA IHP Headphone stage current no signal 1.70 mA IMICS MICS charge pump current no load 30 µA IMIN Minimal supply current Sum of all above blocks 4.6 mA IOP1 OP1 supply current no load 0.64 mA IOP2 OP2 supply current no load 0.64 mA
www.austriamicrosystems.com Revision 0.90 8 O 61 AS3421 AS3422 Datasheet O Electrical Characteristics IMICB Microphone bias current 200µA per microphone via charge pump 0.9 mA IPB Low Power Playback Mode VBAT = 1.8V 2,8 mA VBAT = 1.5V 2,5 mA VBAT = 1.0V 2 mA Symbol Parameter Condition Min Typ Max Unit
8 Typical Operating Characteristics
Figure 4. THD+N vs. Pout; Line to HPH; 16 Ω single ended stereo Figure 5. THD+N vs. Pout; L ine to HPH; 32 Ω single ended stereo Figure 6. THD+N vs. f; Line to HPH; 1mW load per c hannel Figure 7. THD+N vs. f; Line to HPH; 10mW lo ad per channel
16 Ohm
32 Ohm
Figure 8. THD+N vs. f; 20mW and 30mW per channel F igure 9. Frequency Response 30mW@16 Ω ; Line to HPH
9 Detailed Description
This section provides a detailed description of the device related components.
9.1 Audio Line Input
The chip features one line input. The blocks can work in mono differential or in stereo single ended mode. eventually given input capacitors.
9.1.1 Gain Stage
noise in this special mode the internal state machine support very smooth gain fading to avoid unwanted acoustic effects. Figure 17. Fully Differential Stereo Line Inputs
9.1.2 Parameter
VBAT=1.5V, T A= 25ºC, unless otherwise specified.
9.2 Microphone Input
Figure 18. Microphone Input
9.2.1 Gain Stage & Limiter
The Mic Gain Stage has programmable Gain within O11.25dB…+36dB in 128 steps of 0.375dB. design it is necessary to switch of the AGC functionality. This can be done in register 0x17 by setting bit ‘1’. In monitor mode, the gain stage can be set to an fixed (normally higher) gain level or be controlled by the VOL pin.
9.2.2 Microphone Supply
supports basically 3 different modes. enough to operate a microphone properly. This mode is more commonly used in devices with a fixed power supply like in Bluetooth headsets. supply. Please mind that the sensitivity of your microphone can be reduced in this mode.
www.austriamicrosystems.com Revision 0.90 14 O 61 AS3421 AS3422 Datasheet O Detailed Description The second mode, with the name CHAREGPUMP_MODE, is the most commonly used mode which is per default enabled. In this mode the internal charge pump is enabled. The charge pump doubles the supply voltage of AS3421/22 with a high output impedance of the charge pump in order to make external passive filters more effective. If doubling the supply voltage is not enough the microphone supply can be switched to a special regulated mode which increases the output voltage but with a little bit higher output noise. This setting can be found in register 0x35. The third mode is the OFF MODE. This mode allows the user to switch of the microphone supply if not needed (e.g. playback without ANC)
9.2.3 Parameter
VBAT=1.5V, T A= 25ºC unless otherwise specified. T able 5. Microphone Input Parameter Symbol Parameter Condition Min Typ Max Unit VMICIN 0 Input Signal Level AMIC = 24dB 40 mV P VMICIN 1 AMIC = 30dB 20 mV P VMICIN 2 AMIC = 36dB 10 mV P RMICIN Input Impedance MICP to AGND 7.5 k Ω ∆ MICIN Input Impedance Tolerance O7 +33 % CMICIN Input Capacitance 5 pF AMIC Programmable Gain O11.25 +36 dB Gain Steps Discrete logarithmic gain steps 0.375 dB Gain Step Precision 0.15 dB ∆ AMIC Gain Ramp Rate Tinit=64ms 4 ms/step VATTACK Limiter Activation Level VPEAK related to VBAT or VNEG 0.67 1 VDECAY Limiter Release Level 0.4 1 AMICLIMIT Limiter Gain Overdrive 127 @ 0.375dB 36 dB tATTACK Limiter Attack Time 5 µs/step tDECAYODEB Limiter Decay Debouncing Time 64 ms tDECAY Limiter Decay Time 4 ms/step VMICS Microphone Output Voltage no output load 2.7 V IMICS Microphone Supply Current no output load 30 µA ROUT_CP CP Output Resistance 400µA load 900 Ω IMIC_MIN Microphone Output Current Recommended minimum microphone output current @ Vbat = 1.5V 170 µA Recommended minimum microphone output current @ Vbat = 1.8V 300 µA IMIC_MAX Microphone Output Current Recommended maximum microphone output current @Vbat = 1.5V 500 µA Recommended maximum microphone output current @Vbat = 1.8V 700 µA
9.3 Headphone Output
mode the left output is carrying the inverted signal of the right output shown in Figure 20 . Figure 19. Headphone Output Single Ended Mode Figure 20. Headphone Output Differential Mode
9.3.1 Input Multiplexer
ANC by only using the lineOinput gain stage with no other signal on the multiplexer. For the monitor mode, the setting of this input multiplexer can be changed to another source, normally to the microphone.
9.3.2 No-Pop Function
The NoOPop startup of the headphone stage takes 60ms to 120ms dependent on the supply voltage.
9.3.3 No-Clip Function
The headphone output stage gets monitored by comparator stages which detect if the output signal starts to clip. signal with constant amplitude.
9.3.4 Over-Current Protection
9.3.5 Parameter
VBAT=1.5V, T A= 25ºC, unless otherwise specified.
9.4 Operational Amplifier
feedOback ANC or any other additional needed filtering. Figure 21. Operational Amplifiers
www.austriamicrosystems.com Revision 0.90 17 O 61 AS3421 AS3422 Datasheet O Detailed Description
9.4.1 Parameter
VBAT=1.5V, T A= 25ºC, unless otherwise specified. T able 7. Headphone Output Parameter Symbol Parameter Condition Min Typ Max Unit RL_OP Load Impedance Single ended 1 k Ω CL_OP Load Capacitance Single ended 100 pF GBW OP Gain Band Width 4.3 MHz VOS_OP Offset Voltage 6 mV VEIN_HP Equivalent Input Noise 200HzO20kHz 2.6 µV
9.5 SYSTEM
The system block handles the power up and power down sequencing, as well as, the mode switching.
9.5.1 Power Up/Down Conditions
9.5.2 Start-up Sequence
The startOup sequence depends on the used mode. bit. If only the PWR_HOLD is set all enable bits for headphone, microphone, etc have to be set manually. Figure 22. Stand-Alone Mode Start-Up Sequence
1 MODE_CSCL pin In standOalone mode, MODE pin has to be driven high to turn on the device
2 I2C start In I2C mode, a I2C start condition turns on the device
1 MODE pin Power down by driving MODE_CSCL pin to low
2 SERIF Power down by SERIF writing 0h to register 20h bit <0>
3 Low Battery Power down if VBAT is lower than the supervisor offOthreshold
4 VNEG CP OVC Power down if VNEG is higher than the VNEG offOthreshold
Figure 23. I2C Mode Start-Up Sequence The total startOup time (including fadeOin of the gain stages) can be reduced to 600ms by OTP setting.
9.5.3 MODE_CSCL Switching
When the chip is in standOalone mode (no I2C control), the mode can be switched with different levels on the MODE pin. In I2C mode, the monitor mode can be activated be setting the corresponding bit in the system register. multiplexer can be set to a different (normally to MIC) source.
9.5.4 ANC_CSDA Switching
can be entered by simply pulling the ANC_SCDA pin to low. Figure 24. ANC / CSDA Switching influence on the device any more.
9.6 VNEG Charge Pump
audio related blocks. This allows a trueOground headphone output with no more need of external dcOdecoupling capacitors.
9.6.1 Parameter
VBAT=1.5V, T A= 25ºC, unless otherwise specified.
9.7 OTP Memory & Internal Registers
making it possible to change the gain 3 times for reOcalibration or other purposes. memory of the BluetoothO or wireless chipset.
9.7.1 Register & OTP Memory Configuration
Figure 25 is showing the principal register interaction. Figure 25. Register Access OTP Register settings which are loaded from the OTP fuses at every startOup. a programmed bit from “1” to “0”, multiple OTP writes are possible, but only additional unprogrammed “0”Obits can be programmed to “1”. setting will be cleared and overwritten with the hard programmed OTP settings at each powerOup sequence or by a LOAD operation.
executed after each powerOonOreset. memory after a LOAD command. empty batteries for burning the fuses. Attention: If you once burn the OTP_LOCK bit, no further programming, e.g. setting additional “0” to “1”, of the OTP can be done. For production, the OTP_LOCK bit must be set to avoid an unwanted change of the OTP content during the lifetime of the product.
9.7.2 OTP Fuse Burning
environment for the trimming process. In Figure 26 a principal block diagram is shown for trimming the AS3421/22 properly in production. Figure 26. Block Diagram for Production Environmen t in the block diagram it is mandatory to get a voltage difference between VPOS and VNEG of min. 3.4V to guaranty proper trimming of the device. 1.7V. The charge pump switches then automatically into skip mode. charge pump especially during the trim process which can now be started.
Figure 27. Timing Diagram for V NEG Buffering have a couple of test bits inside which are per default set to ‘1’. We do not recommend overwriting these bytes. MAIN_LOCK bit and the ALTx_LOCK bits are not set correctly the result can be malfunction of the device. includes also some code examples.
Figure 28. OTP Burning Process There is an I2C slave block implemented to have access to 64 byte of setting information.
9.8.1 Protocol
9.8.2 Parameter
Figure 34. 2-Wire Serial Timing 1, T A=25ºC, unless otherwise specified.
- Serial interface operates down to VBAT = 1.0V but with 100kHz clock speed and degraded parameters.
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10 Register Description
T able 15. I2C Register Overview Addr Name b7 b6 b5 b4 b3 b2 b1 b0 Audio Registers 00O07h reserved 08h MIC_L MIC_MODE 0: StereoSingleEnd 1: MonoDiff MICL_VOL<6:0> 09h MIC_R MIC_REG_ON 0: use reg 30h & 31h 1: use reg 08h & 09h MICR_VOL<6:0> 0Ah LINE_IN LIN_REG_ON 0: use reg 33h and VOL pin 1: use reg 0Ah LIN_GAIN_+3dB 0: 0dB max. Line Gain 1: +3dB max. Line Gain LIN_VOL<5:0> 0: MUTE; 0Bh GP_OP_L HP_MUX<1:0> 0: MIC; 1: OP1; 2: OP2; 3: open OP2L<3:0> 0: OP2L inverting mode; OP2L_ON OP1L_ON 0Ch GP_OP_R OP_REG_ON 0: use reg 34h 1: use reg 0Bh & 0Ch HP_MODE 0: StereoSingleEnd 1: MonoDiff OP2R<3:0> 0: OP2R inverting mode; OP2R_ON OP1R_ON 0DhO0Fh reserved 18hO1Fh reserved System Register 20h SYSTEM Design_Version<3:0> 1001 REG3F_ON MONITOR_ON CONT_PWRUP PWR_HOLD 21h PWR_SET PWR_REG_ON 0: use reg 0x35 1: use reg 0x21h HP_ON MIC_ON LIN_ON MICS_CP_ON MICS_ON LOW_BAT PWRUP_ COMPLETE 22hO2Fh reserved
www.austriamicrosystems.com Revision 0.90 29 O 61 AS3421 AS3422 Datasheet O Register Description OTP Register 10h ANC_L2 TEST_BIT_5 MICL_VOL_OTP2<6:0> 11h ANC_R2 ALT1_LOCK MICR_VOL_OTP2<6:0> 12h ANC_L3 TEST_BIT_6 MICL_VOL_OTP3<6:0> 13h ANC_R3 ALT2_LOCK MICR_VOL_OTP3<6:0> 14h ANC_L4 TEST_BIT_7 MICL_VOL_OTP4<6:0> 15h ANC_R4 ALT3_LOCK MICR_VOL_OTP4<6:0> 16h MICS_CNTR LowBat + 100mV DEL_ ANC_MUX 17h PWRUP SEQ_LOCK FAST_START<4:0> 0: ~900ms; 0Eh: ~600ms LIN_AGC_OFF MIC_AGC_OFF 30h ANC_L TEST_BIT_1 MICL_VOL_OTP<6:0> 31h ANC_R TEST_BIT_2 MICR_VOL_OTP<6:0> 32h MIC_MON MON_MODE 0: fixed volume 1: adj. volume MIC_MON_OTP<6:0> 33h AUDIO_SET NO_PB_MODE_OTP 0: PB mode enabled 1: PB mode disabled VOL_BUTTON_ MODE_OTP 0: Volume Mode disabled 1: Volume Mode enabled LINE_GAIN_+3dB OTP 0: 0dB max. Line Gain 1: +3dB max. Line Gain MIC_MODE_ OTP 0: StereoSingleEnd 1: MonoDiff HP_MODE_ OTP 0: StereoSingleEnd 1: MonoDiff LIN_MON_ATTEN<2:0> 0: no attenuation; 7: MUTE 34h GP_OP HP_MUX_OTP<1:0> 0: MIC; 1: OP1; 2: OP2; 3: O OP2_OTP<3:0> 0: OP2 inverting mode; OP2_ON_OTP OP1_ON_OTP 35h OTP_SYS MAIN_LOCK 0: write reg 30h.. 35h 1: lock reg 30h..35h TEST_BIT_3 MON_HP_MUX<1:0> 0: MIC; 1: OP1; 2: OP2; 3: O CP_MODE 0: Low noise, low voltage 1: High output voltage; MICS_CP_OFF I2C_MODE 3Eh CONFIG_1 EXTBURNCLK 3Fh CONFIG_2 TM34 BURNSW TM_REG34O35 TM_REG30O33 OTP_MODE<1:0> 0: READ; 1: LOAD; 2: WRITE; 3: BURN T able 15. I2C Register Overview Addr Name b7 b6 b5 b4 b3 b2 b1 b0
www.austriamicrosystems.com Revision 0.90 30 O 61 AS3421 AS3422 Datasheet O Register Description T able 16. MIC_L Register Name Base Default MIC_L 2-wire serial 00h Offset: 08h Left Microphone Input Register Configures the gain for the left microphone input and defines the microphone operation mode. This register is reset at POR. Bit Bit Name Default Access Bit Description
7 MIC_MODE 0 R/W Selects the microphone input mode
0: single ended stereo mode 1: mono differential mode 6:0 MICL_VOL<6:0> 000 0000 R/W Volume settings for left microphone input, adjustable in 127 steps of 0.375dB 00 0000: MUTE 00 0001: O11.25 dB gain 00 0010: O10.875 dB gain 11 1110: 35.625 dB gain 11 1111: 36 dB gain T able 17. MIC_R Register Name Base Default MIC_R 2-wire serial 00h Offset: 09h Right Microphone Input Register Configures the gain for the right microphone input and enables register 08h & 09h. This register is reset at POR. Bit Bit Name Default Access Bit Description 7 MIC_REG_ON 0 R/W Defines which registers are used for the microphone settings. 0: settings of register 30h and 31h are used 1: settings of register 08h and 09h are used 6:0 MICR_VOL<6:0> 000 0000 R/W Volume settings for righ t microphone input, adjustable in 127 steps of 0.375dB 00 0000: MUTE 00 0001: O11.25B gain 00 0010: O10.875 dB gain 11 1110: 35.625 dB gain 11 1111: 36 dB gain
www.austriamicrosystems.com Revision 0.90 31 O 61 AS3421 AS3422 Datasheet O Register Description T able 18. LINE_IN Register Name Base Default LINE_IN 2-wire serial 00h Offset: 0Ah Line Input Register Configures the attenuation for the line input, defines the line input operation mode and enables register 0Ah. This register is reset at POR. Bit Bit Name Default Access Bit Description 7 LIN_REG_ON 0 R/W Defines which source is used for the line input settings. 0: settings of register 33h and VOL pin are used 1: register 0Ah is used 6 LINE_GAIN_+3dB 0 R/W Selects the line input operating gain range. If this bit is set the gain range of the line input amplifiers is shifted by +3dB. 0: Line Input gain range from -46.5dB...0dB 1: Line Input gain range from O43.5dB...+3dB 5:0 LIN_VOL<5:0> 00 0000 R/W Volume settings for line i nput, adjustable in 63 steps of 0.75dB. the following gain settings are valid if LINE_GAIN_+3dB bit is set to ‘0’. 00 0000: MUTE 00 0001:O46.5dB gain 00 0010:O45.75dB gain 11 1110:O0.75dB gain 11 1111:.0 dB gain Volume settings for line input, adjustable in 63 steps of 0.75dB. the following gain settings are valid if LINE_GAIN_+3dB bit is set to ‘1’. 00 0000: MUTE 00 0001:O43.5dB gain 00 0010:O42.75dB gain 11 1110:+2.25dB gain 11 1111:+3 dB gain T able 19. GP_OP_L Register Name Base Default GP_OP_L 2-wire serial 00h Offset: 0Bh Left General Purpose Operational Amplifier Register Enables the left opamp stages, defines opamp 2 mode and gain and sets the HP input multiplexer. This register is reset at POR. Bit Bit Name Default Access Bit Description 7:6 HP_MUX<1:0> 00 R/W Multiplexes the analog audio sig nal to HP amp 00: MIC: selects QMICL/R output 01: OP1: selects QOP1L/R outputs 10:OP2: selects QOP2L/R output 11: open: no signal mixed together with the line input signal 5:2 OP2L<3:0> 0000 R/W Mode and volume settings for lef t OP2, adjustable in 15 steps of 0.75dB 0000: OP2L in inverting mode 0001: 0 dB gain, OP2L in non inverting mode 0001: 0.75 dB gain, non inverting .., 1110: 9.75dB gain, non inverting 1111:.10.5 dB gain, non inverting
www.austriamicrosystems.com Revision 0.90 32 O 61 AS3421 AS3422 Datasheet O Register Description
1 OP2L_ON 0 R/W Enables left OP 2
0: left OP2 is switched off 1: left OP2 is enabled
0 OP1L_ON 0 R/W Enables left OP 1
0: left OP1 is switched off 1: left OP1 is enabled T able 20. GP_OP_R Register Name Base Default GP_OP_R 2-wire serial 00h Offset: 0Ch Right General Purpose Operational Amplifier Registe r Enables the right opamp stages, defines opamp 2 mode and gain and sets the HP mode. This register is reset at POR. Bit Bit Name Default Access Bit Description 7 OP_REG_ON 0 R/W Defines which register is used for th e opamp and HP settings. 0: settings of register 33h and 34h are used 1: register 0B and 0Ch are used
6 HP_MODE 0 R/W Selects the line input mode
0: single ended stereo mode 1: mono differential mode 5:2 OP2R<3:0> 0000 R/W Mode and volume settings for rig ht OP2, adjustable in 15 steps of 0.75dB 0000: OP2R in inverting mode 0001: 0 dB gain, OP2R in non inverting mode 0001: 0.75 dB gain, non inverting .., 1110: 9.75dB gain, non inverting 1111:.10.5 dB gain, non inverting
1 OP2R_ON 0 R/W Enables right OP 2
0: right OP2 is switched off 1: right OP2 is enabled
0 OP1R_ON 0 R/W Enables right OP 1
0: right OP1 is switched off 1: right OP1 is enabled T able 19. GP_OP_L Register Name Base Default GP_OP_L 2-wire serial 00h Offset: 0Bh Left General Purpose Operational Amplifier Register Enables the left opamp stages, defines opamp 2 mode and gain and sets the HP input multiplexer. This register is reset at POR. Bit Bit Name Default Access Bit Description
www.austriamicrosystems.com Revision 0.90 33 O 61 AS3421 AS3422 Datasheet O Register Description T able 21. SYSTEM Register Name Base Default SYSTEM 2-wire serial 31h Offset: 20h SYSTEM Register This register is reset at a POR. Bit Bit Name Default Access Bit Description 7:4 Design_Version<3:0> 1001 R AFE number to identify t he design version 1001: for chip version 1v1
3 TESTREG_ON 0 R/W 0: normal operation
1: enables writing to test register 3Eh & 3Fh to configure the OTP and set the access mode.
2 MONITOR_ON 0 R/W Enables the monitor mode
0: normal operation 1: monitor mode enabled
1 CONT_PWRUP 0 R/W Continues the automatic powerOup seq uence when using the I2C mode
0: chip stops the power-up sequence after the suppl ies are stable, switching on individual blocks has to be done via I 2C commands 1: automatic powerOup sequence is continued
0 PWR_HOLD 1 R/W 0: power up hold is cleared and AFE wi ll power down
1: is automatically set to on after power on T able 22. PWR_SET Register Name Base Default PWR_SET 2-wire serial 0x11 1111b (stand alone mode) 0x00 0000b (I2C mode) Offset: 21h Power Setting Register Please be aware that writing to this register will enable/disable the corresponding blocks, while reading gets the actual status. It is not pos sible to read back e.g ILED settings. This register is reset at POR. Bit Bit Name Default Access Bit Description 7 PWR_REG_ON 0 R/W Defines which register is used for t he power settings. 0: all blocks stay on as defined in the start-up se quence 1: register 21h is used
6 LOW_BAT x R VBAT supervisor status
0: VBAT is above brown out level 1: BVDD has reached brown out level
5 PWRUP_COMPLETE x R PowerOUp sequencer status
0: power-up sequence incomplete 1: powerOup sequence completed
4 HP_ON 0 W 0: switches HP stage off
1: switches HP stage on x R 0: HP stage not powered 1: normal operation
3 MIC_ON 0 W 0: switches microphone stage off
1: switches microphone stage on x R 0: microphone stage not powered 1: normal operation
www.austriamicrosystems.com Revision 0.90 34 O 61 AS3421 AS3422 Datasheet O Register Description
2 LIN_ON 0 W 0: switches line input stage off
1: switches line input stage on x R 0: line input stage not powered 1: normal operation
1 MICS_CP_ON 0 W 0: switches microphone supply charge pump off
1: switches microphone supply charge pump on x R 0: microphone supply charge pump not powered 1: normal operation
0 MICS_ON 0 W 0: switches microphone supply off
1: switches microphone supply on x R 0: microphone supply not enabled 1: normal operation T able 22. PWR_SET Register Name Base Default PWR_SET 2-wire serial 0x11 1111b (stand alone mode) 0x00 0000b (I2C mode) Offset: 21h Power Setting Register Please be aware that writing to this register will enable/disable the corresponding blocks, while reading gets the actual status. It is not pos sible to read back e.g ILED settings. This register is reset at POR. Bit Bit Name Default Access Bit Description
www.austriamicrosystems.com Revision 0.90 35 O 61 AS3421 AS3422 Datasheet O Register Description T able 23. ANC_L2 Register Name Base Default ANC_L2 2-wire serial 80h (OTP) Offset: 10h Left OTP Microphone Input Register (2nd OTP option) Configures the gain for the left microphone input. This is a special register, writing needs to be enabled by writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents. Bit Bit Name Default Access Bit Description
7 TEST_BIT_5 1 R for testing purpose only
6:0 MICL_VOL_OTP2 <6:0> 000 0000 R/W Volume settings for left microphone inpu t, adjustable in 127 steps of 0.375dB 00 0000: MUTE 00 0001: O11.25dB gain 00 0010: O10.875 dB gain 11 1110: 35.625dB gain 11 1111: 36 dB gain T able 24. ANC_R2 Register Name Base Default ANC_R2 2-wire serial 00h (OTP) Offset: 11h Right OTP Microphone Input Register (2nd OTP option ) Configures the gain for the left microphone input. This is a special register, writing needs to be enabled by writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents. Bit Bit Name Default Access Bit Description
7 ALT1_LOCK 0 R/W 0: additional bits can be fused inside register 10h & 11h
1: OTP fusing for register 10h & 11h gets locked, no more changes can be done. 6:0 MICR_VOL_OTP2 <6:0> 000 0000 R/W Volume settings for right microphone inp ut, adjustable in 127 steps of 0.375dB 00 0000: MUTE 00 0001: O11.25dB gain 00 0010: O10.875 dB gain 11 1110: 35.625dB gain 11 1111: 36 dB gain
www.austriamicrosystems.com Revision 0.90 36 O 61 AS3421 AS3422 Datasheet O Register Description T able 25. ANC_L3 Register Name Base Default ANC_L3 2-wire serial 80h (OTP) Offset: 12h Left OTP Microphone Input Register (3rd OTP option) Configures the gain for the left microphone input. This is a special register, writing needs to be enabled by writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents. Bit Bit Name Default Access Bit Description
7 TEST_BIT_6 1 R for testing purpose only
6:0 MICL_VOL_OTP3 <6:0> 000 0000 R/W Volume settings for left microphone inpu t, adjustable in 127 steps of 0.375dB 00 0000: MUTE 00 0001: O11.25dB gain 00 0010: O10.875 dB gain 11 1110: 35.625dB gain 11 1111: 36 dB gain T able 26. ANC_R3 Register Name Base Default ANC_R3 2-wire serial 00h (OTP) Offset: 13h Right OTP Microphone Input Register (3rd OTP option ) Configures the gain for the left microphone input. This is a special register, writing needs to be enabled by writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents. Bit Bit Name Default Access Bit Description
7 ALT2_LOCK 0 R/W 0: additional bits can be fused inside register 12h & 13h
1: OTP fusing for register 12h & 13h gets locked, no more changes can be done. 6:0 MICR_VOL_OTP3 <6:0> 000 0000 R/W Volume settings for right microphone inp ut, adjustable in 127 steps of 0.375dB 00 0000: MUTE 00 0001: O11.25dB gain 00 0010: O10.875 dB gain 11 1110: 35.625dB gain 11 1111: 36 dB gain
www.austriamicrosystems.com Revision 0.90 37 O 61 AS3421 AS3422 Datasheet O Register Description T able 27. ANC_L4 Register Name Base Default ANC_L4 2-wire serial 80h (OTP) Offset: 14h Left OTP Microphone Input Register (4th OTP option) Configures the gain for the left microphone input. This is a special register, writing needs to be enabled by writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents. Bit Bit Name Default Access Bit Description
7 TEST_BIT_7 1 R for testing purpose only
6:0 MICL_VOL_OTP4 <6:0> 000 0000 R/W Volume settings for left microphone inpu t, adjustable in 127 steps of 0.375dB 00 0000: MUTE 00 0001: O11.25dB gain 00 0010: O10.875 dB gain 11 1110: 35.625dB gain 11 1111: 36 dB gain T able 28. ANC_R4 Register Name Base Default ANC_R4 2-wire serial 00h (OTP) Offset: 15h Right OTP Microphone Input Register (4th OTP option ) Configures the gain for the left microphone input. This is a special register, writing needs to be enabled by writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents. Bit Bit Name Default Access Bit Description
7 ALT3_LOCK 0 R/W 0: additional bits can be fused inside register 14h & 15h
1: OTP fusing for register 14h & 15h gets locked, no more changes can be done. 6:0 MICR_VOL_OTP4 <6:0> 000 0000 R/W Volume settings for right microphone inp ut, adjustable in 127 steps of 0.375dB 00 0000: MUTE 00 0001: O11.25dB gain 00 0010: O10.875 dB gain 11 1110: 35.625dB gain 11 1111: 36 dB gain
www.austriamicrosystems.com Revision 0.90 38 O 61 AS3421 AS3422 Datasheet O Register Description T able 29. MICS_CNTR Register Name Base Default MICS_CNTR 2-wire serial 00h (OTP) Offset: 16h Microphone Supply Regsiter Configures the low battery threshold value Bit Bit Name Default Access Bit Description
3 LowBat 0 R/W 0: default LowBat value
1: 100mV increase of LowBat threshold
0 DEL_ ANC_MUX 0 R/W 0: default startup timing of AS3421/22
1: HP_MUX_OTP is set to OTP value 0.8s after device startup T able 30. PWRUP_CNTR Register Name Base Default PWRUP_CNTR 2-wire serial 00h (OTP) Offset: 17h PowerUp Control Register Configures chip startOup speed. This is a special register, writing needs to be enabled by writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents. Bit Bit Name Default Access Bit Description
7 SEQ_LOCK 0 R/W 0: additional bits can be fused inside register 16h & 17h
1: OTP fusing for register 16h & 17h gets locked, no more changes can be done. 6:2 FAST_START <4:0> 0 0000 R/W 0h: ~900ms start-up time 0Eh: ~600ms startOup time
1 LIN_AGC_OFF 0 R/W 0: Line Input AGC enabled
1: Line Input AGC switched off
0 MIC_AGC_OFF 0 R/W 0:Microphone Input AGC enabled
1: Microphone Input AGC switched off T able 31. ANC_L Register Name Base Default ANC_L 2-wire serial 80h (OTP) Offset: 30h Left OTP Microphone Input Register Configures the gain for the left microphone input. This is a special register, writing needs to be enabled by writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents. Bit Bit Name Default Access Bit Description
7 TEST_BIT_1 1 R for testing purpose only
6:0 MICL_VOL_OTP <6:0> 000 0000 R/W Volume settings for left microphone inpu t, adjustable in 127 steps of 0.375dB 00 0000: MUTE 00 0001: O11.25dB gain 00 0010: O10.875 dB gain 11 1110: 35.625dB gain 11 1111: 36 dB gain
www.austriamicrosystems.com Revision 0.90 39 O 61 AS3421 AS3422 Datasheet O Register Description T able 32. ANC_R Register Name Base Default ANC_R 2-wire serial 80h (OTP) Offset: 31h Right OTP Microphone Input Register Configures the gain for the left microphone input. This is a special register, writing needs to be enabled by writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents. Bit Bit Name Default Access Bit Description
7 TEST_BIT_2 1 R for testing purpose only
6:0 MICR_VOL_OTP <6:0> 000 0000 R/W Volume settings for right microphone inp ut, adjustable in 127 steps of 0.375dB 00 0000: MUTE 00 0001: O11.25dB gain 00 0010: O10.875 dB gain 11 1110: 35.625dB gain 11 1111: 36 dB gain
www.austriamicrosystems.com Revision 0.90 40 O 61 AS3421 AS3422 Datasheet O Register Description T able 33. MIC_MON Register Name Base Default MIC_MON 2-wire serial 00h (OTP) Offset: 32h OPT Microphone Monitor Mode Register Configures the gain for the microphone input in monitor mode. This is a special register, writing needs to be enabled by writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents. Bit Bit Name Default Access Bit Description
7 MON_MODE 0 R/W 0: monitor mode is working with fixed microphone ga in
1: monitor mode uses adjustable gain via the VOL pin 6:0 MIC_MON_OTP <6:0> 000 0000 R/W Volume settings for microphone input dur ing monitor mode, adjustable in 127 steps of 0.375dB. If MON_MODE bit is set to 1 the gain can be further adjusted via the VOL pin. 00 0000: MUTE 00 0001: O11.25dB gain 00 0010: O10.875 dB gain 11 1110: 35.625dB gain 11 1111: 36 dB gain T able 34. AUDIO_SET Register Name Base Default AUDIO_SET 2-wire serial 00h (OTP) Offset: 33h OPT Audio Setting Register Configures the audio settings. This is a special register, writing needs to be enabled by writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents. Bit Bit Name Default Access Bit Description 7 NO_PB_MODE 0 R/W This bit defines if the low power mu sic playback mode is enabled or not. In case the bit is set to ‘0’, music playback mode can be entered by pulling the ANC_CSDA pin low. In case the bit is set to ‘1’ the music playback mode is disabled. Pulling the ANC_CSDA pin low has no influence. 0: Music playback mode enabled 1: Music playback mode disabled 6 VOL_BUTTON_MODE 0 R/W If bit is set to ‘1’ the ANC_CS DA pin allows the user to control the line input gain via pushObuttons. If bit is set to ‘0’, the volume control is disabled. Please mind that if VOL_BUTTON_MODE bit is set to ‘1’ entering music playback mode via ANC_CSDA pin is not possible any more. 0: Volume mode via push-button disabled 1: Volume mode via pushObutton enabled 5 LINE_GAIN_+3dB_OTP 0 R/W Selects the line input opera ting gain range. If this bit is set the gain range of the line input amplifiers is shifted by +3dB. 0: Line Input gain range from -46.5dB...0dB 1: Line Input gain range from O43.5dB...+3dB
4 MIC_MODE_OTP 0 R/W 0: microphone input stage operating in single ended mode
1: normal operating in mono balanced
www.austriamicrosystems.com Revision 0.90 41 O 61 AS3421 AS3422 Datasheet O Register Description
3 HP_MODE_OTP 0 R/W 0: headphone stage operating in single ended mode
1: normal operating in mono balanced 2:0 LIN_MON_ATTEN <6:0>
000 R/W Volume settings for line input during monitor mode, adjustable in 7 steps of
6dB and mute. 000: 0dB gain 001: O6dB gain 110: O36dB gain 111: MUTE T able 34. AUDIO_SET Register Name Base Default AUDIO_SET 2-wire serial 00h (OTP) Offset: 33h OPT Audio Setting Register Configures the audio settings. This is a special register, writing needs to be enabled by writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents. Bit Bit Name Default Access Bit Description
www.austriamicrosystems.com Revision 0.90 42 O 61 AS3421 AS3422 Datasheet O Register Description T able 35. GP_OP Register Name Base Default GP_OP 2-wire serial 00h (OTP) Offset: 34h OTP General Purpose Operational Amplifier Register Enables the opamp stages, defines opamp 2 mode and gain and sets the HP input multiplexer. This is a special register, writing needs to be enabled by writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents. Bit Bit Name Default Access Bit Description 7:6 HP_MUX_OTP<1:0> 00 R/W Multiplexes the analog audio signal to HP amp 00: MIC: selects QMICL/R output 01:OP1: selects QOP1L/R outputs 10:OP2: selects QOP2L/R output 11: open: no signal mixed together with the line input signal 5:2 OP2_OTP<3:0> 0000 R/W Mode and volume settings for OP2, adjustable in 15 steps of 0.75dB 0000: OP2L in inverting mode 0001: 0 dB gain, OP2L in non inverting mode 0001: 0.75 dB gain, non inverting .., 1110: 9.75dB gain, non inverting 1111:.10.5 dB gain, non inverting
1 OP2_ON 0 R/W 0: OP2 is switched off
1: left OP2 is enabled
0 OPL_ON 0 R/W 0: OP1 is switched off
1: OP1 is enabled T able 36. OTP_SYS Register Name Base Default OTP_SYS 2-wire serial 40h (OTP) Offset: 35h OTP System Settings Register Defines several system settings for OTP operation. This is a special register, writing needs to be enabled by writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents. Bit Bit Name Default Access Bit Description
7 MAIN_LOCK 0 R/W 0: additional bits can be fused inside the OTP
1: OTP fusing gets locked, no more changes can be done
6 TEST_BIT_3 1 R for testing purpose only
5:4 MON_HP_MUX <1:0>
00 R/W Multiplexes the analog audio signal to HP amp in monitor mode
00: MIC: selects QMICL/R output 01: OP1: selects QOP1L/R outputs 10:OP2: selects QOP2L/R output 11: open: no signal mixed together with the line input signal 2 CP_MODE_OTP 0 R/W This bit controls the operating mod e of the microphone supply charge pump. 0: Standard low noise operation 1: Increased output voltage
1 MICS_CP_OFF 0 R/W 0: MICS charge pump is enabled
1: MICS charge pump is switched off
0 I2C 0 R/W 0: I2C and stand alone mode start-up possible
1: chip startsOup in I2C mode only
www.austriamicrosystems.com Revision 0.90 43 O 61 AS3421 AS3422 Datasheet O Register Description T able 37. CONFIG_1 Register Name Base Default CONFIG_1 2-wire serial 00h Offset: 3Eh OTP Configuration Register Controls the clock configuration. This is a special register, writing needs to be enabled by writing 9h to Reg 20h first. This register is reset at POR and gets loaded with the OTP fuse contents. Bit Bit Name Default Access Bit Description 7:4 O 0000 n/a 3 EXTBURNCLK 0 n/a 0: ext. clock for OTP burning disabled 1: ext. clock for OTP burning enabled 2:0 O 000 n/a T able 38. CONFIG_2 Register Name Base Default CONFIG_2 2-wire serial 00h Offset: 3Fh OTP Access Configuration Register Controls the OTP access. This is a special register, writing needs to be enabled by writing 9h to Reg 20h first. This register is reset at POR and gets loaded with the OTP fuse contents. Bit Bit Name Default Access Bit Description 7:6 O 000 n/a
5 TM34 0 n/a This Register defines the Register bank se lection for Register
TM_REG34O35 and TMREG30O33. Depending on TM34 you can select either between Register bank 14hO17h and 10hO13h enabled or 30hO33h and 34hO37h enabled. 0: test mode Registers 14h-17h and 10h-13h disabled test mode Registers 30h-33h and 34h-37h enabled 1: test mode Registers 14hO17h and 10hO13h enabled test mode Registers 30hO33h and 34hO37h disabled
4 BURNSW 0 n/a 0: BURN switch from LINL to VNEG is disabled
1: BURN switch from LINL to VNEG is enabled
3 TM_REG34O35 0 n/a 0: test mode for Register 34h-35h disabled
test mode for Register 14h-17h disabled 1: test mode for Register 34hO35h enabled test mode for Register 14hO17h enabled
2 TM_REG30O33 0 n/a 0: test mode for Register 30h-33h disabled
test mode for Register 10h-13h disabled 1: test mode for Register 30hO33h enabled test mode for Register 10hO13h enabled 1:0 OTP_MODE<1:0> 00 R/W Controls the OTP access 00: READ 01: LOAD 10: WRITE 11: BURN
11.1 AS3422 Feedback Application Examples
Figure 35. AS3422 Feedback Application Example wit h Bluetooth I2C Control
Figure 36. AS3422 Feedback Application Example wit h Bluetooth ROM Version (No I2C Control)
Figure 37. AS3422 Schematic - Stereo Bluetooth Fee dback Application with I2C Control CAUTION: Exposed pad must be connect to VNEG or left unconnected.
Figure 38. AS3422 Schematic - Stereo Bluetooth Fee dback Application with ROM Version (No I2C Control) CAUTION: Exposed pad must be connect to VNEG or left unconnected.
11.2 AS3421 Feed Forward Application Examples
Figure 39. AS3421 Feed-Forward Application Example with Bluetooth I2C Control
Figure 40. AS3421 Feed-Forward Application Example with Bluetooth ROM Version (No I2C Control)
Figure 41. AS3421 Schematic - Stereo Feed-Forward Bluetooth Application with I2C Control CAUTION: Exposed pad must be connect to VNEG or left unconnected.
Figure 42. AS3421 Schematic - Stereo Feed-Forward Bluetooth Application ROM Version (No I2C Control) CAUTION: Exposed pad must be connect to VNEG or left unconnected.
11.3 Layout Recommendation
audio performance of the device. Therefore it is very important to make sure that the layout of the charge pump is done properly. point which is indicated with three vias in the example. Figure 43. AS3422 CP Layout Recommendation Figure 44. AS3422 Star Shaped Ground Concept For component references please refer to figure 24. For component references please refer to figure 24.
therefore the alignment of the charge pump components is different. A layout recommendation for AS3421 is shown in Figure 45 below. Figure 45. AS3421 CP Layout Recommendation
11.4 Bill of Materials
components shown in Table 39 refer to the schematics shown in Figure 37 and Figure 41 .
1 U1 AS3421 Stereo Bluetooth ANC headphone driver circ uit 1
2 U2 AS1363OAD Low Drop Voltage Regulator 1
3 C3, C15 1µF Charge Pump flying capacitor; +/O 10% to lerance and LDO support 2
4 C1, C6 100nF PMU Blocking capacitors; +/O 10% tolera nce 2
5 C7, C8, C9, C10 220nF Audio DC coupling capacitors; +/O 10% tolerance 4
6 C13 10µF Microphone supply filter capacitor; +/O 10% tolerance 1
8 R5, R6 2k2 Microphone bias resistors; +/O 5%toleranc e 2
9 C2, C5 10µF PMU Blocking capacitors; +/O 10% toleran ce 2
10 R7 15k Voltage Regulator feedback resistor 1
11 R8 47k Voltage Regulator feedback resistor 1
12 R3, R4 10k Two wire interface pull up resistors; +/ O 10% tolerance 2
For component references please refer to figure 26.
11.5 PCB Footprint Recommendation
Figure 46. AS3421 PCB Footprint Recommendation
Figure 47. AS3422 PCB Footprint Recommendation
Figure 48. QFN Marking
Figure 49. AS3421, 24-pin QFN 0.5mm Pitch
Figure 50. AS2322 32-pin QFN 0.5mm Pitch
www.austriamicrosystems.com Revision 0.90 59 O 61 AS3421 AS3422 Datasheet O Revision History
Revision History
Note: Typos may not be explicitly mentioned under revision history. Revision Date Owner Description 0.2 25.1.2012 hgt initial release 0.3 14.3.2012 hgt updated low power playback mode and pin descriptions 0.4 11.6.2012 hgt updated microphone parameters
www.austriamicrosystems.com Revision 0.90 60 O 61 AS3421 AS3422 Datasheet O Ordering Information The devices are available as the standard products shown in Table 41 . Note: All products are RoHS compliant and austriamicrosystems green. Buy our products or get free samples online at ICdirect: http://www.austriamicrosystems.com/ICdirect For further information and requests, please contact us mailto:sales@austriamicrosystems.com or find your local distributor at http://www.austriamicrosystems.com/distributor T able 41. Ordering Information Ordering Code Description Delivery Form Package AS3421OEQFP Low Power Ambient NoiseOCancelling Speak er Driver Tape & Reel dry pack QFN 24 [4.0x4.0x0.85mm] 0.5mm pitch AS3421OEQFPO500 Low Power Ambient NoiseOCancelling S peaker Driver Tape & Reel dry pack QFN 24 [4.0x4.0x0.85mm] 0.5mm pitch AS3422OEQFP Low Power Ambient NoiseOCancelling Speak er Driver Tape & Reel dry pack QFN 32 [5.0x5.0x0.85mm] 0.5mm pitch AS3422OEQFPO500 Low Power Ambient NoiseOCancelling S peaker Driver Tape & Reel dry pack QFN 32 [5.0x5.0x0.85mm] 0.5mm pitch
www.austriamicrosystems.com Revision 0.90 61 O 61 AS3421 AS3422 Datasheet O Copyrights Copyrights Copyright © 1997O2012, austriamicrosystems AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, AustriaOEurope. Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies. Disclaimer Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical lifeOsupport or lifeOsustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services. Contact Information Headquarters austriamicrosystems AG Tobelbaderstrasse 30 AO8141 Unterpremstaetten, Austria Tel: +43 (0) 3136 500 0 Fax: +43 (0) 3136 525 01 For Sales Offices, Distributors and Representatives, please visit: http://www.austriamicrosystems.com/contact