AS29F040

AS29F040 AUSTIN | Alldatasheet

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Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. AS29F040 Rev. 2.2 09/07 Austin Semiconductor, Inc. 512K x 8 FLASH UNIFORM SECTOR 5.0V FLASH MEMORY AVAILABLE AS MILITARY SPECIFICATIONS

• MIL-STD-883
• SMD 5962-96692

FEATURES

• Single 5.0V ±10% power supply operation
• Fastest access times: 55, 60, 70, 90, 120, & 150ns
• Low power consumption: 3 20 mA typical active read current 3 30 mA typical program/erase current 3 1 µA typical standby current (standard access time to active mode)
• Flexible sector architecture

3 Eight uniform 64 Kbyte each

3 Any combination of sectors can be erased

3 Supports full chip erase

• Sector protection
• Embedded Algorithms Erase & Program Algorithms
• Erase Suspend/Resume
• Minimum 1,000,000 Program/Erase Cycles per sector guaranteed
• Compatible with JEDEC standards

3 Pinout and software compatible with single-power-

• Data\\ Polling and Toggle Bits
• 20-year data retention at 125°C For more products and information please visit our web site at www.austinsemiconductor.com PIN ASSIGNMENT (Top View) 32-PIN Ceramic DIP (CW) 32-pin Flatpack (F) 32-pin Lead Formed Flatpack (DCG) A18 A16 A15 A12 DQ0 DQ1 DQ2 VSS VCC WE\\ A17 A14 A13 A11 OE\\ A10 CE\\ DQ7 DQ6 DQ5 DQ4 DQ3 OPTIONS MARKING
• Timing 55ns -55 60ns -60 70ns -70 90ns -90 120ns -120 150ns -150 OPTIONS MARKING
• Package Type Ceramic DIP (600 mil) CW Flatpack F Lead Formed Flatpack DCG Leadless Chip Carrier ECA Temperature Ranges Industrial Temperature (-40°C to +85°C) IT Military Temperature (-55°C to +125°C)XT** 883C Processing (-55°C to +125°C) 883C QML Processing (-55°C to +125°C) Q A12 A15 A16 A18 VCC WE\\ A17 4 3 2 32 31 30 14 15 16 17 18 19 20 I/O0 A14 A13 A11 OE\\ A10 CE\\ I/O 7 I/O6 I/O5 I/O4 I/O3 VSS I/O2 I/O1 32-PAD Ceramic LCC (ECA)

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. AS29F040 Rev. 2.2 09/07 Austin Semiconductor, Inc. GENERAL DESCRIPTION The AS29F040 is a 4Mbit, 5.0 V olt-only FLASH memory organized as 524,288 Kbytes of 8 bits each. The 512 Kbytes of data are divided into eight sectors of 64 Kbytes each for flexible erase capability. The 8 bits of data appear on DQ0-DQ7. The device is designed to be programmed in-system with the standard system 5.0 V olt V CC supply. A 12.0 volt V PP is not required for write or erase operations. The device can also be programmed in standard EPROM programmers. This device is manufactured using 0.32 µm process technology. In addition, it has a second toggle bit, DQ2, and offers the ability to program in the Erase Suspend mode. It is available with access times of 55, 60, ^+^+6=70, 90, 120, and 150ns, allowing high-speed microprocessors to operate with- out wait states. To eliminate bus contention the device has separate chip enable (CE\\), write enable (WE\\), and output en- able (OE\\) controls. The device requires only a single 5.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC single-power-supply FLASH standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other FLASH or EPROM devices. Device programming occurs by executing the program command sequence. This invokes the Embedded Program algorithm -- an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Device erasure occurs by executing the erase command sequence. This invokes the Embedded Erase algorithm -- an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by reading the DQ7 (Data\\Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. The hardware data protection measures include a low V CC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved via programming equipment. The erase suspect feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The system can place the device into the standby mode. Power consumption is greatly reduced in this mode. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection. PIN CONFIGURATION LOGIC SYMBOL PIN DESCRIPTION A0 - A18 Address Inputs DQ0 - DQ7 Data Inputs/Outputs CE\\ Chip Enable OE\\ Output Enable WE\\ Write Enable VCC +5V Single Power Supply VSS Device Ground

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. AS29F040 Rev. 2.2 09/07 Austin Semiconductor, Inc. FUNCTIONAL BLOCK DIAGRAM

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. AS29F040 Rev. 2.2 09/07 Austin Semiconductor, Inc. DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches that store the commands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. The appropriate device bus operations table lists the inputs and control levels required, and the resulting output. The following subsections describe each of these operations in further detail. Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE\\ and OE\\ pins to V IL. CE\\ is the power control and selects the device. OE\\ is the output control and gates array data to the output pins. WE\\ should remain at VIH. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. See “Reading Array Data” for more information. Refer to the AC Read Operations table for timing specifications and to the Read Operations Timings diagram for the timing waveforms. I CC1 in the DC Characteristics table represents the active current specification for reading array data. TABLE 1: DEVICE BUS OPERATIONS NOTES: See the “Sector Protection/Unprotection” section for more information. Writing Commands/Command Sequences To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE\\ and CE\\ to VIL, and OE\\ to VIH. An erase operation can erase one sector, multiple sectors, or the entire device. The Sector Address Tables indicate the address space that each sector occupies. A “sector address” consists of the address bits required to uniquely select a sector. See the “Command Definitions” section for details on erasing a sector or the entire chip, or suspending/resuming the erase operation. After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7 - DQ0. Standard read cycle timings apply in this mode. Refer to the “Autoselect Mode” and “Autoselect Command Sequence” sections for more information. I CC2 in the DC Characteristics table represents the active current specification for the write mode. The “AC Characteristics” section contains timing specification tables and timing diagrams for write operations. Program and Erase Operation Status During an erase or program operation, the system may check the status of the operation by reading the status bits on DQ7 - DQ0. Standard read cycle timings and I CC read specifications apply. Refer to “Write Operation Status” for more information, and to each AC Characteristics section for timing diagrams. OPERATION CE\\ OE\\ WE\\ A0 - A20 DQ0 - DQ7 Read L L H AIN DOUT Write L H L AIN DIN CMOS Standby VCC ± 0.5V X X X High-Z TTL Standby H X X X High-Z Output Disable L H H X High-Z

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. AS29F040 Rev. 2.2 09/07 Austin Semiconductor, Inc. Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE\\ input. The device enters the CMOS standby mode when the CE\\ pin is held at V CC ± 0.5V . (Note that this is a more restricted voltage range than V IH.) The device enters the TTL standby mode when CE\\ is held at VIH. The device requires the standard access time (tCE) before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. ICC3 in the DC Characteristics table represents the standby current specification. Output Disable Mode When the OE\\ input is at V IH, output from the device is disabled. The output pins are placed in the high impedance state. Autoselect Mode The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7 - DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode requires V ID (11.5V to 12.5 V) on address pin A9. Address pins A6, A1, and A0 must be as shown in the Autoselect Codes (High V oltage Method) table. In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits. Refer to the corresponding Sector Address Tables. The Command TABLE 2: SECTOR ADDRESSES TABLE NOTE: All sectors are 64 Kbytes in size. Definitions table shows the remaining address bits that are don’t care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7 - DQ0 To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in the Command Definitions table. This method does not require V ID. See “Command Definitions” for details on using the autoselect mode. Sector Protection/Unprotection The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors. Sector protection/unprotection must be implemented using programming equipment. The procedure requires a high voltage (V ID) on address pin A9 and the control pins. The device is shipped with all sectors unprotected. It is possible to determine whether a sector is protected or unprotected. See “Autoselect Mode” for details. Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to the Command Definitions table). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during V CC power-up and power-down transitions, or from system noise. Low VCC Write Inhibit When VCC is less than V LKO, the device does not accept any write cycles. This protects data during VCC power-up and SECTOR A18 A17 A16 ADDRESS RANGE SA0 0 0 0 00000h - 0FFFFh SA1 0 0 1 10000h - 1FFFFh SA2 0 1 0 20000h - 2FFFFh SA3 0 1 1 30000h - 3FFFFh SA4 1 0 0 40000h - 4FFFFh SA5 1 0 1 50000h - 5FFFFh SA6 1 1 0 60000h - 6FFFFh SA7 1 1 1 70000h - 7FFFFh

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. AS29F040 Rev. 2.2 09/07 Austin Semiconductor, Inc. power-down. The command register and all internal program/ erase circuits are disabled, and the device resets. Subsequent writes are ignored until V CC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO. Write Pulse “Glitch” Protection Noise pulses of less than 5ns (typical) on OE\\, CE\\, or WE\\ do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE\\ = VIL, CE\\ = VIH or WE\\ = VIH. To initiate a write cycle, CE\\ and WE\\ must be a logical zero while OE\\ is a logical one. Power-Up Write Inhibit If WE\\ = CE\\ = VIL and OE\\ = VIH during power up, the device does not accept commands on the rising edge of WE\\. The internal state machine is automatically reset to reading array data on power-up. COMMAND DEFINITIONS Writing specific address and data commands or sequences into the command register initiates device operations. The Command Definitions table defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. All addresses are latched on the falling edge of WE\\ or CE\\, whichever happens later. All data is latched on the rising edge of WE\\ or CE\\, whichever happens first. Refer to the appropriate timing diagrams in the “AC Characteristics” section. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. TABLE 3: Autoselect Codes (High Voltage Method) The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See “Erase Suspend/Erase Resume” for more information. The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high, or while in the autoselect mode. See the “Reset Command” section, next. See also “Requirements for Reading Array Data” in the “Device Bus Operations” section for more information. The Read Operations table provides the read parameters, and the Read Operation Timings diagram shows the timing diagram. Reset Command Writing the reset command to the device resets the device to reading array data. Address bits are don’t care for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend Mode). Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend). Description A18 - A16 A15 - A10 A9 A8 - A7 A6 A5 - A2 A1 A0 Identifier Code On DQ7 to DQ0 Manufacturer ID X X VID X VIL X VIL VIL 01h Device ID X X VID X VIL X VIL VIH A4h 01h (protected) 00h (unprotected) Sector Protection Verification Sector Address XV ID XV IL XV IH VIL

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. AS29F040 Rev. 2.2 09/07 Austin Semiconductor, Inc. After an erase-suspended program operation is complete, the system can once again read array data within non-suspended sectors. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See “Write Operation Status” for more information. The system may also write the autoselect command sequence when the device is in the Erase Suspend mode. The device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the device exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation. See “Autoselect Command Sequence” for more information. The system must write the Erase Resume command (address bits are “don’t care”) to exit the erase suspend mode and continue the sector erase operation. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the device has resumed erasing. TABLE 4: Command Definitions LEGEND: X = Don’t Care. RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE\\ or CE\\ pulse, whichever h appens later. PD = Data to be programmed at location PA. Data latches on the rising edge of WE\\ or CE\\ pulse, whichever happens first. SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A18-A16 uniquely select any sector. NOTES: 1. See Table 1 for description of bus operations. 2. All values are in hexadecimal. 3. Except when reading array or autoselect data, all command bus cycles are write operations. 4. Address bits A18 - A11 are don’t care for unlock and command cycles, unless SA or PA required. 5. No unlock or command cycles required when reading array data. 6. The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ5 goes high (wh ile the device is providing status data). 7. The fourth cycle of the autoselect command sequence is a read cycle. 8. The data is 00h for an unprotected sector and 01h for a protected sector. See “Autoselect Command Sequence” for more inform ation. 9. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation. 10. The Erase Resume command is valid only during the Erase Suspend mode. Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data 1R A R D

1 XXX F0

Manufacturer ID 4 555 AA 2AA 55 555 90 X00 01 Device ID 4 555 AA 2AA 55 555 90 X01 A4 4 555 AA 2AA 55 555 A0 PA PD 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30

1 XXX B0

1 XXX 30

Bus Cycles2,3,4 First Second Third Fourth Fifth Sixth Erase Resume10 Read5 Sector Protect Verify8 Program Chip Erase Sector Erase Erase Suspend Reset6 Autoselect7 4 555 AA 2AA 55 555 90 SA X02

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. AS29F040 Rev. 2.2 09/07 Austin Semiconductor, Inc. completed the program or erase operation. The system can read array data on DQ7-DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit it toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 4). DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a “1.” This is a failure condition that indicates the program or erase cycle was not successfully completed. The DQ5 failure condition may appear if the system tries to program a “1” to a location that is previously programmed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition, the device halts the operation, and when the operation has exceeded the timing limits, DQ5 produces a “1.” Under both these conditions, the system must issue the reset command to return the device to reading array data. DQ3: Sector Erase Timer After writing a sector erase command sequence, the system may read DQ3 to determine whether or not an erase operation has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out is complete, DQ3 switches from “0” to “1.” The system may ignore DQ3 if the system can guarantee that the time between additional sector erase commands will always be less than 50µs. See also the “Sector Erase Command Sequence” section. After the sector erase command sequence is written, the system should read the status on DQ7 (Data\\ Polling) or DQ6 (Toggle Bit I) to ensure the device has accepted the command sequence, and then read DQ3. If DQ3 is “1”, the internally controlled erase cycle has begun; all further commands (other than Erase Suspend) are ignored until the erase operation is complete. If DQ3 is “0”, the device will accept additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 5 shows the outputs for DQ3. TABLE 5: WRITE OPERATION STATUS NOTES: 1. DQ7 and DQ2 requires a valid address when reading status information. Refer to the appropriate subsection for further detai ls. 2. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. See “DQ5: Exceeding Timing Limits” for more information. DQ71 DQ6 DQ52 DQ3 DQ21 Embedded Program Algorithm DQ7\\ Toggle 0 0 No Toggle Embedded Erase Algorithm 0 Toggle 0 1 Toggle Reading within Erase Suspended Sector 1 No toggle 0 N/A Toggle Reading within Non-Erase Suspended Sector Data Data Data Data Data Erase-Suspend-Program DQ7\\ Toggle 0 N/A N/A Standard Mode OPERATION Erase Suspend Mode

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. AS29F040 Rev. 2.2 09/07 Austin Semiconductor, Inc. DC CHARACTERISTICS: TTL/NMOS Compatible NOTES: 1. The I CC current listed includes both the DC operating current and the frequency dependent component (at 6 MHz). The frequency compone nt typically is less than 2mA/MHz, with OE\\ at V IH. 2. Maximum I CC specifications are tested with V CC = V CC Max. 3. I CC active while Embedded Algorithm (program or erase) is in progress. 4. Not 100% tested. 5. For CMOS mode only, I CC3 = 20µA max at extended temperatures (>+85°C). DC CHARACTERISTICS: CMOS Compatible PARAMETER DESCRIPTION SYM MIN TYP MAX UNIT Input Load Current VIN = VSS to VCC, VCC = VCC Max I LI ±1.0 µA A9 Input Load Current VCC = VCC Max, A9 = 12.5V I LIT 50 µA Output Leakage Current VOUT = VSS to VCC, VCC = VCC Max I LO ±1.0 µA VCC Active Read Current1,2 CE\\ = VIL, OE\\ = VIH ICC1 20 30 mA VCC Active Write (Program/Erase) Current2,3,4 CE\\ = VIL, OE\\ = VIH ICC2 30 40 mA VCC Standby Current2 CE\\ = VIH ICC3 0.4 1.0 mA Input Low Voltage VIL -0.5 0.8 V Input High Voltage VIH 2.0 VCC + 0.5 V Voltage for Autoselect and Sector Protect VCC = 5.25V V ID 10.5 12.5 V Output Low Voltage IOL = 12 mA, VCC = VCC Min V OL 0.45 V Output High Voltage IOH = -2.5 mA, VCC = VCC Min V OH 2.4 V Low VCC Lock-out Voltage V LKO 3.2 4.2 V PARAMETER DESCRIPTIO N SYM MIN TYP MAX UNIT Input Load Current VIN = VSS to VCC, VCC = VCC Max I LI ±1.0 µA A9 Input Load Current VCC = VCC Max, A9 = 12.5V I LIT 50 µA Output Leakage Current VOUT = VSS to VCC, VCC = VCC Max I LO ±1.0 µA VCC Active Read Current1,2 CE\\ = VIL, OE\\ = VIH ICC1 20 30 mA VCC Active Program/Erase Current2,3,4 CE\\ = VIL, OE\\ = VIH ICC2 30 40 mA VCC Standby Current2, 5 CE\\ = VCC ± 0.5V I CC3 15 µ A Input Low Voltage VIL -0.5 0.8 V Input High Voltage V IH 0.7 x VCC VCC + 0.3 V Voltage for Autoselect and Sector Protect VCC = 5.25V V ID 10.5 12.5 V Output Low Voltage IOL = 12 mA, VCC = VCC Min V OL 0.45 V Output High Voltage IOH = -2.5 mA, VCC = VCC Min V OH1 0.85 VCC V IOH = -100 µA, VCC = VCC Min V OH2 VCC - 0.4 V Low VCC Lock-out Voltage V LKO 3.2 4.2 V

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. AS29F040 Rev. 2.2 09/07 Austin Semiconductor, Inc. TABLE 6: TEST CONDITIONS, Test Specifications AC CHARACTERISTICS: Read-Only Operations FIGURE 7: TEST CONDITIONS, Test Setup NOTES: 1. See Figure 7 and Table 6 for test specifications. 2. Output driver disable time. 3. Not 100% tested. CONDITIONS -55 ALL OTHERS UNIT Output Load Output Load Capacitance, CL (including jig capacitance) 30 100 pF Input Rise and Fall Times 5 20 ns Input Pulse Levels 0.0 - 3.0 0.45 - 2.4 V Input timing measurement reference levels 1.5 0.8, 2.0 V Output timing measurement reference levels 1.5 0.8, 2.0 V

1 TTL Gate

JEDEC Std -55 -70 90 -120 -150 Read Cycle Time3 tAVAV tRC MIN 55 70 90 120 150 ns Address to Output Delay tAVQV tACC CE\\ = VIL OE\\ = VIL MAX 55 70 90 120 150 ns Chip Enable to Output Delay tELQV tCE OE\\ = VIL MAX 55 70 90 120 150 ns Output Enable to Output Delay tGLQV tOE MAX 30 30 35 50 55 ns Chip Enable to Output High Z2, 3 tEHQZ tDF MAX 18 20 20 30 35 ns Output Enable to Output High Z2, 3 tGHQZ tDF 18 20 20 30 35 ns R e a d M I N 00000n s Toggle and Data Polling M I N 1 01 01 01 01 0 n s Output Hold Time From Addresses CE\\ or OE\\, Whichever Occurs First tAXQX tOH M I N 00000n s SPEED OPTIONS1 UNITSPARAMETER TEST SETUP Output Enable Hold Time3 tOEH SYMBOL

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. AS29F040 Rev. 2.2 09/07 Austin Semiconductor, Inc. FIGURE 8: AC CHARACTERISTICS, Read Operations Timings AC CHARACTERISTICS: Erase and Program Operations NOTES: 1. Not 100% tested. 2. See the “Erase and Programming Performance” section for more information. JEDEC Std -55 -70 90 -120 -150 Write Cycle Time1 MIN tAVAV tWC 55 70 90 120 150 ns Address Setup Time MIN tAVWL tAS ns Address Hold Time MIN tWLAX tAH 40 45 45 50 50 ns Data Setup Time MIN tDVWH tDS 25 30 45 50 50 ns Data Hold Time MIN tWHDX tDH ns Output Enable Setup Time MIN tOES ns Read Recover Time Before Write (OE\\ High to WE\\ Low) MIN t GHWL tGHWL ns CE\\ Setup Time MIN tELWL tCS ns CE\\ Hold Time MIN tWHEH tCH ns Write Pulse Width MIN tWLWH tWP 30 35 45 50 50 ns Write Pulse Width High MIN tWHWL tWPH ns Byte Programming Operation2 TYP tWHWH1 tWHWH1 µs Sector Erase Operation2 TYP tWHWH2 tWHWH2 sec VCC Set Up Time1 MIN tVCS µs SPEED OPTIONS SYMBOL PARAMETER UNITS

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. AS29F040 Rev. 2.2 09/07 Austin Semiconductor, Inc. FIGURE 13: AC CHARACTERISTICS, DQ2 vs. DQ6 NOTES: Both DQ6 and DQ2 toggle with OE\\ or CE\\. See the text on DQ6 and DQ2 in section “Write Operation Status” for more information. AC CHARACTERISTICS: Erase and Program Operations (Alternate CE\\ Controlled Writes) NOTES: 1. Not 100% tested. 2. See the “Erase and Programming Performance” section for more information. JEDEC Std -55 -70 90 -120 -150 Write Cycle Time1 MIN tAVAV tWC 55 70 90 120 150 ns Address Setup Time MIN tAVWL tAS ns Address Hold Time MIN tWLAX tAH 40 45 45 50 50 ns Data Setup Time MIN tDVWH tDS 25 30 45 50 50 ns Data Hold Time MIN tWHDX tDH ns Output Enable Setup Time MIN tOES ns Read Recover Time Before Write (OE\\ High to WE\\ Low) MIN t GHWL tGHWL ns CE\\ Setup Time MIN tELWL tCS ns CE\\ Hold Time MIN tWHEH tCH ns Write Pulse Width MIN tWLWH tWP 30 35 45 50 50 ns Write Pulse Width High MIN tWHWL tWPH ns Byte Programming Operation2 TYP tWHWH1 tWHWH1 µs Sector Erase Operation2 TYP tWHWH2 tWHWH2 sec VCC Set Up Time1 MIN tVCS µs SPEED OPTIONS SYMBOL PARAMETER UNITS

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. AS29F040 Rev. 2.2 09/07 Austin Semiconductor, Inc. FIGURE 14: AC CHARACTERISTICS, Alternate CE\\ Controlled Write Operation Timings NOTES: 1. PA = Program Address, PD = Program Data, SA = Sector Address, DQ7\\ = Complement of Data Input, D OUT = Array Data. 2. Figure indicates the last two bus cycles of the command sequence.

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. AS29F040 Rev. 2.2 09/07 Austin Semiconductor, Inc. ERASE AND PROGRAMMING PERFORMANCE NOTES: 1. Typical program and erase times assume the following conditions: 25°C, 5.0V V CC, 1 million cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90°C, V CC = 4.5V; 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes progr am faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then does the device set D Q5 = 1. See the section on DQ5 for further information. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See Table 4 for further information on command definitions. 6. The device has a minimum guaranteed erase and program cycle endurance of 1 million cycles. LATCHUP CHARACTERISTIC NOTES: Includes all pins except V CC. Test conditions: V CC = 5.0V , one pin at a time. PIN CAPACITANCE NOTES: 1. Sampled, not 100% tested. 2. Test conditions T A = 25°C, f = 1.0 MHz DATA RETENTION TYP1 MAX2 UNIT Sector Erase Time 1 8 sec Chip Erase Time 8 64 sec Byte Programming Time 7 300 µs Chip Programming Time3 3.6 10.8 sec PARAMETER LIMITS COMMENTS Excludes system-level overhead5 Excludes 00h programming prior to erasure4 PARAMETER CONDITIONS SYMBOL TYP MAX UNIT Input Capacitance VIN = 0 C IN 46 p F Output Capacitance VOUT = 0 C OUT 81 2 p F Control Pin Capacitance VPP = 0 C IN2 81 2 p F PARAMETER MIN MAX Input voltage with respect to VSS on all I/O pins -1.0V VCC + 1.0V VCC Current -100mA +100mA PARAMETER CONDITIONS MIN UNIT 150°C 10 Years 125°C 20 YearsMinimum Pattern Data Retention Time

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. AS29F040 Rev. 2.2 09/07 Austin Semiconductor, Inc. MECHANICAL DEFINITIONS* ASI Case (Package Designator CW) SMD 5962-96692, Case Outline X *All measurements are in inches. MIN MAX A 0.140 0.200 A1 0.019 0.047 A2 0.125 0.193 B 0.009 0.012 B1 0.588 0.617 D 1.654 1.686 D1 0.580 0.605 D2 1.492 1.508 e e1 0.016 0.020 SYMBOL SMD SPECIFICATIONS

0.100 BSC

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. AS29F040 Rev. 2.2 09/07 Austin Semiconductor, Inc. MECHANICAL DEFINITIONS* ASI Case (Package Designator F) SMD 5962-96692, Case Outline U *All measurements are in inches. MIN MAX A --- 0.125 b 0.015 0.019 C 0.004 0.007 D 0.810 0.830 E 0.405 0.415 E1 0.305 0.315 e L 0.380 0.420 Q 0.022 0.028 SYMBOL SMD SPECIFICATIONS

0.050 TYP

0.750 TYP

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. AS29F040 Rev. 2.2 09/07 Austin Semiconductor, Inc. MECHANICAL DEFINITIONS* ASI Case (Package Designator DCG) SMD 5962-96692, Case Outline T *All measurements are in inches. MIN MAX A --- 0.132 A1 0.095 0.125 A2 0.003 0.007 b 0.015 0.019 C 0.004 0.007 D 0.810 0.830 E 0.405 0.415 E1 0.525 0.535 E2 0.305 0.315 e eA L Q 0.022 0.028 R SYMBOL SMD SPECIFICATIONS

0.030 TYP

0.007 TYP

0.436 TYP

0.060 TYP

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. AS29F040 Rev. 2.2 09/07 Austin Semiconductor, Inc. ASI Case #208 (Package Designator ECA) MECHANICAL DEFINITION* *All measurements are in inches. AA1 L e R D E MIN MAX A 0.060 0.080 A1 0.040 0.050 B1 0.022 0.028 D 0.540 0.560 D1 0.390 0.410 E 0.442 0.458 E1 0.290 0.310 e 0.045 0.055 L 0.045 0.055 L1 0.075 0.095 R 0.004 0.014 SYMBOL SMD SPECIFICATIONS

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. AS29F040 Rev. 2.2 09/07 Austin Semiconductor, Inc. *AVAILABLE PROCESSES Temperature XT = Military Temperature Range -55 oC to +125oC IT = Industrial Temperature Range -40°C to +85°C 883C = 883C Processing -55°C to +125°C Q = QML Processing -55°C to +125°C

ORDERING INFORMATION

EXAMPLE: AS29F040CW-55/883C Device Number Package Type Speed ns Process AS29F040 CW -55 /* AS29F040 CW -60 /* AS29F040 CW -70 /* AS29F040 CW -90 /* AS29F040 CW -120 /* AS29F040 CW -150 /* EXAMPLE: AS29F040F-60/XT Device Number Package Type Speed ns Process AS29F040 F -55 /* AS29F040 F -60 /* AS29F040 F -70 /* AS29F040 F -90 /* AS29F040 F -120 /* AS29F040 F -150 /* EXAMPLE: AS29F040DCG-70/Q Device Number Package Type Speed ns Process AS29F040 DCG -55 /* AS29F040 DCG -60 /* AS29F040 DCG -70 /* AS29F040 DCG -90 /* AS29F040 DCG -120 /* AS29F040 DCG -150 /* EXAMPLE: AS29F040ECA-90/Q Device Number Package Type Speed ns Process AS29F040 ECA -55 /* AS29F040 ECA -60 /* AS29F040 ECA -70 /* AS29F040 ECA -90 /* AS29F040 ECA -120 /* AS29F040 ECA -150 /*

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. AS29F040 Rev. 2.2 09/07 Austin Semiconductor, Inc. ASI TO DSCC PART NUMBER CROSS REFERENCE* ASI Part # SMD Part # AS29F040CW-55/Q 5962-9669206HXA AS29F040CW-60/Q 5962-9669205HXA AS29F040CW-70/Q 5962-9669204HXA AS29F040CW-90/Q 5962-9669203HXA AS29F040CW-120/Q 5962-9669202HXA AS29F040CW-150/Q 5962-9669201HXA ASI Part # SMD Part # AS29F040F-55/Q 5962-9669206HUA AS29F040F-60/Q 5962-9669205HUA AS29F040F-70/Q 5962-9669204HUA AS29F040F-90/Q 5962-9669203HUA AS29F040F-120/Q 5962-9669202HUA AS29F040F-150/Q 5962-9669201HUA ASI Part # SMD Part # AS29F040DCG-55/Q 5962-9669206HTA AS29F040DCG-60/Q 5962-9669205HTA AS29F040DCG-70/Q 5962-9669204HTA AS29F040DCG-90/Q 5962-9669203HTA AS29F040DCG-120/Q 5962-9669202HTA AS29F040DCG-150/Q 5962-9669201HTA ASI Part # SMD Part # AS29F040ECA-55/Q 5962-9669206H_A AS29F040ECA-60/Q 5962-9669205H_A AS29F040ECA-70/Q 5962-9669204H_A AS29F040ECA-90/Q 5962-9669203H_A AS29F040ECA-120/Q 5962-9669202H_A AS29F040ECA-150/Q 5962-9669201H_A * ASI part number is for reference only. Orders received referencing the SMD part number will be processed per the SMD.