AS29F010F-70/IT

AS29F010 AUSTIN | Alldatasheet

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Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. AS29F010 Rev. 2.3 12/08 Austin Semiconductor, Inc. 128K x 8 FLASH UNIFORM SECTOR 5.0V FLASH MEMORY AVAILABLE AS MILITARY SPECIFICATIONS

• MIL-STD-883  SMD 5962-96690

FEATURES

 Single 5.0V ±10% power supply operation  Low power consumption: 3 12 mA typical active read current 3 30 mA typical program/erase current 3 <1 µA typical standby current  Flexible sector architecture

3 Eight 16Kbyte sectors

3 Any combination of sectors can be erased

3 Full chip erase

 Sector protection

3 Hardware-based feature that disables/reenables program

and erase operations in any combination of sectors

3 Sector protection/unprotection can be implemented

using standard PROM programming equipment  Embedded Algorithms

3 Embedded Erase algorithm automatically pre-programs

and erases the chip or any combination of designated sectors

3 Embedded Program algorithm automatically programs

and verifies data at specified address  Erase Suspend/Resume

3 Supports reading data from a sector not being erased

 Minimum 1,000,000 Program/Erase Cycles per sector guaranteed  Compatible with JEDEC standards

3 Pinout and software compatible with single-power-

3 Superior inadvertent write protection

 Data\\ Polling and Toggle Bits

3 Provides a software method of detecting program or

 Timing 50ns* -50 60ns -60 70ns -70 90ns -90 120ns -120 150ns -150  Package Ceramic DIP (600 mil) CW Flatpack F Lead Formed Flatpack DCG Small Outline J-Lead SOJ  Temperature Industrial Temperature (-40°C to +85°C) IT Military Temperature (-55°C to +125°C) XT 883C Processing (-55°C to +125°C) 883C QML Processing (-55°C to +125°C) Q NOTES: *50ns (-50) option available with IT and XT options only. For more products and information please visit our web site at www.austinsemiconductor.com PIN ASSIGNMENT (Top View) 32-PIN Ceramic DIP (CW) 32-pin Flatpack (F) 32-pin Lead Formed Flatpack (DCG) NC A16 A15 A12 DQ0 DQ1 DQ2 V SS VCC WE\\ NC A14 A13 A11 OE\\ A10 CE\\ DQ7 DQ6 DQ5 DQ4 DQ3

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. AS29F010 Rev. 2.3 12/08 Austin Semiconductor, Inc. GENERAL DESCRIPTION The AS29F010 is a 1Mbit, 5.0 V olt-only FLASH memory organized as 131,072 bytes. The AS29F010 is offered in a 32-pin CDIP package. The byte-wide data appears on DQ0-DQ7. The device is designed to be programmed in-system with the standard system 5.0 V olt V CC supply. A 12.0 volt V PP is not required for program or erase operations. The device can also be programmed or erased in standard EPROM programmers. This device is manufactured using 0.32 µm process technology. It is available with access times of 50, 60, 70, 90, 120, and 150ns, allowing high-speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE\\), write enable (WE\\), and output enable (OE\\) controls. The device requires only a single 5.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC single-power-supply FLASH standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other FLASH or EPROM devices. Device programming occurs by executing the program command sequence. This invokes the Embedded Program algorithm -- an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Device erasure occurs by executing the erase command sequence. This invokes the Embedded Erase algorithm -- an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by reading the DQ7 (Data\\Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is erased when shipped from the factory. The hardware data protection measures include a low V CC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory, and is implemented using standard EPROM programmers. The system can place the device into the standby mode. Power consumption is greatly reduced in this mode. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The bytes are programmed one byte at a time using the EPROM programming mechanism of hot electron injection. PIN CONFIGURATION PIN DESCRIPTION A0 - A16 17 Addresses DQ0 - DQ7 8 Data Inputs/Outputs CE\\ Chip Enable OE\\ Output Enable WE\\ Write Enable VCC +5 Volt Single Power Supply VSS Device Ground NC No Connect LOGIC SYMBOL

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. AS29F010 Rev. 2.3 12/08 Austin Semiconductor, Inc. FUNCTIONAL BLOCK DIAGRAM

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. AS29F010 Rev. 2.3 12/08 Austin Semiconductor, Inc. DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches that store the commands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. The appropriate device bus operations table lists the inputs and control levels required, and the resulting output. The following subsections describe each of these operations in further detail. Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE\\ and OE\\ pins to V IL. CE\\ is the power control and selects the device. OE\\ is the output control and gates array data to the output pins. WE\\ should remain at VIH. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. See “Reading Array Data” for more information. Refer to the AC Read Operations table for timing specifications and to the Read Operations Timings diagram for the timing waveforms. ICC1 in the DC Characteristics table represents the active current specification for reading array data. TABLE 1: DEVICE BUS OPERATIONS OPERATION CE\\ OE\\ WE\\ Addresses1 DQ0 - DQ7 Read L L H AIN DOUT Write L H L AIN DIN Standby VCC ± 0.5V X X X High-Z Output Disable L H H X High-Z Hardware Reset X X X X High-Z NOTES: 1. Addresses are A16:A0. 2. The sector protect and sector unprotect functions must be implemented via programming equipment. See the “Sector Protection / Unprotection” section. Writing Commands/Command Sequences To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE\\ and CE\\ to VIL, and OE\\ to VIH. An erase operation can erase one sector, multiple sectors, or the entire device. The Sector Address Tables indicate the address space that each sector occupies. A “sector address” consists of the address bits required to uniquely select a sector. See the “Command Definitions” section for details on erasing a sector or the entire chip. After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7 - DQ0. Standard read cycle timings apply in this mode. Refer to the “Autoselect Mode” and “Autoselect Command Sequence” sections for more information. I CC2 in the DC Characteristics table represents the active current specification for the write mode. The “AC Characteristics” section contains timing specification tables and timing diagrams for write operations. Program and Erase Operation Status During an erase or program operation, the system may check the status of the operation by reading the status bits on DQ7 - DQ0. Standard read cycle timings and I CC read specifications apply. Refer to “Write Operation Status” for more information, and to each AC Characteristics section in the appropriate data sheet for timing diagrams.

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. AS29F010 Rev. 2.3 12/08 Austin Semiconductor, Inc. Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE\\ input. The device enters the CMOS standby mode when the CE\\ pin is held at V CC ± 0.5V . (Note that this is a more restricted voltage range than V IH.) The device enters the TTL standby more when CE\\ is held at VIH. The device requires the standard access time (tCE) before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. ICC3 in the DC Characteristics table represents the standby current specification. Output Disable Mode When the OE\\ input is at V IH, output from the device is disabled. The output pins are placed in the high impedance state. Autoselect Mode The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7 - DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode requires V ID on address pin A9. Address pins A6, A1, and A0 must be as shown in the Autoselect Codes (High V oltage Method) table. In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits. Refer to the corresponding Sector Address Tables. The Command Definitions table shows the remaining SECTOR A16 A15 A14 ADDRESS RANGE SA0 0 0 0 00000h - 03FFFh SA1 0 0 1 04000h - 07FFFh SA2 0 1 0 08000h - 0BFFFh SA3 0 1 1 0C000h - 0FFFFh SA4 1 0 0 10000h - 13FFFh SA5 1 0 1 14000h - 17FFFh SA6 1 1 0 18000h - 1BFFFh SA7 1 1 1 1C000h - 1FFFFh TABLE 2: SECTOR ADDRESSES TABLE NOTE: All sectors are 16 Kbytes in size. address bits that are don’t care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7 - DQ0 To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in the Command Definitions table. This method does not require V ID. See “Command Definitions” for details on using the autoselect mode. Sector Protection/Unprotection The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors. Sector protection/unprotection must be implemented using programming equipment. The procedure requires a high voltage (V ID) on address pin A9 and the control pins. The device is shipped with all sectors unprotected. It is possible to determine whether a sector is protected or unprotected. See “Autoselect Mode” for details. Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to the Command Definitions table). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during V CC power-up and power-down transitions, or from system noise. Low VCC Write Inhibit When VCC is less than V LKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. AS29F010 Rev. 2.3 12/08 Austin Semiconductor, Inc. erase circuits are disabled, and the device resets. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO. Write Pulse “Glitch” Protection Noise pulses of less than 5ns (typical) on OE\\, CE\\, or WE\\ do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE\\ = VIL, CE\\ = VIH or WE\\ = VIH. To initiate a write cycle, CE\\ and WE\\ must be a logical zero while OE\\ is a logical one. Power-Up Write Inhibit If WE\\ = CE\\ = VIL and OE\\ = VIH during power up, the device does not accept commands on the rising edge of WE\\. The internal state machine is automatically reset to reading array data on power-up. COMMAND DEFINITIONS Writing specific address and data commands or sequences into the command register initiates device operations. The Command Definitions table defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. All addresses are latched on the falling edge of WE\\ or CE\\, whichever happens first. Refer to the appropriate timing diagrams in the “AC Characteristics” section. TABLE 3: Autoselect Codes (High Voltage Method) DESCRIPTION CE\\ OE\\ WE\\ A16 to A14 A13 to A10 A9 to to A1 A0 DQ7 to DQ0 Manufacturer ID L L H X X VID XLXLL 0 1 h Device ID L L H X X VID XLXLH 2 0 h 01h (protected) 00h (unprotected) LXHLSA X VID XSector Protection Verification LLH NOTE: L = Logic Low = V IL, H = Logic High = V IH, SA = Sector Address, X = Don’t Care Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm. The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high, or while in the autoselect mode. See the “Reset Command” section, next. See also “Requirements for Reading Array Data” in the “Device Bus Operations” section for more information. The Read Operations table provides the read parameters, and the Read Operation Timings diagram shows the timing diagram. Reset Command Writing the reset command to the device resets the device to reading array data. Address bits are don’t care for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data. Once programming begins, however, the device ignores reset com- mands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data. If DQ5 goes high during a program or erase operation, writing the reset command returns the device to reading array data.

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. AS29F010 Rev. 2.3 12/08 Austin Semiconductor, Inc. non-suspended sectors. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See “Write Operation Status” for more information. The system may also write the autoselect command sequence when the device is in the Erase Suspend mode. The device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the device exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation. See “Autoselect Command Sequence” for more information. The system must write the Erase Resume command (address bits are “don’t care”) to exit the erase suspend mode and continue the sector erase operation. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the device has resumed erasing. TABLE 4: Command Definitions Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data 1R A R D

1 XXXX F0

Manufacturer ID 4 555 AA 2AA 55 555 90 X00 1 Device ID 4 555 AA 2AA 55 555 90 X01 20 4 555 AA 2AA 55 555 A0 PA PD 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30

1 XXX B0

1 XXX 30

55 555 90 (SA) X024 555 AA 2AA Erase Resume Read4 Reset6 Sector Protect Verify8 Program Chip Erase Sector Erase Erase Suspend Reset5 Autoselect7 Cycles Bus Cycles2,3 First Second Third Fourth Fifth SixthCommand Sequence1 LEGEND: X = Don’t Care RA = Address of the memory location to be read RD = Data read from location RA during read operation PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE\\ or CE\\ pulse, whichever h appens later PD = Data to be programmed at location PA. Data latches on the rising edge of WE\\ or CE\\ pulse, whichever happens first SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A16-A14 uniquely select any sector. NOTES: 1. See Table 1 for description of bus operations. 2. All values are in hexadecimal. 3. Except when reading array or autoselect data, all command bus cycles are write operations. 4. No unlock or command cycles required when reading array data. 5. The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ5 goes high (wh ile the device is providing status data). 6. The device accepts the three-cycle reset command sequence for backward compatibility. 7. The fourth cycle of the autoselect command sequence is a read operation. 8. The data is 00h for an unprotected sector and 01h for a protected sector. See “Autoselect Command Sequence” for more inform ation. 9. The system may read in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspen d command is valid only during a sector erase operation. 10. The Erase Resume command is valid only during the Erase Suspend mode.

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. AS29F010 Rev. 2.3 12/08 Austin Semiconductor, Inc. selected for erasing are protected, DQ6 toggles for approximately 100µs, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. If a program address falls within a protected sector, DQ6 toggles for approximately 2µs after the program command sequence is written, then returns to reading array data. The Write Operation Status table shows the outputs for Toggle Bit I on DQ6. Refer to Figure 4 for the toggle bit algorithm, and to the Toggle Bit Timings figure in the “AC Characteristics” section for the timing diagram. Reading Toggle Bit DQ6 Refer to Figure 4 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7-DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, a system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7-DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit it toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 4). DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a “1.” This is a failure condition that indicates the program or erase cycle was not successfully completed. The DQ5 failure condition may appear if the system tries to program a “1” to a location that is previously programmed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition, the device halts the operation, and when the operation has exceeded the timing limits, DQ5 produces a “1.” Under both these conditions, the system must issue the reset command to return the device to reading array data. NOTE: 1) Read toggle bit twice to determine whether or not it is toggling. See text. 2) Recheck toggle bit because it may stop toggling as DQ5 changes to “1”. See text. FIGURE 4: TOGGLE BIT ALGORITHM

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. AS29F010 Rev. 2.3 12/08 Austin Semiconductor, Inc. DC CHARACTERISTICS: TTL/NMOS Compatible PARAMETER DESCRIPTION SYM MIN TYP MAX UNIT Input Load Current VIN = VSS to VCC, VCC = VCC Max I LI ±5.0 µA A9 Input Load Current VCC = VCC Max, A9 = 12.5V I LIT 100 µA Output Leakage Current VOUT = VSS to VCC, VCC = VCC Max I LO ±5.0 µA VCC Active Read Current1,2 CE\\ = VIL, OE\\ = VIH ICC1 12 35 mA VCC Active Write Current2,3,4 CE\\ = VIL, OE\\ = VIH ICC2 30 50 mA VCC Standby Current CE\\ and OE\\ = V IH ICC3 0.4 5.0 mA Input Low Voltage VIL -0.5 0.8 V Input High Voltage VIH 2.0 VCC + 0.5 V Voltage for Autoselect and Sector Protect VCC = 5.0V V ID 10.5 12.5 V Output Low Voltage IOL = 12 mA, VCC = VCC Min V OL 0.45 V Output High Voltage IOH = -2.5 mA, VCC = VCC Min V OH 2.4 V Low VCC Lock-out Voltage V LKO 3.2 V NOTES: 1. The I CC current listed is typically less than 2mA/MHz, with OE\\ at V IH. 2. Maximum I CC specifications are tested with V CC = V CC Max 3. I CC active while Embedded Program or Embedded Erase Algorithm is in progress. 4. Not 100% tested. DC CHARACTERISTICS: CMOS Compatible PARAMETER DESCRIPTION SYM MIN TYP MAX UNIT Input Load Current VIN = VSS to VCC, VCC = VCC Max I LI ±5.0 µA A9 Input Load Current VCC = VCC Max, A9 = 12.5V I LIT 50 µA Output Leakage Current VOUT = VSS to VCC, VCC = VCC Max I LO ±5.0 µA VCC Active Current1,2 CE\\ = VIL, OE\\ = VIH ICC1 35 mA VCC Active Current2,3,4 CE\\ = VIL, OE\\ = VIH ICC2 50 mA VCC Standby Current CE\\ = V CC ± 0.5V, OE\\ = VIH ICC3 1.6 mA Input Low Voltage VIL -0.5 0.8 V Input High Voltage V IH 0.7 x VCC VCC + 0.3 V Voltage for Autoselect and Sector Protect VCC = 5.25V V ID 10.5 12.5 V Output Low Voltage IOL = 12 mA, VCC = VCC Min V OL 0.45 V IOH = -2.5 mA, VCC = VCC Min V OH1 0.85 VCC V IOH = -100 µA, VCC = VCC Min V OH2 VCC - 0.4 Low VCC Lock-out Voltage V LKO 3.2 V Output High Voltage

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. AS29F010 Rev. 2.3 12/08 Austin Semiconductor, Inc. TABLE 6: TEST CONDITIONS, Test Specifications CONDITIONS ALL SPEEDS UNIT Output Load Output Load Capacitance, CL (including jig capacitance) 50 pF Input Rise and Fall Times 5 ns Input Pulse Levels 0/3 V Input timing measurement reference levels 1.5 V Output timing measurement reference levels 1.5 V

1 TTL Gate

AC CHARACTERISTICS: Read-Only Operations FIGURE 7: TEST CONDITIONS, Test Setup JEDEC Std -50 -60 -70 90 -120 -150 Read Cycle Time1 tAVAV tRC M I N 5 06 07 09 0 1 2 0 1 5 0n s Address to Output Delay tAVQV tACC CE\\ = VIL OE\\ = VIL MAX 50 60 70 90 120 150 ns Chip Enable to Output Delay tELQV tCE OE\\ = VIL MAX 50 60 70 90 120 150 ns Output Enable to Output Delay tGLQV tOE MAX 25 30 35 40 50 55 ns Chip Enable to Output High Z1 tEHQZ tDF MAX 15 20 20 25 30 35 ns Output Enable to Output High Z1 tGHQZ tDF MAX 15 20 20 25 30 35 ns Read MIN ns Toggle and Data Polling MIN ns Output Hold Time From Addresses CE\\ or OE\\, Whichever Occurs First t AXQX tOH MIN ns PARAMETER TEST SETUP Output Enable Hold Time1 tOEH SYMBOL UNITS SPEED OPTIONS NOTES: 1. Not 100% tested. 2. See Figure 7 and Table 6 for test specifications.

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. AS29F010 Rev. 2.3 12/08 Austin Semiconductor, Inc. FIGURE 8: AC CHARACTERISTICS, Read Operations Timings AC CHARACTERISTICS: Erase and Program Operations NOTES: 1. Not 100% tested. 2. See the “Erase and Programming Performance” section for more information. JEDEC Std -50 -60 -70 90 -120 -150 Write Cycle Time1 MIN tAVAV tWC 50 60 70 90 120 150 ns Address Setup Time MIN tAVWL tAS ns Address Hold Time MIN tWLAX tAH 40 45 45 45 50 50 ns Data Setup Time MIN tDVWH tDS 25 30 30 45 50 50 ns Data Hold Time MIN tWHDX tDH ns Output Enable Setup Time MIN tOES ns Read Recover Time Before Write (OE\\ High to WE\\ Low) MIN t GHWL tGHWL ns CE\\ Setup Time MIN tELWL tCS ns CE\\ Hold Time MIN tWHEH tCH ns Write Pulse Width MIN tWLWH tWP 25 30 35 45 50 50 ns Write Pulse Width High MIN tWHWL tWPH ns Byte Programming Operation2 MIN tWHWH1 tWHWH1 µs Chip/Sector Erase Operation2 MAX tWHWH2 tWHWH2 sec VCC Set Up Time1 MIN tVCS µs SYMBOL PARAMETER UNITS SPEED OPTIONS

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. AS29F010 Rev. 2.3 12/08 Austin Semiconductor, Inc. AC CHARACTERISTICS: Erase and Program Operations JEDEC Std -50 -60 -70 90 -120 -150 Write Cycle Time1 MIN tAVAV tWC 50 60 70 90 120 150 ns Address Setup Time MIN tAVEL tAS ns Address Hold Time MIN tELAX tAH 40 45 45 45 50 50 ns Data Setup Time MIN tDVEH tDS 25 30 30 45 50 50 ns Data Hold Time MIN tEHDX tDH ns Output Enable Setup Time1 MIN tOES ns Read Recover Time Before Write MIN tGHEL tGHEL ns WE\\ Setup Time MIN tWLEL tWS ns WE\\ Hold Time MIN tEHWH tWH ns CE\\ Pulse Width MIN tELEH tCP 25 30 35 45 50 50 ns CE\\ Pulse Width High MIN tEHEL tCPH ns Byte Programming Operation2 MIN tWHWH1 tWHWH1 µs Chip/Sector Erase Operation2 MAX tWHWH2 tWHWH2 sec SYMBOL PARAMETER UNITS SPEED OPTIONS NOTES: 1. Not 100% tested. 2. See the “Erase and Programming Performance” section for more information. FIGURE 13: AC CHARACTERISTICS, Alternate CE\\ Controlled Write Operation Timings NOTES: 1. PA = program address, PD = program data, SA = sector address, DQ7\\ = complement of data input, D OUT = array data. 2. Figure indicates the last two bus cycles of the command sequence.

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. AS29F010 Rev. 2.3 12/08 Austin Semiconductor, Inc. ERASE AND PROGRAMMING PERFORMANCE TYP1 MAX2 UNIT Chip/Sector Erase Time 1.0 15 sec Excludes 00h programming prior to erasure4 Byte Programming Time 7 300 µs Chip Programming Time3 0.9 6.25 sec PARAMETER LIMITS COMMENTS Excludes system-level overhead5 NOTES: 1. Typical program and erase times assume the following conditions: 25°C, 5.0V V CC, 1 million cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90°C, V CC = 4.5V , 100,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes progr am faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then does the device set D Q5 = 1. See the section on DQ5 for further information. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See Table 4 for further information on command definitions. 6. The device has a minimum guaranteed erase cycle endurance of 1 million cycles. LATCHUP CHARACTERISTIC PARAMETER MIN MAX Input voltage with respect to VSS on I/O pins -1.0V VCC + 1.0V VCC Current -100mA +100mA NOTES: Includes all pins except V CC. Test conditions: V CC = 5.0V , one pin at a time. PIN CAPACITANCE PARAMETER CONDITIONS SYMBOL MAX UNIT Input Capacitance VIN = 0 C IN 15 pF Output Capacitance VOUT = 0 C OUT 15 pF Control Pin Capacitance VPP = 0 C IN2 15 pF NOTES: 1. Sampled, not 100% tested. 2. Test conditions T A = 25°C, f = 1.0 MHz DATA RETENTION PARAMETER CO NDITIONS MIN UNIT 150°C 10 Years 125°C 20 YearsMinimum Pattern Data Retention Time

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. AS29F010 Rev. 2.3 12/08 Austin Semiconductor, Inc. MECHANICAL DEFINITIONS* ASI Case (Package Designator CW) SMD 5962-96690, Case Outline Y *All measurements are in inches.

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. AS29F010 Rev. 2.3 12/08 Austin Semiconductor, Inc. MECHANICAL DEFINITIONS* ASI Case (Package Designator F) SMD 5962-96690, Case Outline T *All measurements are in inches. MIN MAX A --- 0.125 b 0.015 0.019 C 0.004 0.007 D 0.810 0.830 D1 0.745 0.755 E 0.405 0.415 E1 0.305 0.315 e L 0.380 0.420 Q 0.022 0.028 SYMBOL SMD SPECIFICATIONS

0.050 TYP

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. AS29F010 Rev. 2.3 12/08 Austin Semiconductor, Inc. MECHANICAL DEFINITIONS* ASI Case (Package Designator DCG) SMD 5962-96690, Case Outline U *All measurements are in inches. MIN MAX A --- 0.132 A1 0.095 0.125 A2 0.003 0.007 b 0.015 0.019 C 0.004 0.007 D 0.810 0.830 E 0.405 0.415 E1 0.525 0.535 E2 0.305 0.315 e eA L Q 0.022 0.028 R 0.007 TYP

0.436 TYP

0.060 TYP

0.750 TYP

0.030 TYP

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. AS29F010 Rev. 2.3 12/08 Austin Semiconductor, Inc. MECHANICAL DEFINITIONS* ASI Case (Package Designator SOJ) SMD 5962-96690, Case Outline X *All measurements are in inches.

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. AS29F010 Rev. 2.3 12/08 Austin Semiconductor, Inc. *AVAILABLE PROCESSES XT = Military Temperature Range -55 oC to +125oC IT = Industrial Temperature Range -40°C to +85°C 883C = 883C Processing -55°C to +125°C Q = QML Processing -55°C to +125°C **NOTE: 50ns (-50) option available with IT and XT options only.

ORDERING INFORMATION

EXAMPLE: AS29F010CW-90/883C EXAMPLE: AS29F010F-120/XT EXAMPLE: AS29F010DCG-70/Q EXAMPLE: AS29F010SOJ-55/XT Device Number Package Type Speed ns Process AS29F010 CW -50** /* AS29F010 CW -60 /* AS29F010 CW -70 /* AS29F010 CW -90 /* AS29F010 CW -120 /* AS29F010 CW -150 /* AS29F010 F -60 /* AS29F010 F -70 /* AS29F010 F -90 /* AS29F010 F -120 /* AS29F010 F -150 /* AS29F010 DCG -50** /* AS29F010 DCG -60 /* AS29F010 DCG -70 /* AS29F010 DCG -90 /* AS29F010 DCG -120 /* AS29F010 DCG -150 /* AS29F010 SOJ -50** /* AS29F010 SOJ -60 /* AS29F010 SOJ -70 /* AS29F010 SOJ -90 /* AS29F010 SOJ -120 /* AS29F010 SOJ -150 /*

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. AS29F010 Rev. 2.3 12/08 Austin Semiconductor, Inc. ASI TO DSCC PART NUMBER CROSS REFERENCE* ASI Part # SMD Part # AS29F010CW-60/Q 5962-9669005HYA AS29F010CW-70/Q 5962-9669004HYA AS29F010CW-90/Q 5962-9669003HYA AS29F010CW-120/Q 5962-9669002HYA AS29F010CW-150/Q 5962-9669001HYA ASI Part # SMD Part # AS29F010F-60/Q 5962-9669005HTA AS29F010F-70/Q 5962-9669004HTA AS29F010F-90/Q 5962-9669003HTA AS29F010F-120/Q 5962-9669002HTA AS29F010F-150/Q 5962-9669001HTA ASI Part # SMD Part # AS29F010DCG-60/Q 5962-9669005HUA AS29F010DCG-70/Q 5962-9669004HUA AS29F010DCG-90/Q 5962-9669003HUA AS29F010DCG-120/Q 5962-9669002HUA AS29F010DCG-150/Q 5962-9669001HUA * ASI part number is for reference only. Orders received referencing the SMD part number will be processed per the SMD.

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. AS29F010 Rev. 2.3 12/08 Austin Semiconductor, Inc. DOCUMENT TITLE 128K x 8 FLASH UNIFORM SECTOR 5.0V FLASH MEMORY

REVISION HISTORY

Rev # History Release Date Status

2.3 Changed MAX value from 60 to 15 December 2008 Release

corrections on page 15 &18