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www.cypress.com Document No. 001-95089 Rev. *A 1 AN95089 PSoC® 4/PRoC™ BLE Crystal Oscillator Selection and Tuning Techniques Author: Prakhar Agarwal Associated Part Family: CY 8C4XX 7-BL, CY8C4xx8 -BL, CYBL10 X6X, CYBL10x7x Related Application Notes: None AN95089 provides insights into the selection and tuning of the external crystal oscillator (ECO) and watch crystal oscillator (WCO) for PSoC 4/ PRoC BLE devices to achieve a good RF performance. This application note introduces basics of crystals and clock accuracy measurements. Cypress -recommended crystals and tuning techniques for optimum performance are also discussed.
Contents
3 Effects of Inaccurate ECO Crystal Frequency
13 Appendix: Frequency Error
1 Introduction
This application note helps you select the ECO crystal and the WCO crystal for PSoC 4/PRoC BLE devices and tune them for optimum performance. Bluetooth Low Energy (BLE) is a timing -sensitive technology in which an inaccurate ECO clock can degrade the physical layer RF performance; similarly, an inaccurate WCO clock can lead to increased power consumption in a peripheral. The on-chip ECO circuit with an external crystal is used to synthesize a 24-MHz clock to run the BLE subsystem. The clock sets the protocol timing for link-layer operations and derives the carrier frequency for physical-layer RF circuits. An external WCO crystal is used to derive the 32.768-kHz clock that maintains link-layer timing synchronization when the BLE subsystem is in a low-power mode.
2 Crystal Oscillator Basics
2.1 Crystal Oscillator Circuitry
Figure 1. Basic Crystal Oscillator Circuit phase shift and a voltage gain from the output to input at approximately the resonant frequency of the crystal. causing it to function as a high-gain inverting amplifier.
2.2 Load Cap Value (CL)
The load capacitance is the total capacitance seen by the crystal looking into the rest of the circuit (see Figure 2). Figure 2. Load Capacitance composed of not only the two capacitors C1 and C2, but also the parasitic capacitances and pin capacitances.
Figure 3. Total Load Capacitance Including Parasitic Capacitance and Pin Capacitance The load capacitance required to generate an accurate crystal frequency is spe cified in the crystal datasheet. that the chosen crystal has 8-pF load capacitance.
2.3 Crystal Equivalent RLC Circuit
Figure 4 shows the equivalent RLC circuit of the crystal. Figure 4. Equivalent RLC Circuit of the Crystal is the series resonant frequency of the oscillator and is the frequency of oscillation.
2.3.1 Equivalent Se ries Resistance (ESR )
biasing point of the amplifier becomes unstable, resulting in oscillations.
PSoC® 4/PRoC™ BLE Crystal Oscillator Selection and Tuning Techniques www.cypress.com Document No. 001-95089 Rev. *A 5
2.4 Drive Level
This is a measure of the amount of power dissipated (in µW) across the crystal. The maximum drive level is the maximum power a crystal can dissipate while still maintaining the specified performance. A high drive-level causes problems such as instability and aging. The drive level should be considered in your design to avoid premature aging and damage to the crystal. You should choose a crystal whose drive level specification meets your design drive level requirement.
2.5 PPM Error
The crystal clock accuracy is usually defined in parts per million (ppm) , which means the inaccuracy in the number of clock cycles measured per 106 (1 million) clock cycles. Equation 4: For example, if a 24-MHz crystal oscillator provides a clock of 23.999928 MHz, then the clock accuracy is -72/24 = -3 ppm There are many reasons for ppm variation. Some of these are discussed below: Initial Tolerance (ppm): The deviation from the nominal crystal frequency for different devices under identical conditions (temperature, PCB layout, voltage, etc). This is a datasheet parameter. Temperature Drift (ppm): The deviation from the nominal crystal frequency over temperature. Aging (ppm/year): The cumulative change in the frequency of oscillation experienced by a crystal over a year. The variation due to aging may be different in different years. This may be +/- 1 ppm for the first year and +/- 20 ppm after 15 years. Pullability: This is the change in crystal oscillator f requency due to a change in the load capacitance . It is typically 20 ppm/pF. The parasitic load capacitance varies between 2.5 to 3.5 pF, which can cause the ppm to shift outside the BLE spec ification limit of +/ -50 ppm. Therefore, the board parasitic capacitance should also be considered while choosing the load capacitor value for the crystal. Parasitic Capacitance: Stray capacitances from the PCB and pin input add to the overall parasitic capacitance seen by the crystal. This parasitic capacitance changes the load capacitance value.
3 Effects of Inaccurate ECO Crystal Frequency on RF Performance
The data transmitted over BLE has a symbol rate of 1 mega-symbol per second (symbol timing of 1 µs), where a symbol refers to one bit of baseband signal that modulates the carrier . The symbol timing accuracy should be better than ± 50 ppm. In addition, the deviation in the RF center frequency during a packet transmission should not exceed ± 150 kHz ( See Appendix: Frequency Error (Transmit Center Frequency Tolerance) ).The symbol timing and the centre frequency are both derived from the 24 -MHz crystal oscillator. Therefore, you should use a crystal that meets the BLE specification because the deviation in the crystal oscillator clock directly impacts the RF performance. A higher RF center-frequency deviation of the transmitter increases transmission leakages in adjacent channels that result in the following: Higher interference for receivers in adjacent channels Possibility of not meeting the radio specifications Increase in the spurious spillover in the adjacent channel that could result in failures in a band-edge test A higher frequency-deviation of the receiver with respect to the transmitter could cause a part of the received energy to fall outside the bandwidth of the baseband filter. This causes valid signal energy to be lost in the filter and results in a reduced sensitivity (and hence a reduced range). For GFSK receivers, the frequency deviation also causes a DC shift in the demodulated output and could result in the decoded symbols to be erroneous This results in a higher PER (packet error rate) and reduced sensitivity. Apart from these, a higher frequency -deviation of the receiver makes the receiver move closer to the adjacent channel. Consequently, signals in adjacent channels impact the reception, thus reducing the selectivity.
power-level up to which the receiver can receive packets with a maximum of 30. 8 percent packet error rate (PER). ECO clock drifts beyond ± 20 ppm. 30.8 percent PER. The C/I ratio can degrade by as much as 5 to 8 dBm if the ECO clock is inaccurate by -20 ppm. Oscillator Basics. This requires the ability to tune the ppm to ensure a good RF performance.
4 Crystal Tuning Technique for ECO
tuned by firmware to correct the load capacitance offset, and therefore the frequency. Figure 5. Internal Programmable Trim Capacitors in PSoC 4/PRoC BLE Devices (Model SR620 from Stanford Research Systems). Equation 4 gives the clock ppm deviation. register writes (which effectively change the overall CL seen by the crystal) to bring the clock to the required ppm.
PSoC® 4/PRoC™ BLE Crystal Oscillator Selection and Tuning Techniques www.cypress.com Document No. 001-95089 Rev. *A 7
4.1 Steps to Correct Clock Inaccuracy
Step 1: Enable radio Step 2: Enable WCO Step 3: Enable ECO Step 4: Bring the ECO clock on a GPIO and observe the clock accuracy (Example - clock on Port 2 Pin 7) Step 5: Trim the internal capacitance to achieve 0 ppm Function Code: void trim_capacitance() /* Step1:Enable Radio */ *(uint32*) CYREG_BLE_BLESS_RF_CONFIG = 0x01; /* Step2:Enable WCO */ *(uint32*) CYREG_BLE_BLESS_WCO_CONFIG |= 0x80000000; /* Step3:Enable ECO */ *(uint32*) CYREG_BLE_BLERD_DBUS = 0xC992; /* Step4:Configure pin 2[7] as ECO crystal Output */ *(uint32*) CYREG_GPIO_PRT2_PC = 0xDB6DB6; *(uint32*) CYREG_HSIOM_PORT_SEL2 |= 0xA0000000; /* Step5:Trim Load Capacitance */ *(uint32*) CYREG_BLE_BLERD_BB_XO_CAPTRIM = <Load Cap value >; Details for the se registers are available in PSoC 4/PRoC BLE Registers Technical Reference Manuals (TRMs): PSoC 4 BLE registers TRM and PRoC BLE registers TRM The load capacitance value in step 5 is a 16-bit hex value. Each bit adds 0.1011 pF capacitance. Bits 15-8 together control the capacitance at the XI node. Bits 14 – 8 are used for fine control of the capacitance value at the XI node. Decimal Value of Bits 14-8 Capacitance Value C1 0 3.6900 pF 1 3.7911 pF 2 3.8922 pF ……. …….. 127 16.428 pF Bit 15 is used for coarse control of the capacitance value at the XI node. Bit 15 = 0 means that no additional capacitance is turned ON at the XI node. Bit 15 = 1 means that an additional capacitance of 8.1 pF is turned ON at the XI node. Bits 7-0 together control the capacitance at the XO node. Bits 6-0 are used for fine control of the capacitance value at the XO node.
Bit 7 is used for coarse control of the capacitance value at the XO node. Bit 7 = 0 means that no additional capacitance is turned ON at the XO node. Bit 7 = 1 means that an additional capacitance of 8.1 pF is turned ON at the XO node. Changes in C1 and C2 result in a change in CL. Therefore, both values should be changed to tune the crystal properly. For optimal phase noise, the total capacitance on the XI pin should be 0.8 times the total capacitance on the XO pin. layout after tuning the CL for one board. Table 1. ppm Variation Across Boards for the Same CL
Figure 6. ppm Variation Across Boards for the Same CL tune a board once and use the same capacitance trim value for boards with the same PCB layout. initialization in the application, so that the register holds the updated trim value. This sequence is shown below.
6 Crystal Analysis for ECO
6.1 Frequency Variation with Temperature
Figure 7 shows the frequency variation that was measured for different crystals with temperature. Figure 7. ppm Variation with Temperature crystal ppm. Therefore, the cumulative effect of all these factors on ppm should be within ± 50 ppm.
6.2 Frequency Variation with Load Cap Value
Figure 8 shows the frequency variation for crystals that were measured with the load capacitance value. Figure 8. ppm Variation with Load Cap Value capacitance on the board are discussed in Layout Considerations for PCB section.
7 Recommendation for ECO
- Equivalent series resistance (ESR): The ESR requirement for PSoC 4/PRoC BLE devices is maximum 60 Ω at
24 MHz. Therefore, the crystal ESR should be ≤ 60 Ω.
- Drive level : The drive-level specification for PS oC 4/PRoC BLE devices is maximum 100 µW, so the chosen
specification is ≥ 100 µW (meaning that it can sustain at least 100 µW) would suffice.
- Load Capacitance: The load capacitance of the chosen crystal should be 8 pF.
- Pullability: Pullability should be low . If not, parasitic capacitances will cause a large variation in the crystal
- ppm variation across temperature range of the device: Temperature range for PSoC 4/PRoC BLE devices is
supported temperature range. Table 2 summarizes the crystals that were used for the characterization. Table 2. Drive Level and ESR Values for Different Crystals tune the crystal to be accurate within ± 10 ppm to achieve the best RF performance.
8 Crystal Analysis for WCO
8.1 Frequency Variation with Temperature
temperature for a typical external WCO crystal. Figure 9. ppm Variation with Temperature
at the link layer, thus consuming extra power.
8.2 Start-Up Time and ESR
the hibernate or stop mode, then the entire WCO startup sequence is initiated again because the chip is reset. Crystal amplitude in HPM is limited to approximately 1-V pp while in LPM it is limited to approximately 0.12 V pp. have to do this in the application code. Figure 10. PAD Voltages in Power Modes for WCO manufacturers’ ESR ranges from 35 to 70 kΩ.
8.3 Load Capacitance
Figure 11. External Application View of PSoC 4/PRoC BLE Devices A higher C1/C2 ratio results in a higher current consumption but improved duty cycle.
8.4 CL and Clock Accuracy
account the parasitic capacitance of each leg while calculating the load capacitance. change is very small, then only C2 can be changed. change is very small, then only C2 can be changed.
8.5 Frequency Variation Across Boards
tuned capacitor values are used for all the boards. Table 3. ppm Across Boards for 2:1 Cap Ratio
Figure 12. ppm Variation Across Boards for Same Load Capacitances theboards during production.
9 Recommendations for WCO
- ESR: It should be a maximum of 70 kΩ for the correct operation of the crystal circuitry. A higher ESR means a
- Drive Level: The maximum drive level of the crystal should be ≥ 1 µW.
- ppm variation across the device temperature range: The less the ppm variation , the better it is for power
after meeting the 2:1 ratio recommendation for load capacitance values.
- Size: The s ize of the crystal should be chosen such that it is as small as possible, while meeting three
requirements listed earlier. The ESR of the crystal varies inversely with the crystal size. Table 4. ESR and Size for WCO Crystals
10 Layout Considerations for PCB
trace width, which would consequently alter the load cap value resulting in clock inaccuracy. 2 Minimize the pin-to-pin stray capacitance by having a ground shield trace between pin-connected traces. ground plane without unnecessary vias on the crystal input/output traces. 4 Avoid floating pads of conductor near the crystal because this may introduce a stray capacitance. 5 Surround crystal components by a ground fill to avoid electromagnetic interference. 6 Keep fast-switching and high-current traces and pins such as LEDs away from the crystal circuitry.
7 Route PCB traces symmetrically to have the same parasitic capacitance on both crystal pins. Figure 13. PCB layout with Crystals
11 Summary
The BLE protocol requires that the ECO crystal clock accuracy is within ± 50 ppm. An inaccurate ECO crystal frequency results in poor RF performance. An inaccurate WCO crystal frequency results in high current consumption. The ECO crystal frequency inaccuracy can be corrected by following the 5-step process. Tuning is not required for every board and need to be done only once during development. Temperature, aging, and parasitic capacitance cause variations in the crystal clock accuracy. The crystal should be positioned close to the chip to minimize parasitic capacitances.
12 References
PSoC® 4/PRoC™ BLE Crystal Oscillator Selection and Tuning Techniques www.cypress.com Document No. 001-95089 Rev. *A 16 ECO Crystal Datasheets ECS-240-8-36CKM from ECS Inc TSX-3225 from Epson NX2520SA from NDK DSX321SH from KDS WCO Crystal Datasheets ECS-.327-12.5-34B from ECS CM315 from Citizen ECS-.327-12.5-32-TR from ECS About the Author Name: Prakhar Agarwal Title: Background: Systems Engineer Prakhar Agarwal received his B.E. (Hons) degree in Electronics and Instrumentation from Birla Institute of Technology and Science (BITS, PILANI).
PSoC® 4/PRoC™ BLE Crystal Oscillator Selection and Tuning Techniques www.cypress.com Document No. 001-95089 Rev. *A 17
13 Appendix: Frequency Error (Transmit Center Frequency Tolerance)
In BLE, the deviation of the RF center frequency during the packet transmission should not exceed ±150 kHz for the whole packet. For example, when a radio transmits at the center frequency of 2480 MHz, it could be 2479.850 MHz, or 2480.150 MHz. This is the tolerance in the center frequency when transmitting a packet. The center frequency is derived from the 24-MHz ECO and therefore any inaccuracies in the crystal frequency would be multiplied up to the center frequency. The clock accuracy requirement after taking into account all the factors that affect clock accuracy is
PSoC® 4/PRoC™ BLE Crystal Oscillator Selection and Tuning Techniques www.cypress.com Document No. 001-95089 Rev. *A 18 Document History Document Title: AN95089 – PSoC® 4/PRoC™ BLE Crystal Oscillator Selection and Tuning Techniques Document Number: 001-95089 Revision ECN Orig. of Change Submission Date Description of Change ** 4643683 PKAG 01/29/2015 New Application Note. *A 4764564 PKAG 05/15/2015 Updated template Updated associated part families
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