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www.cypress.com Document No. 001-91267 Rev. *D 1 AN91267 Getting Started with PSoC® 4 BLE Author: Krishnaprasad M V (KRIS) Associated PSoC Creator ™ Project: Yes Associated Part Family : CY8C41 x7-BL, CY8C42x7 -BL, CY8C41x8 -BL, CY8C42x8 -BL Software Version: PSoC Creator 3.2 Related Application Notes: For a complete list of the application notes, click here. To get the latest version of this application note, please visit http://www.cypress.com/go/AN91267 . AN91267 introduces you to PSoC ® 4 BLE, an ARM ® Cortex™-M0 based Programmable System-on-Chip (PSoC) that integrates a Bluetooth Low Energy (BLE) radio system. This application note helps you explore the PSoC 4 BLE architecture and development tools and shows how easily you can create a BLE design using PSoC Creator™, the development tool for PSoC 4 BLE. It also guides you to more resources to accelerate in-depth learning about PSoC 4 BLE.
Contents
Logical Link Control and Adaptation Protocol (L2CAP)
Getting Started with PSoC® 4 BLE www.cypress.com Document No. 001-91267 Rev. *D 2 Introduction BLE is an ultra -low-power wireless standard defined by the Bluetooth Special Interest Group (SIG) for short-range communication. It features a physical layer, protocol stack, and application use cases, all designed and optimized for the lowest power consumption. The Cypress PSoC 4 BLE device is a programmable embedded system -on-chip that integrates a BLE radio, programmable analog and digital peripheral s, memory , and an ARM Cortex-M0 microcontroller on a single chip. PSoC 4 BLE provides a cost -effective alternative to the combination of an MCU and an external BLE radio. In addition to reducing the overall system cost and size, t he programmable analog and digital subsystems allow flexibility and fine -tuning of the design using PSoC Creator, the schematic-based design tool for designing applications for PSoC 4 BLE. PSoC 4 BLE simplifies the RF board design with its integrated balun circuit , which reduces the number of external components required for antenna matching. The BLE protocol stack library is integrated with PSoC Creator and is free of cost. It can be easily configured using a simple graphical user interface (GUI), allowing you to jump-start your BLE design in minutes. PSoC 4 BLE offers a current consumption of 150 nA while retaining the SRAM contents, programmable logic, and the ability to wake up from an interrupt. It consumes only 1.3 µA in Deep-Sleep mode while maintaining the BLE link active. A combination of these low -power modes and flexible analog and digital peripherals provides a single chip solution with best-in-class system power consumption for battery-operated BLE designs such as wearable fitness monitors and wireless sensor interfaces. Cypress’s capacitive touch -sensing feature in PSoC 4 BLE, known as CapSense ®, offers unprecedented signal - to-noise ratio , best-in-class waterproofing , and a wide variety of sensor types such as buttons, sliders, track pads, and proximity sensors that are gaining popularity in wearable electronic devices such as activity monitors and health and fitness equipment. In addition to PSoC 4 BLE, Cypress offers PRoC ™ BLE, a fixed-function BLE device that focuses on human interface device design s such as keyboards, mice, and remote controls. See the Getting Started with PRoC BLE application note for details . See Appendix A: BLE Device Family Comparison for a comparison of the BLE device families from Cypress. The Cypress PSoC portfolio also contains PSoC 1, PSoC 3, PSoC 4 , and PSoC 5LP, which do not support BLE. These devices offer different system architectures and analog and digital peripherals. For more information, refer to the Cypress Platform PSoC Solutions Roadmap. PSoC Resources Cypress provides a wealth of data at www.cypress.com to help you to select the right PSoC device and quickly and effectively integrate it into your design. If you are a first - time user of Cypress ’s PSoC family of products, it is recommended that you read Appendix B: Cypress Term s of Art for a list of commonly used terms. For a comprehensive list of resources, see KBA86521, How to Design with PSoC 3, PSoC 4, and PSoC 5LP. Following is an abbreviated list for PSoC 4 BLE: Overview: PSoC Portfolio, PSoC Roadmap Product Selectors: PSoC 1, PSoC 3, PSoC 4, or PSoC 5LP. In addition, PSoC Creator includes a device selection tool. Datasheets: Describe and provide electrical specifications for the PSoC 41XX-BL and PSoC 42XX-BL device families. Application Notes and Code Examples : Cover a broad range of topics , from basic to advanced level. Many of the application notes include code examples. PSoC Creator provides additional code examples — see Code Examples. Technical Reference Manuals (T RMs): Provide detailed descriptions of the architecture and registers in each PSoC 4 BLE device family. CapSense Design Guide : Learn how to design capacitive touch-sensing applications with the PSoC 4 BLE family of devices. Development Tools CY8CKIT-042-BLE Bluetooth Low Energy (BLE) Pioneer Kit is an easy-to-use and inexpensive development platform for BLE . This kit includes connectors for Arduino™ compatible shields and Digilent® Pmod™ daughter cards. CySmart BLE Host Emulat ion Tool for Windows, iOS, and Android is an easy -to-use GUI that enables you to test and debug your B LE Peripheral applications. See Appendix C: Cypress BLE Development Tools for an overview. Technical Support Frequently As ked Questions (FAQs) : Learn more about our BLE ecosystem BLE Forum : See if your question is already answered by fellow developers on the PSoC 4 BLE and PRoC BLE forums. Cypress support: Still no luck ? Visit our support page and create a technical support case or contact a local sales representative . If you are in the United States, you can talk to our tec hnical support team by calling our toll -free number : +1- 800-541-4736. Select option 8 at the prompt.
- Drag and drop Components to build your hardware
system design in the main design workspace.
- Co-design your application firmware with the PSoC
- Configure the Components using configuration tools.
- Explore the library of more than 100 Components.
- Review the Component datasheets.
Figure 1. PSoC Creator Schematic Entry and Components how to configure and use PSoC Creator Components. unique features of PSoC 4 BLE. describes the system functions provided by PSoC Creator. Datasheets page for a list of all PSoC 4 BLE Component datasheets. resources. To open the document manager, choose the menu item Help > Document Manager.
in other device families; see Table 2. family datasheet, TRM, and application notes. Figure 4. PSoC 4 BLE Architecture (CY8C4248-BL)
48 MHz
2.4 GHz
Getting Started with PSoC® 4 BLE www.cypress.com Document No. 001-91267 Rev. *D 6 BLE Overview BLE or Bluetooth Smart TM is a low-power, short-range, low-data-rate wireless communication protocol that is defined by the Bluetooth SIG. As shown in Figure 5, BLE has a layered protocol stack that is designed to e fficiently transfer a small chunk of data with low power consumption, making it the de facto wireless protocol for battery-operated devices. The BLE stack consists of the following: 2.4-GHz RF physical layer (PHY) with a 1-Mbps data rate Link Layer (LL) that defines the timing and packet format for PHY Host Control Interface (HCI) that links the hardware controller (PHY + LL) layer with the firmware host layer of the stack Logical Link Control and Adaptation Protocol (L2CAP) that acts as a packet assembly /disassembly and protocol multiplexer layer Attribute Protocol (ATT) that defines how the application data is organized and accessed Security Manager (SM) that provides a toolbox for secure data exchange over the BLE link Generic Attribute Profile (GATT) that defines methods to access data defined by the ATT layer. Generic Access Profile (GAP) that provides an application oriented interface which defines if the device acts as a BLE link master or slave and configures the underlying layers accordingly. See Appendix E: BLE Protocol for a detailed description of the BLE protocol. Figure 5. BLE Protocol Stack
Applications
... Custom Profile To develop an application using BLE, you do not need a working knowledge of this complex protocol stack. Cypress provides an easy -to-configure, GUI -based BLE Component that abstracts the protocol complexity. T o get started with BLE , it is sufficient to understand: BLE link establishment procedure Application data representation and abstraction Application requirements mapping to GAP and GATT layer configurations using Cypress’s BLE Component GUI.
Figure 16. BLE Development Setup
status LEDs indicate the state of the BLE interface. Figure 17. My First PSoC 4 BLE Design
- Configure the design in the PSoC Creator schematic page.
- Write the firmware to initialize and handle BLE events.
- Program the PSoC 4 BLE device on the BLE Pioneer Kit.
- Test your design using the CySmart Host Emulation Tool or mobile app.
- Select Generate Application from the Build menu. Notice in the Workspace Explorer window that PSoC Creator
automatically generates source code files for the BLE and Digital Output Pin Components, as Figure 37 shows. Figure 37. Generated Source Files
The following sections discuss these blocks with respect to the design that you configured in Part 1: Configure the Design. Component, which internally initializes the complete BLE subsystem. control to the main loop. Figure 38 and Code 1 show the flow chart and the firmware source code for system initialization. Figure 38. System Initialization Flow Chart
Table 1. The flow chart and the firmware for handling BLE stack events are shown in Figure 39 and Code 2. Table 1. BLE Stack Events advertisement state on the LED. advertisement state on the LED. Update the BLE link state on the LED. advertisement has timed out.
Figure 39. BLE Stack Event Handler Flow Chart
in Figure 40 and Code 3 respectively. Figure 40. BLE IAS Event Handler Flow Chart
Figure 41. Firmware Main Loop Flow Chart
Getting Started with PSoC® 4 BLE www.cypress.com Document No. 001-91267 Rev. *D 31 Code 4. Main Loop Firmware for(;;) static uint8 toggleTimeout = 0; CYBLE_BLESS_STATE_T blessState; uint8 intrStatus; /* Single API call to service all the BLE stack events. Must be * called at least once in a BLE connection interval */ CyBle_ProcessEvents(); /* Update Alert Level value on the blue LED */ switch(alertLevel) case NO_ALERT: Alert_LED_Write(LED_OFF); break; case MILD_ALERT: toggleTimeout++; if(toggleTimeout == LED_TOGGLE_TIMEOUT) /* Toggle alert LED after timeout */ Alert_LED_Write(Alert_LED_Read() ^ 0x01); toggleTimeout = 0; break; case HIGH_ALERT: Alert_LED_Write(LED_ON); break; /* Configure BLESS in Deep-Sleep mode */ CyBle_EnterLPM(CYBLE_BLESS_DEEPSLEEP); /* Prevent interrupts while entering system low power modes */ intrStatus = CyEnterCriticalSection(); /* Get the current state of BLESS block */ blessState = CyBle_GetBleSsState(); /* If BLESS is in Deep-Sleep mode or the XTAL oscillator is turning on, * then PSoC 4 BLE can enter Deep-Sleep mode (1.3uA current consumption) */ if(blessState == CYBLE_BLESS_STATE_ECO_ON || blessState == CYBLE_BLESS_STATE_DEEPSLEEP) CySysPmDeepSleep(); else if(blessState != CYBLE_BLESS_STATE_EVENT_CLOSE) /* If BLESS is active, then configure PSoC 4 BLE system in * Sleep mode (~1.6mA current consumption) */ CySysPmSleep();
MiniProg3. In PSoC Creator, choose Debug > Select Debug Target, as Figure 42 shows. Figure 42. Selecting Debug Target
design using the BLE Pioneer Kit is shown in Figure 15.
- Turn on Bluetooth on your iOS or Android device.
- Press the reset switch on the BLE Pioneer Kit to start BLE advertisements from your design.
- Pull down the CySmart app home screen to start scanning for BLE Peripherals, your device will now appear in the
CySmart app home screen. Select your device to establish a BLE connection.
- Select the “Find Me” Profile from the carousel view.
- Select one of the Alert Level values on the Find Me Profile screen and observe the state of the LED on your device
A step-by-step configuration screenshot of the CySmart mobile app is shown in Figure 46 and Figure 47. Figure 46. Testing with CySmart iOS App
Getting Started with PSoC® 4 BLE www.cypress.com Document No. 001-91267 Rev. *D 38 Related Application Notes AN94020 – Getting Started with PRoC BLE AN91445 – Antenna Design Guide AN91184 – PSoC 4 BLE - Designing BLE Applications AN91162 – Creating a BLE Custom Profile AN92584 – Designing for Low Power and Estimating Battery Life for BLE Applications About the Author Name: Krishnaprasad M V (KRIS). Title: Applications Engineer Senior Staff Background: Krishnaprasad has a BSEE from National Institute of Engineering, Mysore, India.
Getting Started with PSoC® 4 BLE www.cypress.com Document No. 001-91267 Rev. *D 39 Appendix A: BLE Device Family Comparison Table 2 summarizes the features and capabilities of the BLE device family from Cypress. Table 2. BLE Device Families
Features
CY8C41x7-BL CY8C42x7-BL CYBL10X6X CY8C41x8-BL CY8C42x8-BL BLE Subsystem BLE radio and link- layer hardware blocks with Bluetooth 4.1- compatible protocol stack BLE radio and link- layer hardware blocks with Bluetooth 4.1- compatible protocol stack BLE radio and link- layer hardware blocks with Bluetooth 4.1- compatible protocol stack BLE radio and link- layer hardware blocks with Bluetooth 4.1- compatible protocol stack BLE radio and link- layer hardware blocks with Bluetooth 4.1- compatible protocol stack CPU 24-MHz ARM Cortex-M0 CPU with single-cycle multiply 48-MHz ARM Cortex- M0 CPU with single- cycle multiply 48-MHz ARM Cortex- M0 CPU with single- cycle multiply 24-MHz ARM Cortex-M0 CPU with single-cycle multiply 48-MHz ARM Cortex- M0 CPU with single- cycle multiply Flash Memory 128 KB 128 KB 128 KB 256 KB 256 KB SRAM 16 KB 16 KB 16 KB 32 KB 32 KB GPIOs Up to 36 Up to 36 Up to 36 Up to 36 Up to 36 CapSense Up to 35 sensors Up to 35 sensors Up to 35 sensors Up to 35 sensors Up to 35 sensors CapSense Gestures On selected devices On selected devices On selected devices On selected devices On selected devices ADC 12-bit, 806-ksps SAR ADC with sequencer 12-bit, 1-Msps SAR ADC with sequencer 12-bit, 1-Msps SAR ADC with sequencer 12-bit, 806-ksps SAR ADC with sequencer 12-bit, 1-Msps SAR ADC with sequencer Opamps 2 programmable opamps that are active in Deep-Sleep mode 4 programmable opamps that are active in Deep-Sleep mode None 2 programmable opamps that are active in Deep-Sleep mode 4 programmable opamps that are active in Deep-Sleep mode Comparators 2 low-power comparators with the wakeup feature 2 low-power comparators with the wakeup feature None 2 low-power comparators with the wakeup feature 2 low-power comparators with the wakeup feature Current DACs One 7-bit, and one 8-bit One 7-bit, and one 8- bit None One 7-bit, and one 8-bit One 7-bit, and one 8- bit Power Supply Range Low-Power Modes Deep-Sleep mode at 1.3 µA Hibernate mode at 150 nA Stop mode at 60 nA Deep-Sleep mode at 1.3 µA Hibernate mode at 150 nA Stop mode at 60 nA Deep-Sleep mode at 1.3 µA Hibernate mode at 150 nA Stop mode at 60 nA Deep-Sleep mode at 1.3 µA Hibernate mode at 150 nA Stop mode at 60 nA Deep-Sleep mode at 1.3 µA Hibernate mode at 150 nA Stop mode at 60 nA Segment LCD Drive 4-COM, 32-segment LCD drive on select devices 4-COM, 32-segment LCD drive on select devices 4-COM, 32-segment LCD drive on select devices 4-COM, 32-segment LCD drive on select devices 4-COM, 32-segment LCD drive on select devices Serial Communication 2 independent serial communication blocks (SCBs) with programmable I2C, SPI, or UART 2 independent SCBs with programmable I2C, SPI, or UART 1 or 2 independent SCBs with programmable I2C, SPI, or UART 2 independent serial communication blocks (SCBs) with programmable I2C, SPI, or UART 2 independent SCBs with programmable I2C, SPI, or UART
Getting Started with PSoC® 4 BLE www.cypress.com Document No. 001-91267 Rev. *D 40 CY8C41x7-BL CY8C42x7-BL CYBL10X6X CY8C41x8-BL CY8C42x8-BL Timer Counter Pulse-Width Modulator (TCPWM) 4 4 4 4 4 Universal Digital Blocks (UDBs) None 4, each with 8 macrocells and one data path. Can be used to synthesize additional digital peripherals (Timer, Counter, PWM) or communication interfaces (UART, SPI) None None 4, each with 8 macrocells and one data path. Can be used to synthesize additional digital peripherals (Timer, Counter, PWM) or communication interfaces (UART, SPI) Additional Digital Peripherals (I2S, PWM) None Yes (UDB-based digital peripherals on select devices) Yes (fixed-function blocks on select devices) None Yes (UDB-based digital peripherals on select devices) Clocks 3-MHz to 24-MHz IMO 32-kHz ILO 24-MHz ECO 32-kHz WCO 3-MHz to 48-MHz IMO 32-kHz ILO 24-MHz ECO 32-kHz WCO 3-MHz to 48-MHz IMO 32-kHz ILO 24-MHz ECO 32-kHz WCO 3-MHz to 24-MHz IMO 32-kHz ILO 24-MHz ECO 32-kHz WCO 3-MHz to 48-MHz IMO 32-kHz ILO 24-MHz ECO 32-kHz WCO Power Supply Monitoring Power-on reset (POR) Brown-out detection (BOD) Low-voltage detection (LVD) POR BOD LVD POR BOD LVD Power-on reset (POR) Brown-out detection (BOD) Low-voltage detection (LVD) POR BOD LVD Package 56-QFN (7.0 × 7.0 × 0.6 mm) and 68-WLCSP (3.52 × 3.91 × 0.55 mm) 0.6 mm) and 68-WLCSP (3.52 × 3.91 × 0.55 mm) 0.6 mm) and 68-WLCSP (3.52 × 3.91 × 0.55 mm) 56-QFN* (7.0 × 7.0 × 0.6 mm) and 76-WLCSP (4.04 × 3.87 × 0.55 mm) 0.6 mm) and 76-WLCSP (4.04 × 3.87 × 0.55 mm) * = CY8C41x8-BL and CY8C42x8-BL (256K FLASH) QFN packages are pin-to-pin compatible with CY8C41x7-BL and CY8C42x7-BL (128K FLASH) QFN package, respectively.
Getting Started with PSoC® 4 BLE www.cypress.com Document No. 001-91267 Rev. *D 41 Appendix B: Cypress Terms of Art This section lists the most commonly used terms that you might encounter while working with Cypress’s PSoC family of devices. Component Configuration Tool: Simple GUI in PSoC Creator that is embedded in each Component. It is used to customize the Component parameters and is accessed by right-clicking a Component. Components: Free embedded ICs represented by an icon in PSoC Creator software. These are used to integrate multiple ICs and system interfaces into one PSoC Component that is inherently connected to the MCU via the main system bus. For example, the BLE Component creates Bluetooth Smart products in minutes. Similarly, you can use the Programmable Analog Components for sensors. MiniProg3: A programming hardware for development that is used to program PSoC devices on your custom board or PSoC development kits that do not support a built-in programmer. PSoC: A programmable, embedded design platform that includes a CPU, such as the 32-bit ARM Cortex-M0, with both analog and digital programmable blocks . It a ccelerates embedded system design with reliable, easy -to-use solutions, such as touch sensing, and enables low-power designs. PSoC 4 BLE : A PSoC 4 IC with an integrated BLE radio that i ncludes a royalty -free BLE protocol stack compatible with the Bluetooth 4.1 specification. PSoC Creator: PSoC 3, PSoC 4, and PSoC 5LP Integrated Design Environment (IDE) software that installs on your PC and allows concurrent hardware and f irmware design of PSoC systems, or hardware design followed by export to other popular IDEs. PSoC Programmer : A flexible, integrated programming application for programming PSoC devices. PSoC Programmer is integrated with PSoC Creator to program PSoC 3, PSoC 4, PRoC, and PSoC 5LP designs.
Pioneer Baseboard. The kit can be powered either with a coin-cell battery or through the USB interface. capabilities such as the CapSense user interface. master and works with CySmart Host Emulation Tool to provide a BLE host emulation platform on non-BLE Windows PCs. example projects, and documentation files. Figure 54. BLE Pioneer Kit Attributes on your Peripheral. Scan BLE Peripherals to discover available devices to which you can connect. Discover available BLE Attributes including Services and Characteristics on the connected Peripheral device. Perform read and write operations on Characteristic values and descriptors. Receive Characteristic notifications and indications from the connected Peripheral device. Establish a bond with the connected Peripheral device using BLE Security Manager procedures.
The BLE subsystem contains the physical layer (PHY) and link-layer engine with an embedded AES-128 security engine. code correlation are implemented in hardware. sources for the PSoC 4 BLE system. See the Clocking System section for details. The BLESS supports five functional power modes: Deep-Sleep, Sleep, Idle, Transmit, and Receive. maintaining the BLE link-layer timing reference logic. The CPU controls the entry to and exit from this state. the core BLESS logic is turned off. The CPU controls the entry to and exit from this state. layer clock is enabled for the link-layer logic so that the CPU starts the protocol state machines. transmits the 2.4-GHz GFSK-modulated data to the antenna port. BLE enters Transmit mode from Idle mode. the 1-Mbps data received from the RF analog block and forwards it to the link-layer controller after demodulation. A summary of the BLESS power modes and operational sub-blocks is shown in Table 3. Table 3. BLESS Power Modes
Getting Started with PSoC® 4 BLE www.cypress.com Document No. 001-91267 Rev. *D 46 ARM Cortex-M0 and Memory PSoC 4 BLE has a 32 -bit ARM Cortex -M0 CPU, capable of operating at a maximum frequency of 48 MHz, providing a 43 - DMIPS performance. The CPU supports single -cycle 32 -bit multiplication. PSoC 4 BLE has 16 KB/32 KB of SRAM and 128 KB/256 of flash memory that can service most of the BLE application use; the flash includes a re ad accelerator. The device also provides 512 bytes of supervisory flash area for you to store user -specific data such as BLE device address and encryption keys. Programmable Digital Peripherals PSoC 4 BLE provides a rich set of digital peri pherals includin g programmable serial communication blocks (SCBs), timer counter pulse width modulators (TCPWMs), and programmable logic arrays called universal digital blocks (UDBs). Programmable SCBs PSoC 4 BLE has independent run-time programmable SCBs with I2C, SPI, or UART. The SCB supports the following features: Standard SPI master and slave functionality with Motorola®, Texas Instruments®, and National Semiconductor® protocols Standard UART functionality with smart-card reader, Local Interconnect Network (LIN), and Infrared Data Association (IrDA) protocols Standard I2C master and slave functionality SPI and EZI2C mode, which allows operation without CPU intervention Low-power (Deep-Sleep) mode of operation for SPI and I2C protocols (using an external clock) For more information, refer to the PSoC 4 SCB Component datasheet. Programmable TCPWMs PSoC 4 BLE has four programmable 16 -bit TCPWM blocks. Each TCPWM can implement a 16 -bit timer, counter, PWM, or quadrature decoder. TCPWMs provide complementary outputs and selectable start, reload, stop, count, and capture event signals. The PWM mode supports center-aligned, edge, and pseudo random operations. For more information, refer to the PSoC 4 TCPWM Component datasheet. Universal Digital Blocks UDBs are programmable logic blocks that provide functionalities similar to CPLD and FPGA blocks, as Figure 59 shows. UDBs allow you to create a variety of digital functions such as timer, counter, PWM, pseudo random sequence (PRS), CRC, shift register, SPI, UART, I2S, and custom combinational and sequential logic circuits. Each UDB has two programmable logic devices (PLDs), each with 12 inputs and 8 product terms. PLDs can form registered or combinational sum-of-products logic. Addit ionally, an 8 -bit single-cycle arithmetic logic unit (ALU), known as a “datapath,” is present in each UDB. The datapath helps with the efficient implementation of functions such as timer, counter, PWM, and CRC. UDBs also provide a switched digital signal interconnect (DSI) fabric that allows signals from peripherals and ports to be routed to and through the UDBs for communication and control.
Getting Started with PSoC® 4 BLE www.cypress.com Document No. 001-91267 Rev. *D 47 Figure 59. Universal Digital Block Diagram can implement custom logic on UDBs using Verilog. For more information, refer to the following application notes. The use of programmable digital peripherals in BLE applications is shown in Table 4. Table 4. Applications of Programmable Digital Peripherals CTBm block can be configured to function even in device Deep-Sleep mode.
Getting Started with PSoC® 4 BLE www.cypress.com Document No. 001-91267 Rev. *D 48 SAR ADC with Hardware Sequencer PSoC 4 BLE has a 12 -bit, 1 -Msps Successive Approximation Register ( SAR) ADC with input channels that support programmable resolution and single -ended or differential input options. The number of GPIOs limits t he number of ADC input channels that can be implemented. The SAR ADC has a hardware sequencer that can perform an automatic scan on as many as eight channels without CPU intervention. It also supports preprocessing operations such as accumulation and averaging of the output data on these eight channels. You can trigger a scan with a variety of methods, such as firmware, timer, pin, or UDB, giving you additional design flexibility. For more information, refer to the PSoC 4 SAR ADC Component datasheet. Low -Power Compa rators PSoC 4 BLE devices have low -power comparators capable of operating in all system power modes except the Stop mode. In a power-sensitive design, when the device goes into low-power modes , you can use the low-power comparator to monitor analog inputs and generate an interrupt that can wake up the system. For more information, refer to the PSoC 4 Low-Power Comparator Component datasheet. Capacitive Touch Sensing (CapSense) Capacitive touch sensors use human -body capacitance to detect the presence of a finger on or near a sensor. Capacitive sensors are aesthetically superior, easy to use, and have long lifetimes. The CapSense feature in PSoC 4 BLE offers unprecedented signal-to-noise ratio; best-in-class liquid tolerance; and a wide variety of sensor types such as buttons, sliders, track pads, and proximity sensors. A Cypress-supplied software Component makes capacitive sensing design very easy; the Component suppor ts an automatic hardware-tuning feature called SmartSense™ and provides a gesture-recognition library for trackpads and proximity sensors. Two current DACs (IDACs), one 7 -bit and one 8-bit, in the CapSense block are available for general -purpose use if capacitive sensing is not used. The comparator in the CapSense block is also available for general-purpose use. For more information, see the PSoC 4 CapSense Design Guide. Segment LCD Direct Drive r Most low -power, portable, handheld devices such as glucose meters, multimeters, and blood pressure monitors use a segment LCD to display information. Segment LCDs typically require an external driver to interface with a microcontroller. PSoC 4 BLE includes an integrated low-power LCD driver that can directly drive segment LCD glass. PSoC 4 BLE can drive LCDs with as many as 4 common and 32 segment electrodes. The segment LCD driver can retain a static display in Deep-Sleep mode with a system current consumption as low as 7 µA. For more information, see AN87391 PSoC 4 Segment LCD Direct Drive. The use of programmable analog peripherals in different BLE applications is listed in Table 5. Table 5. Applications of Programmable Analog Peripherals
This section explains the system-wide resources available for all peripherals in PSoC 4 BLE. the power modes described in the Bluetooth Low Energy Subsystem (BLESS) section. Active mode: This is the primary mode of operation. In this mode, all peripherals are available. interrupt wakes up the CPU and returns the system to Active mode. asynchronous, or low-power analog peripherals can cause a wakeup. The current consumption in this mode is 1.3 µA. ability to wake up from an interrupt generated by a low-power comparator or a GPIO. consumption in this mode is only 60 nA. best-in-class system power with longer battery life. dependencies are handled by simple APIs; see the Main Loop and Low-Power section for an example. BLE connection intervals, and in Hibernate or Stop mode on BLE advertisement timeout. Table 6. PSoC 4 BLE Power Modes
different device power modes. PSoC 4 BLE has three types of voltage-monitoring capabilities: POR, BOD, and LVD. generate clocks in the range of 3 MHz to 48 MHz in 1-MHz increments with an accuracy of ±2 percent. low-speed peripherals operating in Deep-Sleep mode except the BLESS (see WCO). generate a highly accurate 24 -MHz clock. It is primarily used to clock the BLE subsystem that generates the RF clocks. available in all modes except the Hibernate and Stop modes. Figure 60 shows the clocking architecture of a PSoC 4 BLE device. Figure 60. PSoC 4 BLE Clocking System
32.768 KHz external clock
Getting Started with PSoC® 4 BLE www.cypress.com Document No. 001-91267 Rev. *D 51 Device Securit y PSoC 4 BLE provides a number of options to protect the flash memory from unauthorized access or copying. Each row of flash has a single protection bit; these bits are stored in a supervisory flash row. Programmable GPIOs The I/O system provides an interface between the CPU and the peripherals and the outside world. PSoC 4 BLE has up to 36 programmable GPIO pins. You can configure the GPIOs for CapSense, LCD, analog, or digital signals. PSoC 4 BLE GPIOs support multiple drive modes, drive strengths, and slew rates. PSoC 4 BLE offers an intelligent routing system that gives multiple choices for connecting an internal signal to a GPIO. This flexible routing simplifies circuit design and board layout.
Getting Started with PSoC® 4 BLE www.cypress.com Document No. 001-91267 Rev. *D 52 Appendix E: BLE Protocol Overview BLE, also known as Bluet ooth Smart, was introduced by the Bluetooth SIG as a low -power wireless standard operating in the 2.4-GHz ISM band. Figure 61 shows the BLE stack. Figure 61. BLE Architecture The BLE stack can be subdivided into three groups: Controller: A physical device that encodes the packet and transmits it as radio signals. On reception, the controller decodes the radio signals and reconstructs the packet. Host: A software stack consisting of various protocols and P rofiles (Security Manager, Attribute Protocol, and so on) that manages how two or more devices communicate with one another. Application: A use case that uses the software stack and the controller to implement a particular functionality. The following sections provide an overview of the multiple layers of the BLE stack, using the standard Heart Rate and Battery Service as examples. For a detailed BLE ar chitecture description, see the Bluetooth 4. 1 specification or the training videos on the Bluetooth Developer website. Physical Layer (PHY) The physical layer transmits or receives digital data at 1 Mbps using Gaussian frequency-shift keying (GFSK) modulation in the 2.4 -GHz ISM band. The BLE physical layer divides the ISM band into 40 RF channels with a channel spacing of 2 MHz, 37 of which are data channels and 3 are advertisement channels. Link Layer (LL) The link layer implements key procedures to establish a reliable physical link (using an acknowledgement and flow - control-based architecture) and features that help mak e the BLE protocol rob ust and low power. Some link layer functions include: Advertising, scanning, creating, and maintaining connections to establish a physical link
Figure 63. BLE L2CAP Layer The SM layer defines the methods used for pairing, encryption, and key distribution. interface without being snooped on by a silent listener on the RF channel. saved. After devices are bonded, they do not have to go through the pairing process again when reconnected. BLE uses 128-bit AES for data encryption. keyboard GATT server contains user key press information. receives key-press information from a BLE keyboard. Attribute Handle: The 16-bit address used to address and access an Attribute. 0x2A00. Visit the Bluetooth web page for a list of 16-bit UUIDs assigned by the SIG. Attribute Value: This is the actual data stored in the Attribute.
Getting Started with PSoC® 4 BLE www.cypress.com Document No. 001-91267 Rev. *D 61 Document History Document Title: AN91267 – Getting Started with PSoC® 4 BLE Document Number: 001-91267 Revision ECN Orig. of Change Submission Date Description of Change ** 4564230 KRIS 11/07/2014 New Application Note *A 4567888 KRIS 11/12/2014 Fixed hyperlinks and document formatting *B 4683692 KRIS 03/27/2015 Major reformatting including moving the BLE Protocol and PSoC 4 BLE device details to Appendix. Example design simplified and added Deep-Sleep low-power mode. *C 4758078 KRIS 05/11/2015 Updated Software Version as “PSoC Creator™ 3.1 SP3” in page 1. Replaced “PSoC Creator 3.1 SP1” with “PSoC Creator 3.1 SP3” in all instances across the document. Updated My First PSoC 4 BLE Design: Updated Part 1: Configure the Design: Updated description. Updated Figure 31. *D 4767158 ROIT 05/15/2015 Added support for PSoC 4 BLE 256K Updated Software Versions as “PSoC Creator 3.2” Updated BLE component GUI screenshots Updated CySmart iOS/Android App screenshots Updated Table 2 in Appendix A with WLCSP dimensions
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