ALN1880AT_17 ASB | Alldatasheet
Document overview
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- PDF pages: 3
Technical content
Features
- S21 = 15.1 dB @ 1850 MHz = 14.7 dB @ 1910 MHz
- NF of 0.65 dB over Frequency
- Unconditionally Stable
- Single 5V Supply
- High OIP3 @ Low Current Note: 1. The number and size of ground via holes in a circuit board is critical for the rmal RF grounding considerations. 2. We recommend that the ground via holes be placed on the bottom of all ground pins for better RF and thermal performance, as shown in the drawing at the left side.
Description
(Recommended Footprint) ALN1880AT ASB Inc. (Top View) (Bottom View) Ø 0.4 plated thru holes to ground plane plerow (Side View) Website: www.asb.co.kr E-mail: sales@asb.co.kr Tel: (82) 42-528-7223 Fax: (82) 42-528-7222 More Information 1-stage Single Type Typ. @ T = 25C, Vs = 5 V, Freq. = 1880 MHz, Zo.sys = 50 ohm Solder Stencil Area Specifications (in Production)
2/3 www.asb.co.kr June 2017 plerowTM ALN1880AT Internally Matched LNA Module S-parameters Noise Figure OIP3 P1dB 1850~1910 MHz +5 V Stability Factor (K) Typical Performance (Measured)
3/3 www.asb.co.kr June 2017 plerowTM ALN1880AT Internally Matched LNA Module 1) The tantal capacitor is optional and for bypassing the AC noise introduced from the DC supply. The capacitance value may be determined by customer’s DC supply status. 2) So-called DC blocking capacitors are always necessarily placed at the input and output port for allowing only the RF signal to pass and blocking the D C component in the signal. The DC blocking capacitors are included inside the LNA module. Therefore, C1 & C2 capacitors may not be necessary, but can be added just in case that the customer wants. The value of C1 & C2 is determined by considering the application frequency. Copyright 2007-2017 ASB Inc. All rights reserved. Datasheet subject to change without notice. ASB assumes no re- sponsibility for any errors which may appear in this datasheet. No part of the datasheet may be copied or reproduced in any form or by any means without the prior written consent of ASB. Application Circuit Recommended Soldering Reflow Process Evaluation Board Layout + - ALN OUT IN C1 C2 Tantal Capacitor V DC 20~40 sec 260C 200C 150C 60~180 sec Ramp-up (3˚C/sec) Ramp-down (6C/sec) Size 25 x 25mm IN OUT +Vcc (for ALN-AT, BT, T Series – 10x10mm) Preliminary