ALN1765AT_13 ASB | Alldatasheet

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Technical content

Features

Specifications (in Production) Note: 1. The number and size of ground via holes in a circuit board is critical for thermal RF grounding considerations. 2. We recommend that the ground via holes be placed on the bottom of all ground pins for better RF and thermal performance, as shown in the drawing at the left side.

Description

ASB Inc. (Top View) (Bottom View) Solder Stencil Area Ø 0.4 plated thru holes to ground plane plerow (Side View) Typ. @ T = 25C, Vs = 5 V, Freq. =1765 MHz, Zo.sys = 50 ohm C o u pl er Website: www.asb.co.kr E-mail: sales@asb.co.kr Tel: (82) 42-528-7223 Fax: (82) 42-528-7222 More Information C o u pl er C o u pl er C o u pl er 1-stage Single Type

2/4 www.asb.co.kr March 2009 plerowTM ALN1765AT Internally Matched LNA Module S-parameters Noise Figure OIP3 P1dB 1740~1790 MHz +5 V Typical Performance (Measured) S-parameters & K Factor

3/4 www.asb.co.kr March 2009 plerowTM ALN1765AT Internally Matched LNA Module 1. S-parameter 2. OIP3, P1dB & NF Note: tested at room temperature. 1. S-parameter 2. OIP3, P1dB & NF Note: tested at Vs= 5V.

1739 MHz 1755 MHz 1770 MHz

S21 (dB) S11 (dB) S22 (dB) S21 (dB) G/F (dB) S11 (dB) S22 (dB) S21 (dB) S11 (dB) S22 (dB) OIP3 (dBm) P1dB (dBm) NF (dB) OIP3 (dBm) P1dB (dBm) NF (dB) OIP3 (dBm) P1dB (dBm) NF (dB) S21 (dB) S11 (dB) S22 (dB) S21 (dB) G/F (dB) S11 (dB) S22 (dB) S21 (dB) S11 (dB) S22 (dB) OIP3 (dBm) P1dB (dBm) NF (dB) OIP3 (dBm) P1dB (dBm) NF (dB) OIP3 (dBm) P1dB (dBm) NF (dB) RF Performance with Operating Temperature RF Performance with Voltage Change

4/4 www.asb.co.kr March 2009 plerowTM ALN1765AT Internally Matched LNA Module 1) The tantal or MLC (Multi Layer Ceramic) capacitor is optional and for bypassing the AC noise introduced from the DC supply. The capacitance value may be determined by customer’s DC supply status. The ca- pacitor should be placed as close as possible to Vs pin and be connected directly to the ground plane for the best electrical performance. 2) DC blocking capacitors are always necessarily placed at the inp ut and output port for allowing only the RF signal to pass and blocking the DC component in the signal. The DC blocking capacitors are inclu d- ed inside the ALN module. Therefore, C1 & C2 capacitors may not be necessary, but can be added just in case that the customer wants. The value of C1 & C2 is determined by considering the application fr e- quency. C3 and C4 in the blue dot line circle shall be used for matching. Application Circuit Recommended Soldering Reflow Process 20~40 sec 260C 200C 150C 60~180 sec Ramp-up (3˚C/sec) Ramp-down (6C/sec) IN OUT Vs Size 25x25mm (for ALN-AT, BT, T Series – 10x10mm) Evaluation Board Layout + - ALN OUT IN C1 C2 VS Tantal or MLC (Multi Layer Ceramic) Capacitor (Mandatory) C3 = 0.5pF C4 = 100pF (Mandatory)