EZ80F917050SBCG ZILOG | Alldatasheet
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Zdots® SBC for eZ80AcclaimPlus!™ Connectivity ASSP Copyright ©2007 by Zilog®, Inc. All rights reserved. www.zilog.com
DO NOT USE IN LIFE SUPPORT LIFE SUPPORT POLICY ZILOG'S PRODUCTS ARE NOT AUTHORIZED FO R USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT TH E EXPRESS PRIOR WRITTEN APPROV AL OF THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION. As used herein Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be re asonably expected to result in a significant injury to the user. A critical component is any component in a life suppor t device or system whose failure to perform can be reasonably expected to cause the fa ilure of the life support device or system or to affect its safety or effectiveness. Document Disclaimer ©2007 by Zilog, Inc. All rights reserved. Information in this pu blication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZILOG , INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZILOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The information contained within this document has been verified according to the general principles of electrical and mechanical engineering. Z8, Z8 Encore!, Z8 Encore! XP, Z8 Encore! MC, Crimzon, eZ80, ZNEO, Zdots, and eZ80AcclaimPlus! are trademarks or registered trademarks of Zilog, Inc. All other product or service names are the property of their respective owners. Warning:
Zdots® SBC for eZ80AcclaimPlus!™ Connectivity ASSP Product Specification iii
Revision History
Each instance in the Revision History reflects a change to this document from its previous revision. For more details, refer to the corresponding pages or appropriate links given in the table below. Date Revision Level Description Page No December 2007
02 Updated Table 6, Figure 8, Figure 9,
and Figure 10. 20, 23, 24, and July 2007 01 Original issue. All
PS026102-1207 Table of Contents Zdots® SBC for eZ80AcclaimPlus!™ Connectivity ASSP Product Specification iv Table of Contents
PS026102-1207 Zdots® SBC for eZ80AcclaimPlus!™ Connectivity ASSP Zdots® SBC for eZ80AcclaimPlus!™ Connectivity ASSP Product Specification Zdots® SBC for eZ80AcclaimPlus!™ Connectivity ASSP Zilog’s Zdots® Single Board Computer (SBC) for eZ80AcclaimPlus!™ Connectivity Application Specific Standard Product (ASSP) is a compact, high-performance Ethernet SBC specially designed for the rapid development and deployment of embedded systems requiring control and internet/intranet connectivity. This expandable module is powered by Zilog’s latest power-efficient, high-speed, optimized pipeline architecture eZ80F91 connectivity ASSP, a member of eZ80AcclaimPlus! Zilog® family. eZ80F91 is a high-speed single-cycle instruction-fetch microcontroller, which operates with a clock speed of 50 MHz. It can also operate in Z80®-compatible addressing mode (64 KB) or full 24-bit addressing mode (16 MB). The peripheral-rich Zdots SBC makes it suitable for a variety of applications including industrial control, IrDA connectivity, communication, security, automation, point-of-sale terminals, and embedded networking applications. Zdots® SBC for eZ80AcclaimPlus! TM Connectivity ASSP Features Features of Zdots SBC for eZ80AcclaimPlus! Connectivity ASSP include:
- Factory-default operating clock frequency at 50 MHz
- 10/100 Base-T Ethernet PHY with RJ45 connector
- 512 KB fast SRAM
- 256 KB on-chip Flash memory
- 1 MB OFF-chip NOR Flash memory
- Battery-backed Real-Time Clock
- Input/Output connector which provides 32 general-purpose 5 V-tolerant I/O pinouts
- Zilog’s industry-leading IrDA transceiver—Zilog ZHX1810
- Onboard connector provides I/O bus for external peripheral connections (IRQ, CS, 24 ad- dress, and 8 data)
- Low-cost connection to carrier board via two 2x30 pin headers
- Small footprint 63.5 mm x 78.7 mm
- 3.3 V power supply
- Standard operating temperature range: 0 ºC to +70 ºC
PS026102-1207 Zdots® SBC for eZ80AcclaimPlus!™ Connectivity ASSP Zdots® SBC for eZ80AcclaimPlus!™ Connectivity ASSP Product Specification eZ80AcclaimPlus!TM Connectivity ASSP Features Features of eZ80AcclaimPlus! Connectivity ASSP include:
- Single-cycle instruction fetch, high-performance, pipelined eZ80® CPU core
- 256 KB of Flash memory and 8 KB of SRAM
- 10/100 Mbps Ethernet MAC with 8 KB frame buffer
- Low power features including SLEEP mode, HALT mode, and selective peripheral power-down control
- Two UARTs with independent baud rate generators and support for 9-bit operation
- SPI with independent clock generator
- I2C with independent clock generator
- Infrared data association (IrDA)-compliant infrared encoder/decoder
- New DMA-like eZ80 instructions for efficient block data transfer
- External interface with four chip selects, individual wait state generators, and an external WAIT input pin—supports Intel- and Motorola-style buses
- Flexible-priority vectored interrupts (both internal and external) and interrupt controller
- Real-time clock with on-chip 32 kHz oscillator, selectable 50/60 Hz input, and separate VDD pin for battery backup
- Four 16-bit Counter/Timers with prescalers and direct input/output drive
- Watchdog Timer (WDT)
- 32 bits of general-purpose input/output (GPIO)
- JTAG and ZDI debug interfaces
- 144-pin LQFP package
- Supply voltage of 3.0 V to 3.6 V with 5 V tolerant inputs
- Standard operating temperature range: 0 ºC to +70 ºC
Figure 1 displays the block diagram of Zdots SBC for eZ80AcclaimPlus!™ ASSP. Figure 1. Zdots SBC for eZ80AcclaimPlus! ASSP Functional Block Diagram
8 KB SRAM,
50 MHz
Table 1. Zdots Peripheral Bus Connector Pin Identification*
1 Reserved
2 Reserved
3 Reserved
4 Reserved
Input Reset for on-chip instrumentation (OCI).
6 Reserved
7 F91_WE
Flash memory is Write-protected.
8 Reserved
10 V CC 3.3 V supply input pin.
11 A6 Bidirectional
12 A0 Bidirectional
13 A10 Bidirectional
14 A3 Bidirectional
15 GND V
16 V CC 3.3 V supply input pin.
17 A8 Bidirectional
18 A7 Bidirectional
19 A13 Bidirectional
20 A9 Bidirectional
21 A15 Bidirectional
22 A14 Bidirectional
23 A18 Bidirectional
24 A16 Bidirectional
25 A19 Bidirectional
26 GND V
27 A2 Bidirectional
28 A1 Bidirectional
29 A11 Bidirectional
30 A12 Bidirectional
31 A4 Bidirectional
32 A20 Bidirectional
33 A5 Bidirectional
34 A17 Bidirectional
35 Reserved
36 DIS_Flash
PU 10 kΩ Input A Low disables onboard Flash memory. connected; CMOS input 3.3 V (5 V tolerant).
37 A21 Bidirectional
39 A22 Bidirectional
40 A23 Bidirectional
41 CS0
42 CS1 Output
43 CS2 Output
44 D0 PU 4 k Ω Bidirectional
45 D1 PU 4 k Ω Bidirectional
46 D2 PU 4 k Ω Bidirectional
47 D3 PU 4 k Ω Bidirectional
48 D4 PU 4 k Ω Bidirectional
49 D5 PU 4 k Ω Bidirectional
51 D7 PU 4 k Ω Bidirectional
52 D6 Bidirectional
53 MREQ
54 IORQ Bidirectional
**Table 1. Zdots Peripheral Bus Connector Pin Identification* (Continued)**
Figure 3 on page 8 displays the pin layout of the 60-pin I/O connector (JP2) of the Zdots. ment platform. Table 2 on page 8 describes the pins.
56 RD Bidirectional
57 WR Bidirectional
58 INSTRD Output
59 BUSACK Output
60 BUSREQ PU 2 kΩ Input
- External capacitive loads on RD , WR, IORQ, MREQ, D0–D7, and A0–A23 must be below 10 pF to satisfy
timing requirements for the CPU.
- All unused inputs must be pulled to either V DD or GND, depending on their inactive levels, to reduce power
consumption and to reduce noise sensitivity.
- All inputs are CMOS level 3.3 V (5 V tolerant), except where otherwise noted.
Figure 3. Zdots Input/Output Connector Pin Configuration—JP2 Table 2. Zdots Input/Output Connector Pin Identification*
1 PA7 Bidirectional
2 PA6 Bidirectional
3 PA5 Bidirectional
4 PA4 Bidirectional
5 PA3 Bidirectional
6 PA2 Bidirectional
7 PA1 Bidirectional
8 PA0 Bidirectional
9V CC 3.3 V supply input pin.
11 PB7 Bidirectional
12 PB6 Bidirectional
13 PB5 Bidirectional
14 PB4 Bidirectional
15 PB3 Bidirectional
16 PB2 Bidirectional
17 PB1 Bidirectional
18 PB0 Bidirectional
19 GND V
20 PC7 Bidirectional
21 PC6 Bidirectional
22 PC5 Bidirectional
23 PC4 Bidirectional
24 PC3 Bidirectional
25 PC2 Bidirectional
26 PC1 Bidirectional
27 PC0 Bidirectional
28 PD7 Bidirectional
29 PD6 Bidirectional
30 GND V
31 PD5 Bidirectional
32 PD4 PD 4 k
33 PD3 Bidirectional
34 PD2 Bidirectional
35 PD1 Bidirectional
36 PD0 Bidirectional
37 TDO Output JTAG Data Output pin. **Table 2. Zdots Input/Output Connector Pin Identification* (Continued)**
38 TDI/ZDA Input JTAG Data Input pin. 40 TRIGOUT Output Active High trigger event indicator.
41 TCK/ZCL PU 10 k
Low on reset enables OCI debug. 42 TMS PU 10 k Ω Input JTAG Test Mode Select Input. 44 EZ80CLK Output Synchron ous CPU clock output. 45 I 2CSCL PU 4 k Ω Bidirectional I 2C Bus Clock. 47 I 2CSDA PU 4 k Ω Bidirectional I 2C Data Clock. 48 GND Power V SS/Ground (0 V).
49 F lashWE PU 10 kΩ Input A Low enables a Write to external Flash memory
Flash memory boot block area is Write-protected.
51 CS3 Output Used on the eZ80190, eZ80L92, eZ80F92,
52 DIS_IRDA
use PC0/PC1 UART pins externally. 53 RESET PU 2 kΩ Bidirectional Reset Output from module or push-button reset.
54 WAIT PU 2 kΩ Input Driving the WAIT pin Low forces the CPU to
57 HALT_SLP Output, Active
execution of either a HALT or SLP instruction.
58 NMI
includes a Schmitt-trigger to allow RC rise times. 59 V CC 3.3 V supply input pin. 60 Reserved NC Reserved—No Connection.
- External capacitive loads on RD , WR, IORQ, MREQ, D0–D7, and A0–A23 must be below 10 pF to satisfy
timing requirements for the CPU.
- All unused inputs must be pulled to either V DD or GND, depending on their inactive levels, to reduce power
consumption and to reduce noise sensitivity.
- All inputs are CMOS level 3.3 V (5 V tolerant), except where otherwise noted.
CR1 and resistor R28 when external power is applied to the board. chokes) and two LED indicators. Table 3. Zdots MII Resistor Configuration
1 Yes1 No All Disabled
data, the left LED is ON. When the PHY is transmitting data, the right LED is ON. to eZ80F91 Product Specification (PS0192).
- MII Register 0 (Speed and Duplex Bits) must be set by a MAC to achieve a link.
- When autonegotiation is enabled, these bi ts are written but will be ignored by PHY.
- The advertised abilities of MII Register 4 cannot exceed the abilities of MII Register 1. Autonegotiation must
Table 3. Zdots MII Resistor Configuration (Continued)
eZ80F91 device is already well into the next bus cycle. Data being written is not corrupted because the Write pulse is not yet asserted. Figure 4. Bus Contention without the Zdots Fast Buffer Feature
programming of on-chip Flash. states of the signals and the status of the jumper for different modes. only three wait states at 50 MHz. wait-state access. The eZ80F91’s on-chip SRAM is used with zero wait states. PD2 (Shutdown, R_SD). The IrDA transceiver is of the LED type 870 nm Class 1. cannot be used simultaneously. Table 4. Flash Memory Programming Signals and Jumpers
PS026102-1207 Onboard Component Description Zdots® SBC for eZ80AcclaimPlus!™ Connectivity ASSP Product Specification disabled by setting PD2 (IR_SD) High or by pulling the DIS_IRDA pin on the I/O connector Low. The shutdown is used for power savings. To enable the IrDA transceiver, DIS_IRDA is left floating and PD2 is set to Low. Reset Generator The onboard Reset Generator Chip performs reliable Power-On Reset. The chip generates a reset pulse with a duration of 200 ms if the power supply drops below 2.93 V . This reset pulse ensures that the board always starts in a defined condition. The RESET pin on the I/O connector reflects the status of the RESET line. It is a bidirectional pin for resetting external peripheral components or for resetting the Zdots with a low-impedance output (for example, a 100 Ω push button). Serial Interface Ports The CPU contains two UARTs with programmable baud rate generators. UART0 is con- nected to GPIO PD[0:7] on the I/O connector. UART1 is connected to GPIO PC[0:7] on the I/O connector. Do not connect an RS-232 interface without level shifters. There are no RS-232 level shifters on the Zdots. Physical Dimensions The footprint of the Zdots PCB is 63.5 mm x 78.7 cm. With an RJ-45 Ethernet connector, the overall height is 25 mm, see Figure 5 on page 17. Note:
Figure 5. Physical Dimensions of the Zdots SBC
Table 6 lists the installed components of the Zdots. Table 6. Bill of Materials for the Zdots 35-0062-01 IC, 74LCX32, LV, QUAD OR, 14-TSSOP 1 U4 Fairchild Semi.
15 C13, C14,
Table 5. Absolute Maximum Ratings (Continued)
Table 6. Bill of Materials for the Zdots (Continued)
1 Y1 CITIZEN
1 Y2 CITIZEN
1 Y3 Fox NC-38
1 P2 Halo Electronics
Figure 9. Zdots Schematic Diagram—CPU and PHY
25 MHz
Figure 10. Zdots Schematic Diagram—Module Memory assembly rev B of the module.
PS026102-1207 Customer Support Zdots® SBC for eZ80AcclaimPlus!™ Connectivity ASSP Product Specification Customer Support For answers to technical questions about the product, documentation, or any other issues with Zilog’s offerings, please visit Zilog’s Knowledge Base at http://www.zilog.com/kb. For any comments, detail technical questions, or reporting problems, please visit Zilog’s Technical Support at http://support.zilog.com.