GMS97C2051 HYNIX | Alldatasheet
Document overview
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Technical content
Features
Compatible with MCS-51TM Products
2 Kbytes of programmable EPROM
4.25V to 5.5V Operating Range (GMS97C2051) 2.70V to 3.6V Operating Range (GMS97L2051) Version for 12MHz / 24 MHz Operating frequency (GMS97C2051) Only 12MHz Operating frequency (GMS97L2051) Two-Level Program Memory Lock with encryption array 128 bytes SRAM
15 Programmable I/O Lines
Low Power Idle and Power Down Modes
Description
The GMS97C2051/L2051 is a high-performance CMOS 8-bit microcontroller with 2Kbytes of programmable EPROM. The device is compatible with the industry standard MCS-51TM instruction set and pinout. The HYUN- DAI MicroElectronics GMS97C2051/L2051 is a powerful microcontroller which provides a highly flexible and cost effective solution to many embedded control applications. The GMS97C2051/L2051 provides the following standard features: 2Kbytes of EPROM, 128 bytes of RAM, 15 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, a precision analog comparator, on-chip oscillator and clock circuitry. In addition, the GMS97C2051/L2051 supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power Down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset. Pin Configuration PDIP/SOP (T0) P3.4 VCC P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 (AIN1) P1.0 (AIN0) P3.7 RST (RXD) P3.0 (TXD) P3.1 XTAL2 XTAL1 (INT1) P3.3 (T1) P3.5 GND (INT0 )P3.2
GMS97C2051/L2051 8-Bit CMOS Microcontroller HYUNDAI MicroElectronics 2 Block Diagram VCC GND P1.0-P1.7 RAM ADDR RAM STACK POINTER PC INCREMENTER PROGRAM COUNTER ACC EPROM PROGRAM ADDRESS REGISTER BUFFER DPTR TMP1TMP2 PSW B REGISTER INTERRUPT, SERIAL PORT AND TIMER BLOCKS OSC PORT 3 LATCH PORT 1 LATCH TIMING AND CONTROL INSTRUCTION REGISTER PORT 1 DRIVERS PORT 3 DRIVERS RST P 3 . 0 - P 3 . 5 P 3 . 7 ANALOG COMPARATOR ALU
values of the new bits will always be 0. Table 1. GMS97C2051/L2051 SFR Map and Reset Values
Table 2. Bit Assignment of SFRs
Table 3. SFR lists and their addresses the register is incremented every machine cycle. Table 4. Timer / Counter 0 and 1 Operating Modes
Figure 3. Time/Counter 0 and 1 Input Clock Logic Table 5. USART Operating Modes : Serial data enters and exits through RXD. TXD outputs the shift clock.
Table 6. Formulas for calculating Baud rates be interrupted by any other interrupt source. Figure 4. Interrupt Request Sources
Table 7. Interrupt Sources and their corresponding Interrupt Vectors Table 8. Interrupt Priority-Within-Level limits may cause unknown program behavior. boundaries may cause erratic execution. family architecture have been preserved.
- MOVX-related instructions, Data Memory:
instructions should be included in the program.
or set to ‘1’ if external pullups are used. cycles before the internal reset algorithm takes control. this event, but access to the port pins is not inhibited. that writes to a port pin or to external memory. enough to allow the oscillator to restart and stabilize. ( similar to power-on reset ). Table 9. Power Saving Modes Overview
- CPU status registers maintain their data.
8-Bit CMOS Microcontorller GMS97C2051/L2051 HYUNDAI MicroElectonics11 Programming The EPROM The GMS97C2051/L2051 is programmed by using a modified Quick-Pulse ProgrammingTM algorithm. It differs from older methods in the value used for VPP (programming supply voltage) and in the width and number of the P3.2(PROG ) . The GMS97C2051/L2051 contains two signature bytes that can be read and used by an EPROM pro- gramming system to identify the device. The signature bytes identify the device as an manufactured by HME . Table 10 shows the logic levels for reading the signa- ture byte, and for programming the program memory, the encryption table, and the security bits. The circuit configuration and waveforms for quick-pulse pro- gramming are shown in Figures 5 and Figure 8. Figure 6 shows the circuit configuration for normal program memory verification. EPROM Programming and Verification Internal Address Counter : The GMS97C2051/L2051 contains an internal EPROM address counter which is always set to 07FFH on the rising edge of RST after setting P3.0 to ‘H’ and is ad- vanced by applying continuous level transition to pin P3.0. Programming Algorithm : To program the GMS97C2051/L2051, the following sequence is recommended. 1. Power-up Sequence Apply power between V CC and GND pins with crystal oscillation. Set P3.0 to ‘H’. Set RST to GND. With all other pins floating, wait for greater than 1 0 m s . 2. Set pin RST to ‘H’ and pin P3.2 to ‘H’. 3. Apply the appropriate combination of ‘H’ or ‘L’ logic levels to pins P3.3, P3.4, P3.5, P3.7 to select one of the programming operations shown in the EPROM Programming Modes. (Table 10). To program and verify the array 4. The P3.0 level is pulled ‘L’ and apply data for code byte at location 0000H to P1.0 to P1.7 5. Raise RST to 12.75V to enable pr ogramming. 6. The P3.2( PROG ) is pulsed low 10 times as shown i n Figure 8. Each programming pulse is low for 100us(±10us) and high for a minimum of 10us. 7. To verify the programmed data, lower RST from 12.75V to logic ‘H’ level and set pins P3.3 to P3.7 to the appropriate levels. Output data can be read at the port P1 pins. At this time P3.0 should not be changed. 8. To program a byte at the next address location, P3.0 level transition is needed to advance the internal address counter. Apply new data to the port P1 pins. 9. Repeat step 5 through 8, changing data and advancing the address counter for the entire 2K b y t e s a r r a y . Program Verify : If lock bits LB1 and LB2 have not been programmed, code data can be read back via port P1 pins. 1. Set the internal address counter to 07FFH by bringing RST from ‘L’ to ‘H’ and reset the internal address counter to 0000H by bringing P3.0 from ‘H’ to ‘L’. 2. Apply the appropriate control signals for Read Code data to pins P3.3, P3.4, P3.5, P3.7 and read the output data at the port P1 pins. 3. The P3.0 level transition is taken to advance the internal address counter. 4. Read the next code data byte at the port P1 pins. 5. Repeat step 3 and 4 until the entire array is read. Program Memory Lock Bits The two-level Program Lock system consists of 2 Lock bits and a 32-byte Encryption Array which are used to protect the program memory against software piracy. Encryption Array : Within the EPROM array are 32 bytes of Encryption Array that are initially unprogrammed (all 1s). Every time that a byte is addressed during a verify, address lines are used to select a byte of the Encryption array. This byte is then exclusive-NORed (XNOR) with the code byte, creating an Encrypted Verify byte. The algorithm, with the array in the unprogrammed state (all 1s), will return the code in its original, un- modified form. It is recommended that whenever the Encryption Array is used, at least one of the Lock Bits be programmed as well.
1 U U No program lock features. that P3.5 and P3.7 need to be pulled to a logic low. Table 10. EPROM Programming Modes
- Vcc = 5 V 10 % during program-
- P3.2/PROG receives 10 programming pulses
and high for a minimum of 10uS.
Figure 7. EPROM Programming and Verification Figure 8. Programming Waveform
10 PULSES
8-Bit CMOS Microcontorller GMS97C2051/L2051 HYUNDAI MicroElectonics15 Absolute Maximum Ratings Ambient temperature Voltage on VCC pin Voltage on any pin Input Current on any pin Absolute sum of all input current NOTE : Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for longer periods may affect device reliability. During overload conditions IN > Vcc or VIN < Vss ) the voltage on Vcc pins with respect to ground (Vss) must not exceed the values defined by the absolute maximum ratings.
GMS97C2051/L2051 8-Bit CMOS Microcontroller HYUNDAI MicroElectronics 16 D.C. Characteristics (5V Version) Vcc = 4.25V to 5.5V, Vss= 0V, TA= 0 O C to 70 O C f o r t h e GMS97C2051/C1051 Parameter Symbol Limit Values Unit Test Min Max Condition Input Low Voltage V IL -0.5 0.2Vcc-0.1 V Input High Voltage (Except XTAL1, RST) VIH 0.5Vcc-0.1 Vcc+0.5 V Input High Voltage (XTAL1, RST) VIH1 0.7Vcc Vcc+0.5 V Output Low Voltage (ports 1,3) VOL 0.45 V I OL =10mA,Vcc=5V Output High Voltage (ports 1,3) VOH 2.4 0.75Vcc 0.9Vcc VI OH = -80uA, Vcc=5V±10% IOH = -30uA IOH = -12uA Logical 0 Input Current (ports 1,3) I IL -50 uA V IN=0.45V Logical 1-to-0 Transition Current (ports 1,3) ITL -750 uA V IN=2V Input Leakage Current (Port P1.0, P1.1) ILI ±1uA uA 0<V IN<Vcc Comparator Input Offset Voltage VOS 200 mV Vcc=5V Comparator Input Common Mode Voltage VCM 0V c c V Pin Capacitance C IO 10 pF Test Freq.=1MHz, TA=25 O C Power supply current: Active mode, 12Mhz Idle mode, 12Mhz Active mode, 24Mhz Idle mode, 24Mhz Power Down mode Icc Iccidle Icc Iccidle Ipd 100 mA mA mA mA uA Vcc=5.0V Vcc=5.0V, P1.0&P1.1=0 or Vcc Vcc=5.0V Vcc=5.0V, P1.0&P1.1=0 or Vcc Vcc=5.0V, P1.0&P1.1=0 or Vcc
8-Bit CMOS Microcontorller GMS97C2051/L2051 HYUNDAI MicroElectonics17 D.C. Characteristics (3V Version) Vcc = 2.7V to 3.6V, Vss= 0V, TA= 0 O C to 70 O C f o r t h e GMS97L2051/L1051 Parameter Symbol Limit Values Unit Test Min Max Condition Input Low Voltage V IL -0.5 0.2Vcc-0.1 V Input High Voltage (Except XTAL1, RST) VIH 0.5Vcc-0.1 Vcc+0.5 V Input High Voltage (XTAL1, RST) VIH1 0.7Vcc Vcc+0.5 V Output Low Voltage (ports 1,3) VOL 0.45 V I OL =6mA,Vcc=2.7V Output High Voltage (ports 1,3) VOH 0.75Vcc 0.9Vcc VI OH = -30uA IOH = -12uA Logical 0 Input Current (ports 1,3) I IL -50 uA V IN=0.45V Logical 1-to-0 Transition Current (ports 1,3) ITL -750 uA V IN=2V Input Leakage Current (Port P1.0, P1.1) ILI ±1uA uA 0<V IN<Vcc Comparator Input Offset Voltage VOS 200 mV Vcc=3V Comparator Input Common Mode Voltage VCM 0V c c V Pin Capacitance C IO 10 pF Test Freq.=1MHz, TA=25 O C Power supply current: Active mode, 12Mhz Idle mode, 12Mhz Power Down mode Icc Iccidle Ipd mA mA uA Vcc=3V Vcc=3V, P1.0&P1.1=0 or Vcc Vcc=3V, P1.0&P1.1=0 or Vcc
GMS97C2051/L2051 8-Bit CMOS Microcontroller HYUNDAI MicroElectronics 18 External Clock drive waveforms tCHCX tCLCL tCLCX tCHCX tCLCH
0.7 VCC
0.2 VCC - 0.1V 0.45V VCC - 0.5 V tCHCL External Clock Drive Symbol Parameter GMS97L2051/L1051 GMS97C2051/C1051 Min Max Min Max Units 1/tCLCL Oscillator Frequency 0 12 0 24 MHz tCLCL Clock Period 83.3 41.6 ns tCHCX High Time 30 15 ns tCLCX Low Time 30 15 ns tCLCH Rise Time - 20 - 20 ns tCHCL Fall Time - 20 - 20 ns AC Testing Input/Output Waveforms(1) VCC - 0.5V 0.45V 0.2VCC + 0.9V TEST POINTS 0.2V CC - 0.1V Note: 1. AC Inputs during testing are driven at VCC - 0.5V for a logic 1 and 0.45V for a logic 0. Timing measurements are made at V IH min. for a logic 1 and VIL max. for a logic 0. Float Waveforms(1) VLOAD + 0.1V VLOAD VLOAD - 0.1V VOL + 0.1V VOL + 0.1V Timing Reference Points Note: 1. For timing purposes, a port pin is no longer floating when a 100mV change from load voltage occurs. A port pin begins to float when a 100mV change from the loaded V OH /VOL level occurs.
8-Bit CMOS Microcontorller GMS97C2051/L2051 HYUNDAI MicroElectronics19 Package Dimension
20 PDIP
20 SOP
unit : mm ( inch )
GMS97C2051/L2051 8-Bit CMOS Microcontroller HYUNDAI MicroElectronics 20
Ordering Information
Speed ( MHz) Power Supply Ordering Code Package Operation Range 12 2.7V to 3.6V GMS97L2051 20 PDIP GMS97L2051-D 20 SOP 4.25V to 5.5V GMS97C2051 20 PDIP Commercial GMS97C2051-D 20 SOP (0 /G02 to 70/G02 ) 24 4.25V to 5.5V GMS97C2051-24 20 PDIP GMS97C2051-24D 20 SOP Package Type 20 PDIP 20 Lead, 0.300/G03 Wide, Plastic Dual Inline Package (PDIP) 20 SOP 20 Lead, 0.300/G03 Wide, Plastic Gull Wing Small Outline (SOP)
8-Bit CMOS Microcontorller GMS97C1051/L1051 HYUNDAI MicroElectronics21 Compatible with MCS-51TM Products
1 Kbytes of programmable EPROM
4.25V to 5.5V Operating Range (GMS97C1051) 2.70V to 3.6V Operating Range (GMS97L1051) Version for 12MHz / 24 MHz Operating frequency (GMS97C1051) Only 12MHz Operating frequency (GMS97L1051) Two-Level Program Memory Lock with encryption array 64 bytes SRAM Low Power Idle and Power Down Modes The GMS97C1051/L1051 is a high-performance CMOS 8-bit microcontroller with 1Kbytes of programmable EPROM. The device is compatible with the industry standard MCS-51TM instruction set and pinout. The HYUNDAI MicroElectronics GMS97C1051/L1051 is a powerful microcontroller which provides a highly flexi- ble and cost effective solution to many embedded control applications. The GMS97C1051/L1051 provides the following standard features: 1Kbytes of EPROM, 64 bytes of RAM, 15 I/O lines, 16-bit timer/counter, a three vector two-level interrupt architecture, a precision analog comparator, on-chip oscillator and clock circuitry. In addition, the GMS97C1051/L1051 supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power Down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset. Pin Configuration (T0) P3.4 VCC P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 (AIN1) P1.0 (AIN0) P3.7 RST P3.0 P3.1 XTAL2 XTAL1 (INT1) P3.3 P3.5 GND PDIP/SOP (INT0 )P3.2
GMS97C1051/L1051 8-Bit CMOS Microcontroller HYUNDAI MicroElectronics 22 Block Diagram VCC GND P1.0-P1.7 RAM ADDR RAM STACK POINTER PC INCREMENTER PROGRAM COUNTER ACC EPROM PROGRAM ADDRESS REGISTER BUFFER DPTR TMP1TMP2 PSW B REGISTER INTERRUPT , TIMER BLOCKS OSC PORT 3 LATCH PORT 1 LATCH TIMING AND CONTROL INSTRUCTION REGISTER PORT 1 DRIVERS PORT 3 DRIVERS RST P 3 . 0 - P 3 . 5 P 3 . 7 ANALOG COMPARATOR ALU
values of the new bits will always be 0. Table 1. GMS97C1051/L1051 SFR Map and Reset Values
illustrates the input clock logic. Table 4. Timer / Counter 0 Operating Modes
Table 5. Interrupt Sources and their corresponding Interrupt Vectors Table 6. Interrupt Priority-Within-Level limits may cause unknown program behavior. boundaries may cause erratic execution. family architecture have been preserved.
- MOVX-related instructions, Data Memory:
structions should be included in the program.
or set to ‘1’ if external pullups are used. cycles before the internal reset algorithm takes control. this event, but access to the port pins is not inhibited. that writes to a port pin or to external memory. enough to allow the oscillator to restart and stabilize. ( similar to power-on reset ). Table 7. Power Saving Modes Overview
- CPU status registers maintain their data.
GMS97C1051/L1051 8-Bit CMOS Microcontroller HYUNDAI MicroElectronics 30 Programming The EPROM The GMS97C1051/L1051 is programmed by using a modified Quick-Pulse ProgrammingTM algorithm. It differs from older methods in the value used for VPP (programming supply voltage) and in the width and number of the P3.2(PROG ) . The GMS97C1051/L1051 contains two signature bytes that can be read and used by an EPROM pro- gramming system to identify the device. The signature bytes identify the device as an manufactured by HME. Table 8 shows the logic levels for reading the signature byte, and for programming the program memory, the encryption table, and the security bits. The circuit con- figuration and waveforms for quick-pulse programming are shown in Figures 5 and Figure 8. Figure 6 shows the circuit configuration for normal program memory verification. EPROM Programming and Verification Internal Address Counter : The GMS97C1051/L1051 contains an internal EPROM address counter which is always set to 03FFH on the rising edge of RST after setting P3.0 to ‘H’ and is ad- vanced by applying continuous level transition to pin P3.0. Programming Algorithm : To program the GMS97C1051/L1051, the following sequence is recommended. 1. Power-up Sequence Apply power between V CC and GND pins with crystal oscillation. Set P3.0 to ‘H’. Set RST to GND. With all other pins floating, wait for greater than 1 0 m s . 2. Set pin RST to ‘H’ and pin P3.2 to ‘H’. 3. Apply the appropriate combination of ‘H’ or ‘L’ logic levels to pins P3.3, P3.4, P3.5, P3.7 to select one of the programming operations shown in the EPROM Programming Modes. (Table 8). To program and verify the array 4. The P3.0 level is pulled ‘L’ and apply data for code byte at location 0000H to P1.0 to P1.7 5. Raise RST to 12.75V to enable pr ogramming. 6. The P3.2( PROG ) is pulsed low 10 times as shown i n Figure 8. Each programming pulse is low for 100us(±10us) and high for a minimum of 10us. 7. To verify the programmed data, lower RST from 12.75V to logic ‘H’ level and set pins P3.3 to P3.7 to the appropriate levels. Output data can be read at the port P1 pins. At this time P3.0 should not be changed. 8. To program a byte at the next address location, P3.0 level transition is needed to advance the internal address counter. Apply new data to the port P1 pins. 9. Repeat step 5 through 8, changing data and advancing the address counter for the entire 1K b y t e s a r r a y . Program Verify : If lock bits LB1 and LB2 have not been programmed, code data can be read back via port P1 pins. 1. Set the internal address counter to 03FFH by bringing RST from ‘L’ to ‘H’ and reset the internal address counter to 0000H by bringing P3.0 from ‘H’ to ‘L’. 2. Apply the appropriate control signals for Read Code data to pins P3.3, P3.4, P3.5, P3.7 and read the output data at the port P1 pins. 3. The P3.0 level transition is taken to advance the internal address counter. 4. Read the next code data byte at the port P1 pins. 5. Repeat step 3 and 4 until the entire array is read. Program Memory Lock Bits The two-level Program Lock system consists of 2 Lock bits and a 32-byte Encryption Array which are used to protect the program memory against software piracy. Encryption Array : Within the EPROM array are 32 bytes of Encryption Array that are initially unprogrammed (all 1s). Every time that a byte is addressed during a verify, address lines are used to select a byte of the Encryption array. This byte is then exclusive-NORed (XNOR) with the code byte, creating an Encrypted Verify byte. The algorithm, with the array in the unprogrammed state (all 1s), will return the code in its original, un- modified form. It is recommended that whenever the Encryption Array is used, at least one of the Lock Bits be programmed as well.
1 U U No program lock features. that P3.5 and P3.7 need to be pulled to a logic low. Table 8. EPROM Programming Modes Notes:1. '0' = Valid low, '1' = Valid high for that pin.
- Vcc = 5 V 10 % during programming
- P3.2/PROG receives 10 programming pulses
and high for a minimum of 10uS.
GMS97C1051/L1051 8-Bit CMOS Microcontroller HYUNDAI MicroElectronics 34 Absolute Maximum Ratings Ambient temperature Voltage on VCC pin Voltage on any pin Input Current on any pin Absolute sum of all input current NOTE : Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for longer periods may affect device reliability. During overload conditions IN > Vcc or VIN < Vss ) the voltage on Vcc pins with respect to ground (Vss) must not exceed the values defined by the absolute maximum ratings.
8-Bit CMOS Microcontorller GMS97C1051/L1051 HYUNDAI MicroElectronics35 D.C. Characteristics (5V Version) Vcc = 4.25V to 5.5V, Vss= 0V, TA= 0 O C to 70 O C f o r t h e GMS97C2051/C1051 Parameter Symbol Limit Values Unit Test Min Max Condition Input Low Voltage V IL -0.5 0.2Vcc-0.1 V Input High Voltage (Except XTAL1, RST) VIH 0.5Vcc-0.1 Vcc+0.5 V Input High Voltage (XTAL1, RST) VIH1 0.7Vcc Vcc+0.5 V Output Low Voltage (ports 1,3) VOL 0.45 V I OL =10mA,Vcc=5V Output High Voltage (ports 1,3) VOH 2.4 0.75Vcc 0.9Vcc VI OH = -80uA, Vcc=5V±10% IOH = -30uA IOH = -12uA Logical 0 Input Current (ports 1,3) I IL -50 uA V IN=0.45V Logical 1-to-0 Transition Current (ports 1,3) ITL -750 uA V IN=2V Input Leakage Current (Port P1.0, P1.1) ILI ±1uA uA 0<V IN<Vcc Comparator Input Offset Voltage VOS 200 mV Vcc=5V Comparator Input Common Mode Voltage VCM 0V c c V Pin Capacitance C IO 10 pF Test Freq.=1MHz, TA=25 O C Power supply current: Active mode, 12Mhz Idle mode, 12Mhz Active mode, 24Mhz Idle mode, 24Mhz Power Down mode Icc Iccidle Icc Iccidle Ipd 100 mA mA mA mA uA Vcc=5.0V Vcc=5.0V, P1.0&P1.1=0 or Vcc Vcc=5.0V Vcc=5.0V, P1.0&P1.1=0 or Vcc Vcc=5.0V, P1.0&P1.1=0 or Vcc
GMS97C1051/L1051 8-Bit CMOS Microcontroller HYUNDAI MicroElectronics 36 D.C. Characteristics (3V Version) Vcc = 2.7V to 3.6V, Vss= 0V, TA= 0 O C to 70 O C f o r t h e GMS97L2051/L1051 Parameter Symbol Limit Values Unit Test Min Max Condition Input Low Voltage V IL -0.5 0.2Vcc-0.1 V Input High Voltage (Except XTAL1, RST) VIH 0.5Vcc-0.1 Vcc+0.5 V Input High Voltage (XTAL1, RST) VIH1 0.7Vcc Vcc+0.5 V Output Low Voltage (ports 1,3) VOL 0.45 V I OL =6mA,Vcc=2.7V Output High Voltage (ports 1,3) VOH 0.75Vcc 0.9Vcc VI OH = -30uA IOH = -12uA Logical 0 Input Current (ports 1,3) I IL -50 uA V IN=0.45V Logical 1-to-0 Transition Current (ports 1,3) ITL -750 uA V IN=2V Input Leakage Current (Port P1.0, P1.1) ILI ±1uA uA 0<V IN<Vcc Comparator Input Offset Voltage VOS 200 mV Vcc=3V Comparator Input Common Mode Voltage VCM 0V c c V Pin Capacitance C IO 10 pF Test Freq.=1MHz, TA=25 O C Power supply current: Active mode, 12Mhz Idle mode, 12Mhz Power Down mode Icc Iccidle Ipd mA mA uA Vcc=3V Vcc=3V, P1.0&P1.1=0 or Vcc Vcc=3V, P1.0&P1.1=0 or Vcc
8-Bit CMOS Microcontorller GMS97C1051/L1051 HYUNDAI MicroElectronics37 External Clock drive waveforms tCHCX tCLCL tCLCX tCHCX tCLCH 0.2 VCC - 0.1V 0.45V VCC - 0.5 V tCHCL External Clock Drive Symbol Parameter GMS97L2015/L1051 GMS97C2051/C1051 Min Max Min Max Units 1/tCLCL Oscillator Frequency 0 12 0 24 MHz tCLCL Clock Period 83.3 41.6 ns tCHCX High Time 30 15 ns tCLCX Low Time 30 15 ns tCLCH Rise Time - 20 - 20 ns tCHCL Fall Time - 20 - 20 ns AC Testing Input/Output Waveforms(1) VCC - 0.5V 0.45V 0.2VCC + 0.9V TEST POINTS 0.2V CC - 0.1V Note: 1. AC Inputs during testing are driven at VCC - 0.5V for a logic 1 and 0.45V for a logic 0. Timing measurements are made at V IH min. for a logic 1 and VIL max. for a logic 0. Float Waveforms(1) VLOAD + 0.1V VLOAD VLOAD - 0.1V VOL + 0.1V VOL + 0.1V Timing Reference Points Note: 1. For timing purposes, a port pin is no longer floating when a 100mV change from load voltage occurs. A port pin begins to float when a 100mV change from the loaded V OH /VOL level occurs.
GMS97C1051/L1051 8-Bit CMOS Microcontroller HYUNDAI MicroElectronics 38 Package Dimension unit : mm ( inch )
8-Bit CMOS Microcontorller GMS97C1051/L1051 HYUNDAI MicroElectronics39 Speed ( MHz) Power Supply Ordering Code Package Operation Range 12 2.7V to3.6V GMS97L1051 20 PDIP GMS97L1051-D 20 SOP 4.25V to 5.5V GMS97C1051 20 PDIP Commercial GMS97C1051-D 20 SOP (0 /G02 to 70/G02 ) 24 4.25V to 5.5V GMS97C1051-24 20 PDIP GMS97C1051-24D 20 SOP Package Type 20 PDIP 20 Lead, 0.300/G03 Wide, Plastic Dual Inline Package (PDIP) 20 SOP 20 Lead, 0.300/G03 Wide, Plastic Gull Wing Small Outline (SOP)