PE9704 PEREGRINE | Alldatasheet
Document overview
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Technical content
Features
- 3.0 GHz operation
- ÷10/11 dual modulus prescaler
- Phase detector output
- Serial interface or hardwired programmable
- Ultra-low phase noise
- SEU < 10-9 errors / bit-day
- 100 Krad (Si) total dose
- 44-lead CQFJ Peregrines PE9704 is a high-performance integer-N PLL capable of frequency synthesis up to 3.0 GHz. The device is designed for superior phase noise performance while providing an order of magnitude reduction in current consumption, when compared with existing commercial space PLLs. The PE9704 features a ÷10/11 dual modulus prescaler, counters, and a phase comparator as shown in Figure 1. Counter values are programmable through a serial interface, and can also be directly hard wired. The PE9704 is optimized for commercial space applications. Single Event Latch-up (SEL) is physically impossible and Single Event Upset (SEU) is better than -9 errors per bit / day. Fabricated in Peregrines patented UTSi® (Ultra Thin Silicon) CMOS technology, the PE9704 offers excellent RF performance and intrinsic radiation tolerance. FIN Prescaler Main Counter 20-Bit Frequency Register M(8:0) A(3:0) R(5:0) 19* R CounterFR Phase Detector 6 6 Serial Control PD_U PD_D3 MSEL fp fc Direct Control * prescaler bypass not available in Direct mode LD Ce x t
Figure 2. Pin Configuration Table 1. Pin Descriptions
2 R 0 Direct Input R Counter bit0
3 R 1 Direct Input R Counter bit1
4 R 2 Direct Input R Counter bit2
5 R 3 Direct Input R Counter bit3
6 GND Both (Note 1) Ground
7 R 4 Direct Input R Counter bit4
8 R 5 Direct Input R Counter bit5 (MSB)
9 M 0 Direct Input M Counter bit0
10 M 1 Direct Input M Counter bit1
11 V DD Both (Note 1) Same as pin 1
12 V DD Both (Note 1) Same as pin 1
13 M 2 Direct Input M Counter bit2
14 M 3 Direct Input M Counter bit3
16 DATA Serial Input
high) on the rising edge of CLOCK.
PEREGRINE SEMICONDUCTOR CORP. | http://www.peregrine-semi.com Copyright Peregrine Semiconductor Corp. 2003 Page 3 of 12 Pin No. Pin Name Interface Mode Type Description M5 Direct Input M Counter bit5
17 GND Both Ground
CLOCK Serial Input Clock input. Data is clocked serially into either the 20-bit primary register (E_WR low) or the 8-bit enhancement register (E_WR high) on the rising edge of CLOCK. 18 M6 Direct Input M Counter bit6
19 M 7 Direct Input M Counter bit7
20 M 8 Direct Input M Counter bit8 (MSB)
21 A 0 Direct Input A Counter bit0
22 D MODE Both Input Selects direct interface mode (D MODE=1) or serial interface mode (DMODE=0)
23 V DD Both (Note 1) Same as pin 1
E_WR Serial Input Enhancement register write enable. While E_WR is high, DATA can be serially clocked into the enhancement register on the rising edge of CLOCK. 24 A1 Direct Input A Counter bit1.
25 A 2 Direct Input A Counter bit2
26 A 3 Direct Input A Counter bit3 (MSB)
27 F IN Both Input RF prescaler input from the VCO. 3.0 GHz maximum frequency. 28 GND Both Ground. 29 GND Both Ground. 30 N/C No connect.
31 V DD Both (Note 1) Same as pin 1
32 D OUT Serial Output Data Out. The Main Counter output, R Counter output, or dual modulus prescaler select (MSEL) can be routed to DOUT through enhancement register programming.
33 V DD Both (Note 1) Same as pin 1
34 N/C No connect. 35 GND Both Ground. 36 PD_ D Both Output PD_ D pulses down when fp leads fc. 37 PD_ U Both PD_ U pulses down when fc leads fp.
38 V DD Both (Note 1) Same as pin 1
39 C EXT Both Output
Logical NAND of PD_U and PD_D, passed through an on-chip, 2 kΩ series resistor. Connecting CEXT to an external capacitor will low pass filter the input to the inverting amplifier used for driving LD.
40 GND Both Ground
41 GND Both Ground
42 F R Both Input Reference frequency input
43 ENH Both Output, OD Enhancement mode. When asserted low (0), enhancement register bits are functional. 44 LD Serial Output Lock detect output, the open-drain logical inversion of CEXT. When the loop is locked, LD is high impedance; otherwise LD is a logic low (0). Note 1: V DD pins 1, 11, 12, 23, 31, 33, 35, and 38 are connected by diodes and must be supplied with the same positive voltage level. Note 2: All digital input pins have 70 k Ω pull-down resistors to ground.
Table 2. Absolute Maximum Ratings Table 3. Operating Ratings Table 4. ESD Ratings rating specified in Table 4. devices are immune to latch-up.
Table 5. DC Characteristics Counter and phase detector outputs: fc, fp.
Table 6. AC Characteristics Note 2: CMOS logic levels can be used to drive reference input if DC coupled. Voltage input needs to be a minimum of 0.5Vp-p. Note 3: Parameter is guaranteed through characterization only and is not tested.
PEREGRINE SEMICONDUCTOR CORP. | http://www.peregrine-semi.com Copyright Peregrine Semiconductor Corp. 2003 Page 7 of 12 Functional Description The PE9704 consists of a prescaler, counters, a phase detector, and control logic. The dual modulus prescaler divides the VCO frequency by either 10 or 11, depending on the value of the modulus select. Counters R and M divide the reference and prescaler output, respectively, by integer values stored in a 20-bit register. An additional counter (A) is used in the modulus select logic. The phase-frequency detector generates up and down frequency control signals. The control logic includes a selectable chip interface. Data can be written via a serial bus or hardwired directly to the pins. There are also various operational and test modes and a lock detect output. Main Counter Chain Normal Operating Mode Setting the PB control bit low enables the ÷10/11 prescaler. The main counter chain then divides the RF input frequency (F IN) by an integer derived from the values in the M and A counters. In this mode, the output from the main counter chain (fp) is related to the VCO frequency (FIN) by the following equation: where A ≤ M + 1, 1 ≤ M ≤ 511 When the loop is locked, FIN is related to the reference frequency (FR) by the following equation: where A ≤ M + 1, 1 ≤ M ≤ 511 A consequence of the upper limit on A is that FIN must be greater than or equal to 90 x (FR / (R+1)) to obtain contiguous channels. The A counter can accept values as high as 15, but in typical operation it will cycle from 0 to 9 between increments in M. Programming the M counter with the minimum allowed value of 1 will result in a minimum M counter divide ratio of 2. Prescaler Bypass Mode Setting the frequency control register bit PB high allows FIN to bypass the ÷10/11 prescaler. In this mode, the prescaler and A counter are powered down, and the input VCO frequency is divided by the M counter directly. This mode is only available when using the serial port to set the frequency control bits. The following equation relates F IN to the reference frequency FR: where 1 ≤ M ≤ 511 Reference Counter The reference counter chain divides the reference frequency F R down to the phase detector comparison frequency fc. The output frequency of the 6-bit R Counter is related to the reference frequency by the following equation: where 0 ≤ R ≤ 63 Note that programming R with 0 will pass the reference frequency (FR) directly to the phase detector.
Figure 3. Serial Interface Mode Timing Diagram Table 9. Enhancement Register Bit Functionality Bit 2 f p output Drives the M counter output onto the D OUT output. Bit 3 Power down Power down of all f unctions except programming interface. Bit 4 Counter load Immediate and conti nuous load of counter programming. Bit 5 MSEL output Drives the internal dual modul us prescaler modulus select (MSEL) onto the DOUT output.
Copyright Peregrine Semiconductor Corp. 2003 File No. 70/0083~00B | | UTSi CMOS RFIC SOLUTIONS Page 10 of 12 Phase Detector Outputs The phase detector is triggered by rising edges from the main counter (fp) and the reference counter (fc). It has two outputs, PD_U, and PD_D. If the divided VCO leads the divided reference in phase or frequency (f p leads fc), PD_D pulses low. If the divided reference leads the divided VCO in phase or frequency (f c leads fp), PD_U pulses low. The width of either pulse is directly proportional to phase offset between the two input signals, f p and fc. The phase detector gain is 430 mV / radian. PD_U and PD_D are designed to drive an active loop filter which controls the VCO tune voltage. PD_U pulses result in an increase in VCO frequency and PD_D results in a decrease in VCO frequency. Software tools for designing the active loop filter can be found at Peregrines web site (www.peregrine-semi.com Lock Detect Output A lock detect signal is provided at pin LD, via the pin CEXT (see Figure 1). CEXT is the logical NAND of PD_U and PD_D waveforms, driven through a series 2k ohm resistor. Connecting CEXT to an external shunt capacitor provides integration of this signal. The C EXT signal is then sent to the LD pin through an internal inverting comparator with an open drain output. Thus LD is an AND function of PD_U and PD_D.
Figure 4. Package Drawing Table 10. Ordering Information