PE9702 PEREGRINE | Alldatasheet
Document overview
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Technical content
Features
- 3.0 GHz operation
- ÷10/11 dual modulus prescaler
- Internal phase detector
- Serial, parallel or hardwired programmable
- Ultra-low phase noise
- SEU < 10-9 errors / bit-day
- 100 Krad (Si) total dose
- 44-lead CQFJ Peregrines PE9702 is a high-performance integer-N PLL capable of frequency synthesis up to 3.0 GHz. The device is designed for superior phase noise performance while providing an order of magnitude reduction in current consumption, when compared with existing commercial space PLLs. The PE9702 features a 10/11 dual modulus prescaler, counters and a phase comparator as shown in Figure 1. Counter values are programmable through either a serial or parallel interface and can also be directly hard wired. The PE9702 is optimized for commercial space applications. Single Event Latch up (SEL) is physically impossible and Single Event Upset (SEU) is better than -9 errors per bit / day. Fabricated in Peregrines patented UTSi® (Ultra Thin Silicon) CMOS technology, the PE9702 offers excellent RF performance and intrinsic radiation tolerance. Fin Fin Prescaler Main Counter Secon- dary 20-bit Latch Primary 20-bit Latch Pre_en M(6:0) A(3:0) R(3:0) R Counterfr Phase Detector 6 6 fc fp D(7:0) Sdata PD_U PD_D
Figure 2. Pin Configuration Table 1. Pin Descriptions 2 R 0 Direct Input R Counter bit0 (LSB). 3 R 1 Direct Input R Counter bit1. 4 R 2 Direct Input R Counter bit2. 5 R 3 Direct Input R Counter bit3. D0 Parallel Input Parallel data bus bit0 (LSB). M0 Direct Input M Counter bit0 (LSB). 8 D 1 Parallel Input Parallel data bus bit1. M 1 Direct Input M Counter bit1. 9 D 2 Parallel Input Parallel data bus bit2. M 2 Direct Input M Counter bit2. 10 D 3 Parallel Input Parallel data bus bit3. M 3 Direct Input M Counter bit3. 11 V DD ALL (Note 1) Same as pin 1. 12 V DD ALL (Note 1) Same as pin 1. register data is transferred to the secondary register on S_WR or Hop_WR rising edge.
PEREGRINE SEMICONDUCTOR CORP. | http://www.peregrine-semi.com Copyright Peregrine Semiconductor Corp. 2003 Page 3 of 15 Pin No. Pin Name Interface Mode Type Description D4 Parallel Input Parallel data bus bit4 M4 Direct Input M Counter bit4 Sdata Serial Input Binary serial data input. Input data entered MSB first. D5 Parallel Input Parallel data bus bit5. 14 M5 Direct Input M Counter bit5. Sclk Serial Input Serial clock input. Sdata is clocked serially into the 20-bit primary register (E_WR low) or the 8-bit enhancement register (E_WR high) on the rising edge of Sclk. D6 Parallel Input Parallel data bus bit6. 15 M6 Direct Input M Counter bit6. FSELS Serial Input Selects contents of primary register (FSELS=1) or secondary register (FSELS=0) for programming of internal counters while in Serial Interface Mode. D7 Parallel Input Parallel data bus bit7 (MSB). 16 Pre_en Direct Input Prescaler enable, active low. When high, F in bypasses the prescaler. 17 GND ALL Ground. FSELP Parallel Input Selects contents of primary register (FSELP=1) or secondary register (FSELP=0) for programming of internal counters while in Parallel Interface Mode. 18 A0 Direct Input A Counter bit0 (LSB). Serial Input Enhancement register write enable. While E_WR is high, Sdata can be serially clocked into the enhancement register on the rising edge of Sclk. E_WR Parallel Input Enhancement register write. D[7:0] are latched into the enhancement register on the rising edge of E_WR. A1 Direct Input A Counter bit1. M2_WR Parallel Input M2 write. D[3:0] are latched into the primary register (R[5:4], M[8:7]) on the rising edge of M2_WR. 20 A2 Direct Input A Counter bit2. Smode Serial, Parallel Input Selects serial bus interface mode (Bmode=0, Smode=1) or Parallel Interface Mode (Bmode=0, Smode=0). 21 A3 Direct Input A Counter bit3 (MSB). 22 Bmode ALL Input Selects direct interface mode ( Bmode=1). 23 V DD ALL (Note 1) Same as pin 1. 24 M1_WR Parallel Input M1 write. D[7:0] are latched into the primary register (Pre_en, M[6:0]) on the rising edge of M1_WR. 25 A_WR Parallel Input A write. D[7:0] are latched into the primary register (R[3:0], A[3:0]) on the rising edge of A_WR. 26 Hop_WR Serial, Parallel Input Hop write. The contents of the primary register are latched into the secondary register on the rising edge of Hop_WR. 27 F in ALL Input Prescaler input from the VCO. 3.0 GHz max frequency.
28 Fin ALL Input
Prescaler complementary input. A bypass capacitor in series with a 51 Ω resistor should be placed as close as possible to this pin and be connected directly to the ground plane. 29 GND ALL Ground. 30 f p ALL Output Monitor pin for main divider output. Switching activity can be disabled through enhancement register programming or by floating or grounding VDD pin 31.
Copyright Peregrine Semiconductor Corp. 2003 File No. 70/0036~00C | UTSi CMOS RFIC SOLUTIONS Page 4 of 15 Pin No. Pin Name Interface Mode Type Description 31 V DD-fp ALL (Note 1) V DD for fp. Can be left floating or connected to GND to disable the fp output. 32 Dout Serial, Parallel Output Data Out. The MSEL signal and the raw prescaler output are available on Dout through enhancement register programming. 33 V DD ALL (Note 1) Same as pin 1.
34 Cext ALL Output
Logical NAND of PD_U and PD_D terminated through an on chip, 2 kΩ series resistor. Connecting Cext to an external capacitor will low pass filter the input to the inverting amplifier used for driving LD. 35 V DD ALL (Note 1) Same as pin 1. 36 PD_ D ALL Output PD_ D is pulse down when fp leads fc. 37 PD_ U ALL PD_ U is pulse down when fc leads fp. 38 V DD-fc ALL (Note 1) V DD for fc. Can be left floating or connected to GND to disable the fc output. 39 f c ALL Output Monitor pin for reference divider output. Switching activity can be disabled through enhancement register programming or by floating or grounding VDD pin 38. 40 GND ALL Ground. 41 GND ALL Ground. 42 f r ALL Input Reference frequency input.
43 LD ALL Output,
Lock detect and open drain logical inversion of CEXT. When the loop is in lock, LD is high impedance, otherwise LD is a logic low (0). 44 Enh Serial, Parallel Input Enhancement mode. When asserted low (0), enhancement register bits are functional. Note 1: V DD pins 1, 11, 12, 23, 31, 33, 35, and 38 are connected by diodes and must be supplied with the same positive voltage level. V DD pins 31 and 38 are used to enable test modes and should be left floating. Note 2: All digital input pins have 70 k Ω pull-down resistors to ground.
Table 2. Absolute Maximum Ratings Table 3. Operating Ratings Table 4. ESD Ratings rating specified in Table 4. devices are immune to latch-up.
Table 5. DC Characteristics Counter and phase detector outputs: fc, fp.
Table 6. AC Characteristics Note 2: CMOS logic levels can be used to drive reference input if DC coupled. Voltage input needs to be a minimum of 0.5Vp-p. Note 3: Parameter is guaranteed through characterization only and is not tested.
generates up and down frequency control signals. Figure 3. Functional Block Diagram
PEREGRINE SEMICONDUCTOR CORP. | http://www.peregrine-semi.com Copyright Peregrine Semiconductor Corp. 2003 Page 9 of 15 Main Counter Chain Normal Operating Mode The main counter chain divides the RF input frequency, Fin, by an integer derived from the user- defined values in the M and A counters. It is composed of the 10/11 dual modulus prescaler, modulus select logic, and 9-bit M counter. Setting Pre_en low enables the 10/11 prescaler. Setting Pre_en high allows F in to bypass the prescaler and powers down the prescaler. The output from the main counter chain, fp, is related to the VCO frequency, Fin, by the following equation: where A ≤ M + 1, 1 ≤ M ≤ 511 When the loop is locked, Fin is related to the reference frequency, fr, by the following equation: where A ≤ M + 1, 1 ≤ M ≤ 511 A consequence of the upper limit on A is that Fin must be greater than or equal to 90 x (fr / (R+1)) to obtain contiguous channels. Programming the M Counter with the minimum value of 1 will result in a minimum M Counter divide ratio of 2. In Direct Interface Mode, main counter inputs M and M8 are internally forced low. In this mode, the M value is limited to 1 ≤ M ≤ 127. Prescaler Bypass Mode Setting Pre_en high allows Fin to bypass and power down the prescaler. In this mode, the 10/11 prescaler and A register are not active, and the input VCO frequency is divided by the M counter directly. The following equation relates F in to the reference frequency, fr: where 1 ≤ M ≤ 511 In Direct Interface Mode, main counter inputs M7 and M8 are internally forced low. In this mode, the M value is limited to 1 ≤ M ≤ 127. Reference Counter The reference counter chain divides the reference frequency, fr, down to the phase detector comparison frequency, fc. The output frequency of the 6-bit R Counter is related to the reference frequency by the following equation: where 0 ≤ R ≤ 63 Note that programming R with 0 will pass the reference frequency, fr, directly to the phase detector. In Direct Interface Mode, R Counter inputs R4 and R5 are internally forced low (0). In this mode, the R value is limited to 0 ≤ R ≤ 15. Register Programming Parallel Interface Mode Parallel Interface Mode is selected by setting the Bmode input low and the Smode input low. Parallel input data, D[7:0], are latched in a parallel fashion into one of three 8-bit primary register sections on the rising edge of M1_WR, M2_WR, or A_WR per the mapping shown in Table 7 on page 10. The contents of the primary register are transferred into a secondary register on the rising edge of Hop_WR according to the timing diagram shown in Figure 5. Data is transferred to the counters as shown in Table 7 on page 10. The secondary register acts as a buffer to allow rapid changes to the VCO frequency. This double buffering for ping-pong counter control is programmed via the FSELP input. When FSELP is high, the primary register contents set the counter inputs. When FSELP is low, the secondary register contents are utilized. Parallel input data, D[7:0], are latched into the enhancement register on the rising edge of E_WR according to the timing diagram shown in Figure 4. This data provides control bits as shown in Table 8 on page 10 with bit functionality enabled by asserting the Enh input low.
Bmode input low and the Smode input high. counters as shown in Table 7 on page 10. register contents are utilized. asserting the Enh input low. and R5 are internally forced low (0). Table 7. Primary Register Programming *Serial data clocked serially on Sclk rising edge while E_WR low and captured in secondary register on S_WR rising edge. Table 8. Enhancement Register Programming *Serial data clocked serially on Sclk rising edge while E_WR high and captured in the double buffer on E_WR falling edge.
The functions of the enhancement register bits are shown below with all bits active high. Table 9. Enhancement Register Bit Functionality Bit 3 Power down Power down of all f unctions except programming interface. Bit 5 MSEL output Drives the internal dual modulus prescaler modulus select (MSEL) onto the Dout output. Bit 6 Prescaler output Drives the raw internal prescaler output (fmain) onto the Dout output. Bit 7 f p, fc OE f p, fc outputs disabled. loop filter which controls the VCO tune voltage.
Figure 6. Package Drawing
Table 10. Ordering Information