9701-01

PE9701 PEREGRINE | Alldatasheet

Document overview

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Technical content

Features

• 3.0 GHz operation
• ÷10/11 dual modulus prescaler
• Internal phase detector with charge pump
• Serial, parallel or hardwired programmable
• Ultra-low phase noise
• SEU < 10-9 errors / bit-day
• 100 Krad (Si) total dose
• 44-lead CQFJ

Figure 1. Block Diagram

Document No. 70-0035-02 │www.psemi.com ©2003-2006 Peregrine Semiconductor Corp. All rights reserved. Table 1. Pin Descriptions (continued)

Description

Binary serial data input. Input data entered MSB first. Parallel Input Parallel data bus bit5. Direct Input M Counter bit5. Sclk Serial Input Serial clock input. Sdata is clocked serially into the 20-bit primary register (E_WR “low”) or the 8-bit enhancement register (E_WR “high”) on the rising edge of Sclk. Parallel Input Parallel data bus bit6. Direct Input M Counter bit6. FSELS Serial Input Selects contents of primary register (FSELS=1) or secondary register (FSELS=0) for programming of internal counters while in Serial Interface Mode. Parallel Input Parallel data bus bit7 (MSB). Pre_en Direct Input Prescaler enable, active “low”. When “high”, Fin bypasses the prescaler. GND ALL Ground. FSELP Parallel Input Selects contents of primary register (FSELP=1) or secondary register (FSELP=0) for programming of internal counters while in Parallel Interface Mode. Direct Input A Counter bit0 (LSB). E_WR Serial Input Enhancement register write enable. While E_WR is “high”, Sdata can be serially clocked into the enhancement register on the rising edge of Sclk. Parallel Input Enhancement register write. D[7:0] are latched into the enhancement register on the rising edge of E_WR. Direct Input A Counter bit1. M2_WR Parallel Input M2 write. D[3:0] are latched into the primary register (R[5:4], M[8:7]) on the rising edge of M2_WR. Direct Input A Counter bit2. Smode Serial, Parallel Input Selects serial bus interface mode (Bmode=0, Smode=1) or Parallel Interface Mode (Bmode=0, Smode=0). Direct Input A Counter bit3 (MSB). Bmode ALL Input Selects direct interface mode (Bmode=1). VDD ALL (Note 1) Same as pin 1. M1_WR Parallel Input M1 write. D[7:0] are latched into the primary register (Pre_en, M[6:0]) on the rising edge of M1_WR. A_WR Parallel Input A write. D[7:0] are latched into the primary register (R[3:0], A[3:0]) on the rising edge of A_WR. Hop_WR Serial, Parallel Input Hop write. The contents of the primary register are latched into the secondary register on the rising edge of Hop_WR. Fin ALL Input Prescaler input from the VCO. 3.0 GHz max frequency. Fin ALL Input Prescaler complementary input. A bypass capacitor in series with a 51 Ω resistor should be placed as close as possible to this pin and be connected directly to the ground plane. GND ALL Ground. fp ALL Output Monitor pin for main divider output. Switching activity can be disabled through enhancement register programming or by floating or grounding VDD pin 31.

©2003-2006 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0035-02 │UltraCMOS™ RFIC Solutions Note 1: VDD pins 1, 11, 12, 23, 31, 33, 35, and 38 are connected by diodes and must be supplied with the same positive voltage level. VDD pins 31 and 38 are used to enable test modes and should be left floating. All digital input pins have 70 kΩ pull-down resistors to ground. (Note 1) VDD for fp Dout Serial, Parallel Output Data Out. The MSEL signal and the raw prescaler output are available on Dout through enhancement register programming. VDD ALL (Note 1) Same as pin 1. Cext ALL Output Logical “OR” of PD_U and PD_D terminated through an on chip, 2 kΩ series resistor. Connecting Cext to an external capacitor will low pass filter the input to the inverting amplifier used for driving LD. VDD ALL (Note 1) Same as pin 1. CP ALL Output Charge pump current is sourced for “up” when fc leads fp and sinked for “down” when fc lags fp. NC ALL No connection. VDD-fc ALL (Note 1) VDD for fc fc ALL Output Monitor pin for reference divider output. Switching activity can be disabled through enhancement register programming or by floating or grounding VDD pin 38. GND ALL Ground. GND ALL Ground. fr ALL Input Reference frequency input. LD ALL Output, OD Lock detect and open drain logical inversion of Cext. When the loop is in lock, LD is high impedance, otherwise LD is a logic low (“0”). Enh Serial, Parallel Input Enhancement mode. When asserted low (“0”), enhancement register bits are functional.

©2003-2006 Peregrine Semiconductor Corp. All rights reserved. Table 2. Absolute Maximum Ratings Table 4. ESD Ratings exceeding the specified rating in Table 4. devices are immune to latch-up. Table 3. Operating Ratings Table 5. DC Characteristics: VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified Counter and phase detector outputs: fc, fp.

©2003-2006 Peregrine Semiconductor Corp. All rights reserved. Table 6. AC Characteristics: VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified Note 2: CMOS logic levels can be used to drive reference input if DC coupled. Voltage input needs to be a minimum of 0.5 Vp-p. Parameter is guaranteed through characterization only, and is not tested.

©2003-2006 Peregrine Semiconductor Corp. All rights reserved. phase detector, a charge pump, and control logic. parallel bus, or hardwired directly to the pins. Figure 4. Functional Block Diagram

©2003-2006 Peregrine Semiconductor Corp. All rights reserved. and powers down the prescaler. a minimum M Counter divide ratio of “2”. M value is limited to 1 ≤ M ≤ 127. M value is limited to 1 ≤ M ≤ 127. detector comparison frequency, fc. mode, the R value is limited to 0 ≤ R ≤ 15. Bmode input “low” and the Smode input “low”. to the counters as shown in Table 7 on page 9. the secondary register contents are utilized. Figure 5. This data provides control bits as

©2003-2006 Peregrine Semiconductor Corp. All rights reserved. Bmode input “low” and the Smode input “high”. the counters as shown in Table 7 on page 9. secondary register contents are utilized. register on the rising edge of Sclk, MSB (B0) first.

1. After the falling edge of E_WR, the data

R4 and R5 are internally forced low (“0”). Table 7. Primary Register Programming Table 8. Enhancement Register Programming *Serial data clocked serially on Sclk rising edge while E_WR “low” and captured in secondary register on S_WR rising edge. *Serial data clocked serially on Sclk rising edge while E_WR “high” and captured in the double buffer on E_WR falling edge.

Document No. 70-0035-02 │www.psemi.com ©2003-2006 Peregrine Semiconductor Corp. All rights reserved. pin CP. The current pulses from pin CP are low pass filtered externally and then connected to the VCO tune voltage. PD_U pulses result in a current source, which increases the VCO frequency; PD_D pulses result in a current sink, which decreases VCO frequency. A lock detect output, LD is also provided, via the pin Cext. Cext is the logical “NAND” of PD_U and PD_D waveforms, which is driven through a series 2k Ω resistor. Connecting Cext to an external shunt capacitor provides integration. Cext also drives the input of an internal inverting comparator with an open drain output. Thus LD is an “AND” function of PD_U and PD_D. See Figure 4 for a schematic of this circuit. Enhancement Register The functions of the enhancement register bits are shown below with all bits active “high”. Table 9. Enhancement Register Bit Functionality two input signals, fp and fc. Reserved Bit 1 Reserved Bit 2 Reserved** Bit 3 Power down Power down of all functions except programming interface. Bit 4 Counter load Immediate and continuous load of counter programming as directed by the Bmode and Smode inputs. Bit 5 MSEL output Drives the internal dual modulus prescaler modulus select (MSEL) onto the Dout output. Bit 6 Prescaler output Drives the raw internal prescaler output (fmain) onto the Dout output. Bit 7 fp, fc OE fp, fc outputs disabled.

©2003-2006 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0035-02 │UltraCMOS™ RFIC Solutions Figure 9. Package Drawing Table 10. Ordering Information

Document No. 70-0035-02 │www.psemi.com ©2003-2006 Peregrine Semiconductor Corp. All rights reserved. Sales Offices The Americas Peregrine Semiconductor Corporation

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