ICS95V857_09 ICST | Alldatasheet
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Systems, Inc. ICS95V857 0674U—01/27/09 Block Diagram 2.5V Wide Range Frequency Clock Driver (45MHz - 233MHz) Pin Configuration 48-Pin TSSOP/TVSOP Recommended Application: DDR Memory Modules / Zero Delay Board Fan Out Provides complete DDR registered DIMM solution with ICSSSTVF16857, ICSSSTVF16859 or ICSSSTV32852 Product Description/Features: Low skew, low jitter PLL clock driver 1 to 10 differential clock distribution (SSTL_2) Feedback pins for input to output synchronization PD# for power management Spread Spectrum-tolerant inputs Auto PD when input signal removed Specifications: Meets PC3200 Class A+ specification for DDR-I 400 support Covers all DDRI speed grades Switching Characteristics: CYCLE - CYCLE jitter: <50ps OUTPUT - OUTPUT skew: <40ps Period jitter: ±30ps STUPNIS TUPTUO etatSLLP DDVA# DPT NI_KLCC NI_KLCT KLCC KLCT TUO_BFC TUO_BF DNGH L H L H L H ffo/dessapyB DNGH H L H L H L ffo/dessapyB V5.2 )mon( LL H Z ZZ Z f fo V5.2 )mon( LH LZ ZZ Z f fo V5.2 )mon( HL HL HL H n o V5.2 )mon( HH LH LH L n o V5.2 )mon( X) zHM02< )1( ZZ Z Z f fo Functionality PLL FB_INT FB_INC CLK_INC CLK_INT PD# Control Logic FB_OUTT FB_OUTC CLKT0 CLKT1 CLKT2 CLKT3 CLKT4 CLKT5 CLKT6 CLKT7 CLKT8 CLKT9 CLKC0 CLKC1 CLKC2 CLKC3 CLKC4 CLKC5 CLKC6 CLKC7 CLKC8 CLKC9 6.10 mm Body, 0.50 mm Pitch = TSSOP 4.40 mm Body, 0.40 mm Pitch = TVSOP GND CLKC0 CLKT0 VDD CLKT1 CLKC1 GND GND CLKC2 CLKT2 VDD VDD C LK_INT C LK_INC VDD AVDD AGND GND CLKC3 CLKT3 VDD CLKT4 CLKC4 GND GND CLKC5 CLKT5 VDD CLKT6 CLKC6 GND GND CLKC7 CLKT7 VDD PD# FB_INT FB_INC VDD FB_OUT C FB_OUT T GND CLKC8 CLKT8 VDD CLKT9 CLKC9 GND ICS95V857
0674U—01/27/09 Pin Configuration 40-Pin MLF 56-Ball BGA Top View GND CLKC2 CLKT2 VDD CLK_INT CLK_INC VDD AVDD AGND GND CLKC7 CLKT7 VDD PD# FB_INT FB_INC VDD VDD FB_OUTC FB_OUTT CLKC3 CLKT3 VDD CLKT4 CLKC4 CLKC9 CLKT9 VDD CLKT8 CLKC8 CLKC1 CLKT1 VDD CLKT0 CLKC0 CLKC5 CLKT5 VDD CLKT6 CLKC6 11 20 ICS95V857 A B 123456 C D E F G H J K 12345 6 A CLKT0 CLKC0 GND GND CLKC5 CLKT5 B CLKC1 CLKT1 VDD VDD CLKT6 CLKC6 C GND GND NC NC GND GND D CLKT2 CLKC2 NC NC CLKC7 CLKT7 E VDD VDD NB NB VDD PD# F CLK_INT CLK_INC NB NB FB_INC FB_INT G VDD AVDD NC NC FB_OUTC VDD H AGND GND NC NC GND FB_OUTT J CLKC3 CLKT3 VDD VDD CLKT8 CLKC8 K CLKT4 CLKC4 GND GND CLKC9 CLKT9
0674U—01/27/09 Pin Descriptions EMANNIPE PYTN OITPIRCSED DDVR WPV 5.2,ylppusrewoP DNGR WPd nuorG DDVAR WPV 5.2,ylppusrewopgolanA DNGAR WPd nuorggolanA )0:9(TKLCT UOs tuptuoriaplaitnereffidfokcolC"eurT" )0:9(CKLCT UOs tuptuoriaplaitnereffidfoskcolc"yratnemelpmoC" CNI_KLCN It upnikcolcecnerefer"yratnemelpmoC" TNI_KLCN It upnikcolcecnerefer"eurT" CTUO_BFT UO tI.kcabdeeflanretxerofdetacided,tuptuokcabdeeF"yratnemelpmoC" deriwebtsumtuptuosihT.KLCehtsaycneuqerfemasehttasehctiws CNI_BFot TTUO_BFT UO sehctiwstI.kcabdeeflanretxerofdetacided,tuptuokcabdeeF""eurT" otderiwebtsumtuptuosihT.KLCehtsaycneuqerfemasehtta TNI_BF TNI_BFN I rofLLPlanretniehtotlangiskcabdeefsedivorp,tupnikcabdeeF"eurT" rorreesahpetanimileotTNI_KLChtiwnoitazinorhcnys CNI_BFN I LLPlanretniehtotlangissedivorp,tupnikcabdeeF"yratnemelpmoC" rorreesahpetanimileotCNI_KLChtiwnoitazinorhcnysrof #DPN It upniSOMCVL.nwoDrewoP This PLL Clock Buffer is designed for a VDD of 2.5V, an AVDD of 2.5V and differential data input and output levels. The ICS95V857 is a zero delay buffer that distributes a differential clock input pair (CLK_INC, CLK_INT) to ten differential pair of clock outputs (CLKT[0:9], CLKC[0:9]) and one differential pair feedback clock output (FB_OUT, FB_OUTC). The clock outputs are controlled by the input clocks (CLK_INC, CLK_INT), the feedback clocks (FB_INT, FB_INC), the 2.5-V LVCMOS input (PD#) and the Analog Power input (AV DD ). When input (PD#) is low while power is applied, the receivers are disabled, the PLL is turned off and the differential clock outputs are tri-stated. When AVDD is grounded, the PLL is turned off and bypassed for test purposes. When the input frequency is less than the operating frequency of the PLL, appproximately 20MHz, the device will enter a low power mode. An input frequency detection circuit on the differential inputs, independent from the input buffers, will detect the low frequency condition and perform the same low power features as when the (PD#) input is low. When the input frequency increases to greater than approximately 20 MHz, the PLL will be turned back on, the inputs and outputs will be enabled and PLL will obtain phase lock between the feedback clock pair (FB_INT, FB_INC) and the input clock pair (CLK_INC, CLK_INT). The PLL to the ICS95V857 clock driver uses the input clocks (CLK_INC, CLK_INT) and the feedback clocks (FB_INT, FB_INC) provide high-performance, low-skew, low-jitter, output differential clocks (CLKT[0:9], CLKC[0:9]). The ICS95V857 is also able to track Spread Spectrum Clock (SSC) for reduced EMI. The ICS95V857 is characterized for operation from 0°C to 85°C, and will meet JEDEC Standard 82-1 and 82-1A Class A+ for registered DDR clock drivers.
0674U—01/27/09 Absolute Maximum Ratings Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 85°C; Supply Voltage AVDD , VDD = 2.5V ± 0.2V PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input High Current I IH VI = VDD or GND 5 µA Input Low Current I IL VI = VDD or GND 5 µA IDD2.5 CL = 0pf @ 200MHz 148 170 mA IDDPD CL = 0pf 100 µA Output High Current I OH VDD = 2.3V, VOUT = 1V -18 -32 mA Output Low Current I OL VDD = 2.3V, VOUT = 1.2V 26 35 mA High Impedance Output Current IOZ VDD =2.7V, Vout=VDD or GND ±10 mA Input Clamp Voltage V IK VDDQ = 2.3V Iin = -18mA -1.2 V VDD = min to max, IOH = -1 mA V DDQ - 0.1 V VDDQ = 2.3V, IOH = -12 mA 1.7 V VDD = min to max IOL =1 mA 0.1 V VDDQ = 2.3V IOH =12 mA 0.6 V Input Capacitance1 CIN VI = GND or VDD 3p F Output Capacitance1 C OUT VOUT = GND or VDD 3p F 1Guaranteed by design at 220MHz, not 100% tested in production. Operating Supply Current High-level output voltage VOH Low-level output voltage VOL
0674U—01/27/09 Recommended Operating Condition (see note1) TA = 0 - 85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage V DD , AVDD 2.3 2.5 2.7 V CLKT, CLKC, FB_INC 0.4 V DD /2 - 0.18 V PD# -0.3 0.7 V CLKT, CLKC, FB_INC V DD /2 + 0.18 2.1 V PD# 1.7 V DD + 0.6 V DC input signal voltage (note 2) VIN -0.3 V DD + 0.3 V DC - CLKT, FB_INT 0.36 V DD + 0.6 V AC - CLKT, FB_INT 0.7 V DD + 0.6 V Output differential cross- voltage (note 4) VOX V DD /2 - 0.15 V DD /2 + 0.15 V Input differential cross- voltage (note 4) V IX V DD /2 - 0.2 VDD /2 V DD /2 + 0.2 V High level output current I OH -6.4 mA Low level output current IOL 5.5 mA Operating free-air temperature T A 08 5 ° C Differential input signal voltage (note 3) VID Low level input voltage VIL High level input voltage VIH Notes: 1. Unused inputs must be held high or low to prevent them from floating. 2. DC input signal voltage specifies the allowable DC execution of differential input. 3. Differential inputs signal voltages specifies the differential voltage [VTR-VCP] required for switching, where VT is the true input level and VCP is the complementary input level. 4. Differential cross-point voltage is expected to track variations of VDD and is the voltage at which the differential signal must be crossing.
0674U—01/27/09 Notes: 1. Refers to transition on noninverting output in PLL bypass mode. 2. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This is due to the formula: duty cycle=t wH /tc, where the cycle (tc) decreases as the frequency goes up. 3. Switching characteristics guaranteed for application frequency range. 4. Static phase offset shifted by design. Timing Requirements TA = 0 - 85°C; Supply Voltage AVDD , VDD = 2.5 V +/- 0.2V (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN MAX UNITS Max clock frequency freq op 2.5V+0.2V @ 25oC 45 233 MHz Application Frequency Range freqApp 2.5V+0.2V @ 25oC 95 220 MHz Input clock duty cycle d tin 40 60 % CLK stabilization T STAB 15 µs Switching Characteristics (see note 3) PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS Low-to high level propagation delay time tPLH 1 CLK_IN to any output 3.5 ns High-to low level propagation delay time tPLL 1 CLK_IN to any output 3.5 ns Output enable time t EN PD# to any output 3 ns Output disable time tdis PD# to any output 3 ns Period jitter T jit (per) 100MHz to 200MHz -30 30 ps Half-period jitter t(jit_hper) 100MHz to 200MHz -75 75 ps Input clock slew rate t sl(i) 14 V / n s Output clock slew rate t sl(o) 12 V / n s Cycle to Cycle Jitter1 Tcyc-Tcyc 100MHz to 200MHz -50 50 ps Static Phase Offset t(static phase offset) 4 -50 0 50 ps Output to Output Skew T skew 40 ps
0674U—01/27/09
Ordering Information
N D E1 E /c97 SEATING PLANE SEATING PLANE AA2 e -C-- C - b c L aaa C 6.10 mm. Body, 0.50 mm. pitch TSSOP (240 mil) (0.020 mil) MIN MAX MIN MAX A -- 1.20 -- .047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 D E E1 6.00 6.20 .236 .244 e L 0.45 0.75 .018 .030 N a0 °8 °0 °8 ° VARIATIONS MIN MAX MIN MAX 48 12.40 12.60 .488 .496 1 0-0039 N D mm. D (inch) Ref erence Doc.: JEDEC Publicat ion 9 5, M O-1 53 0.50 BASIC 0.020 BASIC SEE VARIATIONS SEE VARIATIONS SEE VARIATIONS SEE VARIATIONS 8.10 BASIC 0.319 BASIC SYMBOL In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSION S Example: 95V857AGLFT Designation for tape and reel packaging Lead Free (Optional) Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type XXXX y G (LF) T
0674U—01/27/09 INDEX AREA INDEX AREA 121 2 N D E1 E α SEATING PLANE SEATING PLANE AA2 e -C-- C - b c L aaa C A- - 1 . 2 0 - - . 0 4 7 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.13 0.23 .005 .009 c 0.09 0.20 .0035 .008 D E E1 4.30 4.50 .169 .177 e L 0.45 0.75 .018 .030 N a0 ° 8 ° 0 ° 8 ° VARIATIONS MIN MAX MIN MAX 48 9.60 9.80 .378 .386 1 0-0037 N D mm. D (inch) Reference Doc.: JEDEC Publication 95, M O-1 53 0.40 BASIC 0.016 BASIC SEE VARIATIONS SEE VARIATIONS SEE VARIATIONS SEE VARIATIONS 6.40 BASIC 0.252 BASIC SYMBOL In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSION S 4.40 mm. Body, 0.40 mm. pitch TSSOP (173 mil) (16 mil) Example: 95V857ALLF T Designation for tape and reel packaging Lead Free (Optional) Package Type L = TSSOP (TVSOP) Revision Designator (will not correlate with datasheet revision) Device Type XXXX y L (LF) T
0674U—01/27/09 Example: 95V857AKLFT Designation for tape and reel packaging Lead Free (Optional) Package Type K = MLF Revision Designator (will not correlate with datasheet revision) Device Type XXXX y K (LF) T Top View IndexArea E D Sawn Singulation Anvil Singulation or A 0.08 C C Seating Plane E2 E2 L (N -1)x e (Ref.) D (Ref.) N& N Even D E N e D E (Ref.) N& N Odd e (Typ.) If N & N areEven (N -1)x e (Ref.) E ED b Thermal Base N ALL DIMENSIONS IN MILLIMETERS N SYMBOL MIN. MAX. N D A 0.80 1.00 N E A1 0 0.05 D x E BASIC A3 D2 MIN. / MAX. b 0.18 0.30 E2 MIN. / MAX. e L MIN. / MAX. 10-0053 Source Reference: MLF2™ SE THERMALLY ENHANCED, VERY THIN, FINE PITCH QUAD FLAT / NO LEAD PLASTIC PACKAGE 0.30 / 0.50
0.25 Reference
0.50 BASIC
6.00 x 6.00 2.75 / 3.05 2.75 / 3.05
0674U—01/27/09 Example: 95V857AHLF T - e -TYP b REF b REF Alpha Designations for Vertical Grid (Letters I, O, Q & S not used) Alpha Designations for Vertical Grid (Letters I, O, Q & S not used) Numeric Designations for Horizontal Grid Numeric Designations for Horizontal Grid h TYP h TYP c REF c REF A B C D TOP VIEW 3 2 14 Seating Plane Seating Plane C T 0.12 C d TYP E D D1D1D1 D1 D1 - e - - e -- e - TYP TYP D E T e HORIZ VERT TOTAL d h D1 E1 b c Min/Max Min/Max Min/Max * Source Ref.: JEDEC Publication 95, 10-0055 ALL DIMENSIONS IN MILLIMETERS REF. DIMENSIONS ----- BALL GRID ----- Max. Note: Ball grid total indicates maximum ball count for package. Lesser quantity may be used. MO-205*, MO-225** Designation for tape and reel packaging Lead Free (Optional) Package Type H = BGA Revision Designator (will not correlate with datasheet revision) Device Type XXXX y H (LF) T