8N80 WXDH | Alldatasheet

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Technical content

ROUM Semiconductor Technology CO.,LTD. Rev. 1.0 www.roum.cn Page 1 of 10 8N80

1 Description

These silicon N-channel Enhanced VDMOSFETs, is obtained by the self -aligned planar Technology which reduce the conduction loss, improve switching performance and en hance the avalanche energy. Thetransistor can be used in various power switching circuit for system miniaturization and higher efficiency.Which accords with the RoHS standard.

2 Features

  • Low Gate Charge
  • ESD Improved
  • Fast Switching
  • Low ON Resistance
  • 100% Single Pulse Avalanche Energy Test
  • 100% Δ VDS Test

3 Applicatio ns

  • Electronic Ballast
  • ATX Power
  • High Voltage H Bridge PWM Motor Drive 8A 800V N-channel Enhancement Mode Power MOSFET

4 Electrical Characteristics

4.1 Absolute Maximum Rating(Tc=25℃,unless otherwise noted)

PARAMETER SYMBOL VALUE UNIT Drian-Source Voltage VDS 800 V Gate-Drain Voltage VGS ± 30 V Drain Current(continuous) ID（T=25℃） （T=100℃） 8 A 5.4 A Drain Current(Pulsed)(Note 1) IDM 32 A Single Pulse Avalanche Energy(Note 5) EAS 350 mJ Avalanche Energy Repetitive(Note 1) EAR 55 mJ Avalanche Current(Note 1) IAR 3.3 A Peak Diode Recovery dv/dt(Note 6) dv/dt 5 V/ns Total Dissipation Ta=25℃ Ptot 2 W TC=25℃ Ptot 120 W Junction Temperature Tj 150 ℃ storage Temperature Tstg -55～150 ℃ Maximum Temperature for soldering TL 300 ℃

4.2 Thermal Characteristics

PARAMETER SYMBOL VALUE UNIT Thermal Resistance Junction to Case-sink RthJC 1.04 ℃/W Thermal Resistance Junction to Ambient RthJA 62.5 ℃/W VDSS = 800V RDS(on) （TYP)= 1.1Ω ID = 8A TO-220C 1 2 3 4 5 6 7 8 A B C D 87654321 D C B A Title N u mb er R ev isio nSize D D ate: 1 0 -A p r-2 0 1 7 Sh eet o f File: D :\\ Pr og ram Files\\p ro tel 99 se\\ 文件夹\\W X D HD raw n B y : G S D

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4.3 Electrical Characteristics(Tc=25℃,unless otherwise noted)

PARAMETER SYMBOL Test Condition VALUE UNIT MIN TYP MAX Off Characteristics Drain-source Breakdown Voltage BVDSS ID=250μA,VGS=0V 800 -- -- V Drain-to-Source Leakage Current IDSS VDS=800V,VGS=0V,TC=25℃ -- -- 25 μA VDS=640V,VGS=0V,TC=125℃ -- -- 250 μA Gate-to-Source Forward Leakage IGSSF VGS=+20V, VDS=0V -- -- 10 nA Gate-to-Source Reverse Leakage IGSSR VGS=﹣20V, VDS=0V -- -- -10 nA On Characteristics(Note 3) Gate threshold voltage VGS(th) VDS=VGS,ID=250μA 2 -- 4 V Drain-source on Resist ance RDS(on) VGS=10V,ID=4A -- 1.1 1.25 Ω Dynamic Characteristics(Note 4) Forward Transfer conductance gfs VDS=15V,ID=4A -- 8.5 -- S Input Capacitance Ciss VGS=0V,VDS=25V,f=1.0MHz -- 2100 -- pF Output Capacitance Coss -- 152 -- Reverse Transfer Cap acitance Crss -- 12 -- Switching Characteristics(note4) Turn-on Delay Time td(on) ID=8A, VDD=400V, VGS=10V, RG=4.7Ω -- 40 -- nS Turn-on Rise Time tr -- 120 -- nS Turn-off Delay Time td(off) -- 70 -- nS Turn-off Fall Time tf -- 80 -- nS Total Gate Charge Qg ID=8A,VDD=640V,VGS=10V -- 47 -- nC Gate-to-Source Charge Qgs -- 10 -- Gate-to-Drain(“Miller”)C harge Qgd -- 17 -- Drain-Source Diode Characteristics Diode Forward Voltage (Note 3) VFSD VGS=0V,IS=8A -- -- 1.5 V Diode Forward Current (Note 2) IS -- -- 8 A Reverse Recovery Time trr TJ=25℃,IF=8A, dIF/dt=100A/μS,VGS=0V -- 303 -- nS Reverse Recovery Charge Qrr -- 2230 -- nC Notes： 1: Repetitive rating, pulse width limited by maximum junction temperature. 2: Surface mounted on FR4 Board, t≤10sec. 3: Pulse width ≤ 300μs, duty cycle ≤ 2%. 4: Guaranteed by design, not subject to production. 5. L=20mH,ID=5.9A,VDD=50V,VGATE=800V,Start TJ=25℃. 6. ISD=8A,di/dt≤100A/μs,VDD≤BVDSS, Start TJ=25℃.

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5 Typical characteristics diagrams

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5 Typical characteristics diagrams(continues)

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6 Typical Test Circuit and Waveform

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A B C D 16151413121110987654321 D C B A Title N u mb er R ev isio nSize E D ate: 2 5 -May -2 0 1 7 Sh eet o f File: C :\\ U sers\\A dm in istrat or \\D esk to p \\ 模板\\w x d hq x t ( 1) . d dbD raw n B y : Same Type 50KΩ DUT VDS 200nF V 12V 200nF is DUT GS VGS 10V Q gs Q gd Q g VDS RL V DDDUT VGS RG 10V VDS 90% 10% VGS td(on) tr td(off) tf I D di/dt=100A/μA Q trr rr di/dt adj. Double Pulse D.U.T I L Current Pump V DD D 1) Gate Charge T est Circuit & Waveform 2) Resistive Switching T est Circuit & Waveforms 3) Diode Reverse Recovery Test Circuit & Waveform

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6 Typical Test Circuit and Waveform(continues)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A B C D 16151413121110987654321 D C B A Title N u mb er R ev isio nSize E D ate: 2 5 -May -2 0 1 7 Sh eet o f File: C :\\ U sers\\A dm in istrat or \\D esk to p \\ 模板\\w x d hq x t ( 1) . d dbD raw n B y : VDS I D DUT V DD L 10V RG BV SS I AS V DD I D(t) V DS(t) tp 4) Unclamped Inductive Switching Test Circuit & Waveforms

7 Product Names Rules

With 2 Digital,For Example: 60 on behalf of 600V, 06 on behalf of 60v Special Function Code E on behalf of build-in ESD Nothing on behalf of not ESD Packaging Code 220F: F 220: Nothing 251: B 252: D 262: I 263: E Rated Current Code With 1-2 Digital, For Example: 4 on behalf of 4A, 10 on behalf of 10A, 08 on behalf of 0.8A Channel Polarity Code N on behalf of N channel P on behalf of P channel F X X N E X X

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8 Product Specifications and Packaging Models

Product Model Package Type Mark Name RoHS Package Quantity 8N80 TO-220C 8N80 Pb-free Tube 1000/box F8N80 TO-220F F8N80 Pb-free Tube 1000/box I8N80 TO-262 I8N80 Pb-free Tube 1000/box E8N80 TO-263 E8N80 Pb-free Tape ＆ Reel 800/box

9 Dimensions

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9 Dimensions(continues)

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10 Attentions

 ROUM Semiconductor Technology CO.,LTD. reserves the right to change the specification without prior notice! The customer should obtain the latest version of the information before making the order and verify that the information is complete and up to date.  It is the responsibility of the purchaser for any failure or failure of any semiconductor product under certain conditions. It is the responsibility of the purchaser to comply with safety standards and to take safety measures in the system design and machine manufacturing of Roma products in order to avoid potential risk of failure. Injury or property damage.  Product promotion is endless, our company will be dedicated to provide customers with better products.

11 Appendix

Revision history: Date REV. Description Page 2017.03.31 1.0 Original