89C52

89C52 ISSI | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 50

Technical content

Integrated Silicon Solution, Inc. — 1-800-379-4774 1 MC013-1C 11/21/98 ISSI ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 1998, Integrated Silicon Solution, Inc. IS89C52 CMOS SINGLE CHIP 8-BIT MICROCONTROLLER with 8-Kbytes of FLASH NOVEMBER 1998

FEATURES

• 80C51 based architecture
• 8-Kbytes of on-chip Reprogrammable Flash Memory
• 256 x 8 RAM
• Three 16-bit Timer/Counters
• Full duplex serial channel
• Boolean processor
• Four 8-bit I/O ports, 32 I/O lines
• Memory addressing capability – 64K ROM and 64K RAM
• Program memory lock – Lock bits (3)
• Power save modes: – Idle and power-down
• Eight interrupt sources
• Most instructions execute in 0.3 µs
• CMOS and TTL compatible
• Maximum speed: 40 MHz @ Vcc = 5V
• Industrial temperature available
• Packages available: – 40-pin DIP – 44-pin PLCC – 44-pin PQFP GENERAL DESCRIPTION The ISSI IS89C52 is a high-performance microcontroller fabricated using high-density CMOS technology. The CMOS IS89C52 is functionally compatible with the industry standard 80C51 microcontrollers. The IS89C52 is designed with 8-Kbytes of Flash memory, 258 x 8 RAM; 32 programmable I/O lines; a serial I/O port for either multiprocessor communications, I/O expansion or full duplex UART; three 16-bit timer/counters; an eight-source, two-priority-level, nested interrupt structure; and an on-chip oscillator and clock circuit. The IS89C52 can be expanded using standard TTL compatible memory.

Figure 1. IS89C52 Pin Configuration: 40-pin PDIP

Figure 2. IS89C52 Pin Configuration: 44-pin PLCC

Figure 3. IS89C52 Pin Configuration: 44-pin PQFP

Figure 4. IS89C52 Block Diagram

3 LOCK BITS

32 BYTES

Table 1. Detailed Pin Description Pulse input (PROG) during Flash programming. The Port 1 output buffers can sink/source four TTL inputs. programming and verification. 12 4 0 I T2(P1.0): Timer/Counter 2 external count input. 23 4 1 I T2EX(P1.1): Timer/Counter 2 trigger input. the P2 Special Function Register.

10 11 5 I RxD (P3.0): Serial input port. 11 13 7 O TxD (P3.1): Serial output port. 12 14 8 I INT0INT0INT0INT0INT0 (P3.2): External interrupt 0. 13 15 9 I INT1INT1INT1INT1INT1 (P3.3): External interrupt 1. 14 16 10 I T0 (P3.4): Timer 0 external input. 15 17 11 I T1 (P3.5): Timer 1 external input. 16 18 12 O WRWRWRWRWR (P3.6): External data memory write strobe. 17 19 13 O RDRDRDRDRD (P3.7): External data memory read strobe. fetches from internal program memory. to the internal clock generator circuits. XTAL 2 18 20 14 O Crystal 2: Output from the inverting oscillator amplifier. GND 20 22 16 I Ground: 0V reference. Vcc 40 44 38 I Power Supply: This is the power supply voltage for operation. Table 1. Detailed Pin Description (continued)

• Memory Map and Registers
• Timer/Counters
• Serial Interface
• Interrupt System
• Other Information
• Flash Memory MEMORY MAP AND REGISTERS Memory The IS89C52 has separate address spaces for program and data memory. The program and data memory can be up to 64K bytes long. The lower 8K program memory can reside on-chip. Figure 5 shows a map of the IS89C52 program and data memory. The IS89C52 has 256 bytes of on-chip RAM, plus numbers of special function registers. The lower 128 bytes can be accessed either by direct addressing or by indirect addressing. Figure 6 shows internal data memory organization and SFR Memory Map. The lower 128 bytes of RAM can be divided into three segments as listed below and shown in Figure 7. Register Banks 0-3: locations 00H through 1FH (32 bytes). The device after reset defaults to register bank 0. To use the other register banks, the user must select them in software. Each register bank contains eight 1-byte registers R0-R7. Reset initializes the stack point to location 07H, and is incremented once to start from 08H, which is the first register of the second register bank. Bit Addressable Area: 16 bytes have been assigned for this segment 20H-2FH. Each one of the 128 bits of this segment can be directly addressed (0-7FH). Each of the 16 bytes in this segment can also be addressed as a byte. Scratch Pad Area: 30H-7FH are available to the user as data RAM. However, if the data pointer has been initialized to this area, enough bytes should be left aside to prevent SP data destruction. FFFFH: 64K 1FFFH: Program Memory (Read Only) Data Memory (Read/Write) EA = 0 External PSEN EA = 1 Internal 0000 00 FFFFH: External Internal FFH: 0000 RD WR

Figure 5. IS89C52 Program and Data Memory Structure

write accesses have no effect. sections, and detailed in Table 2. The B register is used during multiply and divide operations. Figure 6. Internal Data Memory and SFR Memory Map Figure 7. Lower 128 Bytes of Internal RAM

8 BYTES

Integrated Silicon Solution, Inc. — 1-800-379-4774 9 MC013-1C 11/21/98 ISSI SPECIAL FUNCTION REGISTERS (Continued) Stack Pointer (SP) The Stack Pointer Register is eight bits wide. It is incremented before data is stored during PUSH and CALL executions. While the stack may reside anywhere in on- chip RAM, the Stack Pointer is initialized to 07H after a reset. This causes the stack to begin at location 08H. Data Pointer (DPTR) The Data Pointer consists of a high byte (DPH) and a low byte (DPL). Its function is to hold a 16-bit address. It may be manipulated as a 16-bit register or as two independent 8-bit registers. Ports 0 To 3 P0, P1, P2, and P3 are the SFR latches of Ports 0, 1, 2, and 3, respectively. Serial Data Buffer (SBUF) The Serial Data Buffer is actually two separate registers, a transmit buffer and a receive buffer register. When data is moved to SBUF, it goes to the transmit buffer, where it is held for serial transmission. (Moving a byte to SBUF initiates the transmission.) When data is moved from SBUF, it comes from the receive buffer. Timer Registers Register pairs (TH0, TL0) and (TH1, TL1) are the 16-bit Counter registers for Timer/Counters 0 and 1, respectively. Capture Registers The register pair (RCAP2H, RCAP2L) are the Capture registers for the Timer 2 Capture Mode. In this mode, in response to a transition at the IS89C52's T2EX pin, TH2 and TL2 are copied into RCAP2H and RCAP2L. Timer 2 also has a 16-bit auto-reload mode, and RCAP2H and RCAP2L hold the reload value for this mode. Control Registers Special Function Registers IP, IE, TMOD, TCON, SCON, and PCON contain control and status bits for the interrupt system, the Timer/Counters, and the serial port. They are described in later sections of this chapter.

Table 2. Special Function Registers

1. SFRs are added to the 80C51 SFRs.

Integrated Silicon Solution, Inc. — 1-800-379-4774 11 MC013-1C 11/21/98 ISSI The detail description of each bit is as follows: PSW: Program Status Word. Bit Addressable. 7 6 54321 0 CY AC F0 RS1 RS0 OV — P Register Description: CY PSW.7 Carry flag. AC PSW.6 Auxiliary carry flag. F0 PSW.5 Flag 0 available to the user forgeneral purpose. RS1 PSW.4 Register bank selector bit 1.(1) RS0 PSW.3 Register bank selector bit 0.(1) OV PSW.2 Overflow flag. — PSW.1 Usable as a general purpose flag P PSW.0 Parity flag. Set/Clear by hardware each instruction cycle to indicate an odd/even number of “1” bits in the accumulator. Note: 1. The value presented by RS0 and RS1 selects the corre- sponding register bank. RS1 RS0 Register Bank Address 0 0 0 00H-07H 0 1 1 08H-0FH 1 0 2 10H-17H 1 1 3 18H-1FH PCON: Power Control Register. Not Bit Addressable. 7 6 54321 0 SMOD — — — GF1 GF0 PD IDL Register Description: SMOD Double baud rate bit. If Timer 1 is used to generate baud rate and SMOD=1, the baud rate is doubled when the serial port is used in modes 1, 2, or 3. — Not implemented, reserve for future use.(1) — Not implemented, reserve for future use.(1) — Not implemented, reserve for future use.(1) GF1 General purpose flag bit. GF0 General purpose flag bit. PD Power-down bit. Setting this bit activates power- down mode. IDL Idle mode bit. Setting this bit activates idle mode. If 1s are written to PD and IDL at the same time, PD takes precedence. Note: 1. User software should not write 1s to reserved bits. These bits may be used in future products to invoke new features. IE: Interrupt Enable Register. Bit Addressable. 7 6 54321 0 EA — — ES ET1 EX1 ET0 EX0 Register Description: EA IE.7 Disable all interrupts. If EA=0, no interrupt will be acknowledged. If EA=1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit. — IE.6 Not implemented, reserve for future use.(5) — IE.5 Not implemented, reserve for future use.(5) ES IE.4 Enable or disable the serial port interrupt. ET1 IE.3 Enable or disable the Timer 1 overflow interrupt. EX1 IE.2 Enable or disable External Interrupt 1. ET0 IE.1 Enable or disable the Timer 0 overflow interrupt. EX0 IE.0 Enable or disable External Interrupt 0. Note: To use any of the interrupts in the 80C51 Family, the following three steps must be taken: 1. Set the EA (enable all) bit in the IE register to 1. 2. Set the coresponding individual interrupt enable bit in the IE register to 1. 3. Begin the interrupt service routine at the corresponding Vector Address of that interrupt (see below). Interrupt Source Vector Address IE0 0003H TF0 000BH IE1 0013H TF1 001BH RI & TI 0023H 4. In addition, for external interrupts, pins INT0 and INT1 (P3.2 and P3.3) must be set to 1, and depending on whether the interrupt is to be level or transition acti- vated, bits IT0 or IT1 in the TCON register may need to be set to 0 or 1. ITX = 0 level activated (X = 0, 1) ITX = 1 transition activated User software should not write 1s to reserved bits. These bits may be used in future products to invoke new features.

12 Integrated Silicon Solution, Inc. — 1-800-379-4774 MC013-1C 11/21/98 ISSI IP: Interrupt Priority Register. Bit Addressable. 7 6 54321 0 — — — PS PT1 PX1 PT0 PX0 Register Description: — IP.7 Not implemented, reserve for future use(3) — IP.6 Not implemented, reserve for future use(3) — IP.5 Not implemented, reserve for future use(3) PS IP.4 Defines Serial Port interrupt priority level PT1 IP.3 Defines Timer 1 interrupt priority level PX1 IP.2 Defines External Interrupt 1 priority level PT0 IP.1 Defines Timer 0 interrupt priority level PX0 IP.0 Defines External Interrupt 0 priority level Notes: 1. In order to assign higher priority to an interrupt the coresponding bit in the IP register must be set to 1. While an interrupt service is in progress, it cannot be interrupted by a lower or same level interrupt. 2. Priority within level is only to resolve simultaneous requests of the same priority level. From high-to-low, interrupt sources are listed below: IE0 TF0 IE1 TF1 RI or TI TF2 or EXF2 User software should not write 1s to reserved bits. These bits may be used in future products to invoke new features. TCON: Timer/Counter Control Register. Bit Addressable 7 6 54321 0 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Register Description: TF1 TCON.7 Timer 1 overflow flag. Set by hardware when the Timer/Counter 1 overflows. Cleared by hardware as processor vectors to the interrupt service routine. TR1 TCON.6 Timer 1 run control bit. Set/Cleared by software to turn Timer/Counter 1 ON/ OFF. TF0 TCON.5 Timer 0 overflow flag. Set by hardware when the Timer/Counter 0 overflows. Cleared by hardware as processor vectors to the interrupt service routine. TR0 TCON.4 Timer 0 run control bit. Set/Cleared by software to turn Timer/Counter 0 ON/ OFF. IE1 TCON.3 External Interrupt 1 edge flag. Set by hardware when the External Interrupt edge is detected. Cleared by hardware when interrupt is processed. IT1 TCON.2 Interrupt 1 type control bit. Set/Cleared by software specify falling edge/low level triggered External Interrupt. IE0 TCON.1 External Interrupt 0 edge flag. Set by hardware when the External Interrupt edge is detected. Cleared by hardware when interrupt is processed. IT0 TCON.0 Interrupt 0 type control bit. Set/Cleared by software specify falling edge/low level triggered External Interrupt.

Integrated Silicon Solution, Inc. — 1-800-379-4774 13 MC013-1C 11/21/98 ISSI TMOD: Timer/Counter Mode Control Register. Not Bit Addressable. Timer 1 Timer 0 GATE C/ TTTTT M1 M0 GATE C/ TTTTT M1 M0 GATE When TRx (in TCON) is set and GATE=1, TIMER/ COUNTERx will run only while INTx pin is high (hardware control). When GATE=0, TIMER/ COUNTERx will run only while TRx=1 (software control). C/T Timer or Counter selector. Cleared for Timer operation (input from internal system clock). Set for Counter operation (input from Tx input pin). M1 Mode selector bit.(1) M0 Mode selector bit.(1) Note 1: M1 M0 Operating Mode 0 0 Mode 0. (13-bit Timer) 0 1 Mode 1. (16-bit Timer/Counter) 1 0 Mode 2. (8-bit auto-load Timer/Counter) 1 1 Mode 3. (Splits Timer 0 into TL0 and TH0. TL0 is an 8-bit Timer/Counter controller by the standard Timer 0 control bits. TH0 is an 8-bit Timer and is controlled by Timer 1 control bits.) 1 1 Mode 3. (Timer/Counter 1 stopped). SCON: Serial Port Control Register. Bit Addressable. 7 6 54321 0 SM0 SM1 SM2 REN TB8 RB8 TI RI Register Description: SM0 SCON.7 Serial port mode specifier.(1) SM1 SCON.6 Serial port mode specifier.(1) SM2 SCON.5 Enable the multiprocessor com- munication feature in mode 2 and 3. In mode 2 or 3, if SM2 is set to 1 then RI will not be activated if the received 9th data bit (RB8) is 0. In mode 1, if SM2=1 then RI will not be activated if valid stop bit was not received. In mode 0, SM2 should be 0. REN SCON.4 Set/Cleared by software to Enable/ Disable reception. TB8 SCON.3 The 9th bit that will be transmitted in mode 2 and 3. Set/Cleared by software. RB8 SCON.2 In modes 2 and 3, RB8 is the 9th data bit that was received. In mode 1, if SM2=0, RB8 is the stop bit that was received. In mode 0, RB8 is not used. TI SCON.1 Transmit interrupt flag. Set by hardware at the end of the eighth bit time in mode 0, or at the beginning of the stop bit in the other modes. Must be cleared by software. RI SCON.0 Receive interrupt flag. Set by hardware at the end of the eighth bit time in mode 0, or halfway through the stop bit time in the other modes (except see SM2). Must be cleared by software. Note 1: SM0 SM1 MODE Description Baud Rate 0 0 0 Shift register Fosc/12 0 1 1 8-bit UART Variable 1 0 2 9-bit UART Fosc/64 or Fosc/32 1 1 3 9-bit UART Variable

14 Integrated Silicon Solution, Inc. — 1-800-379-4774 MC013-1C 11/21/98 ISSI T2CON: Timer/Counter 2 Control Register. Bit Addressable. 7 6 5432 10 TF2 EXF2 RCLK TCLK EXEN2 TR2 C/ T2T2T2T2T2 CP/RL2RL2RL2RL2RL2 Register Description: TF2 T2CON.7 Timer 2 overflow flag set by hardware and cleared by software. TF2 cannot be set when either RCLK = 1 or TCLK = 1. EXF2 T2CON.6 Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX, and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 causes the CPU to vector to the Timer 2 interrupt routine. EXF2 must be cleared by software. RCLK T2CON.5 Receive clock flag. When set, causes the Serial Port to use Timer 2 overflow pulses for its receive clock in modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock. TLCK T2CON.4 Transmit clock flag. When set, causes the Serial Port to use Timer 2 overflow pulses for its transmit clock in modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock. EXEN2 T2CON.3 Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of negative transition on T2EX if Timer 2 is not being used to clock the Serial Port, EXEN2 = 0 causes Timer 2 to ignore events at T2EX. TR2 T2CON.2 Software START/STOP control for Timer 2. A logic 1 starts the Timer. C/T2 T2CON.1 Timer or Counter select. 0 = Internal Timer. 1 = External Event Counter (triggered by falling edge). CP/RL2 T2CON.0 Capture/Reload flag. When set, captures occur on negative transitions at T2EX if EXEN2 = 1. When cleared, auto-reloads occur either with Timer 2 overflows or negative transitions at T2EX when EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the Timer is forced to auto-reload on Timer 2 overflow. Note: 1. Timer 2 Operating Modes RCLK + TCLK CP/ RL2RL2RL2RL2RL2 TR2 MODE 0 0 1 16-Bit Auto-Reload 0 1 1 16-Bit Capture

1 X 1 Baud Rate Generator

X X 0 (Off)

either as Timers or event Counters. As a Timer, the register is incremented every machine cycle. of the oscillator frequency. cycle following the one in which the transition was detected. level is sampled at least once before it changes. are the same for both Timer/Counters, but Mode 3 is different. The four modes are described in the following sections. (TR1) does not clear the registers. bits, one for Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3). Figure 8. Timer/Counter 1 Mode 0: 13-Bit Counter

Figure 11. Timer/Counter 0 Mode 3: Two 8-Bit Counters This is a powerful addition to the other two just discussed. which are selected by RCLK, TCLK, CP/RL2, and TR2. T2CON, and EXF2, like TF2, can generate an interrupt. The Capture Mode is illustrated in Figure 12. input T2EX also triggers the 16-bit reload and sets EXF2. The auto-reload mode is illustrated in Figure 13. with the serial port (see Figure 14).

Table 5. Timer/Counter 1 Used as a Timer

3 Does Not Run 30H B0H

Table 6. Timer/Counter 1 Used as a Counter

3 Not Available — —

1. The Timer is turned ON/OFF by setting/clearing bit TR1
2. The Timer is turned ON/OFF by the 1-to-0 transition on

INT1 (P3.3) when TR1 = 1 (hardware control). set up Timers in different modes. Table 3 ORed with 60H from Table 6). in the program by setting bit TRx (in TCON) to 1. Table 3. Timer/Counter 0 Used as a Timer

3 Two 8-Bit Timers 03H 0BH

Table 4. Timer/Counter 0 Used as a Counter

3 One 8-Bit Counter 07H 0FH

1. The Timer is turned ON/OFF by setting/clearing bit TR0
2. The Timer is turned ON/OFF by the 1 to 0 transition on

INT0 (P3.2) when TR0 = 1 (hardware control).

1/64 the oscillator frequency (see Figure 17). baud rate, which is variable in Mode 3 (see Figure 18). initiated in Mode 0 by the condition RI = 0 and REN = 1. bit TR2 must be set separately to turn the Timer on. Table 7. Timer/Counter 2 Used as a Timer Table 8. Timer/Counter 2 Used as a Counter

1. Capture/Reload occurs only on Timer/Counter overflow.
2. Capture/Reload occurs on Timer/Counter overflow and

Timer 2 is used in the baud rate generating mode.

Integrated Silicon Solution, Inc. — 1-800-379-4774 21 MC013-1C 11/21/98 ISSI Using the Timer 1 to Generate Baud Rates When Timer 1 is the baud rate generator, the baud rates in Modes 1 and 3 are determined by the Timer 1 overflow rate and the value of SMOD according to the following equation. Mode 1, 3 2 SMOD X (Timer 1 Overflow Rate)Baud Rate = 32 The Timer 1 interrupt should be disabled in this application. The Timer itself can be configured for either timer or counter operation in any of its three running modes. In the most typical applications, it is configured for timer operation in auto-reload mode (high nibble of TMOD = 0010B). In this case, the baud rate is given by the following formula. Mode 1,3 2 SMOD X Oscillator Frequency Baud Rate = 32 12x [256 – (TH1)] Programmers can achieve very low baud rates with Timer 1 by leaving the Timer 1 interrupt enabled, configuring the Timer to run as a 16-bit timer (high nibble of TMOD = 0001B), and using the Timer 1 interrupt to do a 16-bit software reload. Table 9 lists commonly used baud rates and how they can be obtained from Timer 1. Multiprocessor Communications Modes 2 and 3 have a special provision for multiprocessor communications. In these modes, nine data bits are received, followed by a stop bit. The ninth bit goes into RB8; then comes a stop bit. The port can be programmed such that when the stop bit is received, the serial port interrupt is activated only if RB8 = 1. This feature is enabled by setting bit SM2 in SCON. The following example shows how to use the serial interrupt for multiprocessor communications. When the master processor must transmit a block of data to one of several slaves, it first sends out an address byte that identifies the target slave. An address byte differs from a data byte in that the ninth bit is 1 in an address byte and 0 in a data byte. With SM2 = 1, no slave is interrupted by a data byte. An address byte, however, interrupts all slaves, so that each slave can examine the received byte and see if it is being addressed. The addressed slave clears its SM2 bit and prepares to receive the data bytes that follows. The slaves that are not addressed set their SM2 bits and ignore the data bytes. SM2 has no effect in Mode 0 but can be used to check the validity of the stop bit in Mode 1. In a Mode 1 reception, if SM2 = 1, the receive interrupt is not activated unless a valid stop bit is received. Baud Rates The baud rate in Mode 0 is fixed as shown in the following equation. Mode 0 Baud Rate = Oscillator Frequency The baud rate in Mode 2 depends on the value of the SMOD bit in Special Function Register PCON. If SMOD = 0 (the value on reset), the baud rate is 1/64 of the oscillator frequency. If SMOD = 1, the baud rate is 1/32 of the oscillator frequency, as shown in the following equation. Mode 2 Baud Rate = 2 SMOD x (Oscillator Frequency) In the IS89C52, these baud rates can be determined by Timer 1, Timer 2, or both (one for transmit and the other for receive).

at the time the final shift pulse is generated. have a variable baud rate generated from Timer 1. 1 only in the ninth bit of the transmit shift register. divide-by-16 counter, not to the "write to SBUF" signal. left of TB8, and all positions to the left of that contain 0s. eleventh divide-by-16 rollover after "write to SBUF". and 1FFH is written to the input shift register. of the rest of the frame proceeds. As data bits come in from the right, 1s shift out to the left. looking for a 1-to-0 transition at the RXD input. Table 10. Serial Port Setup

3 D0H

2 B0H

3 F0H

Figure 15. Serial Port Mode 0

Figure 16. Serial Port Mode 1

Figure 17. Serial Port Mode 2

Figure 18. Serial Port Mode 3

interrupts, two timer interrupts, and a serial port interrupt. These are shown in Figure 19. than the on-chip hardware) controls the request flag. Timer/Counter registers (except for Timer 0 in Mode 3). the interrupt, and the bit must be cleared in software. must be cleared in software. interrupts or set to turn on interrupts (see SFR IE). Figure 19. Interrupt System

Integrated Silicon Solution, Inc. — 1-800-379-4774 31 MC013-1C 11/21/98 ISSI Thus, the processor acknowledges an interrupt request by executing a hardware-generated LCALL to the appropriate servicing routine. In some cases it also clears the flag that generated the interrupt, and in other cases it does not. It never clears the Serial Port or Timer 2 flags. This must be done in the user's software. The processor clears an external interrupt flag (IE0 or IE1) only if it was transition- activated. The hardware-generated LCALL pushes the contents of the Program Counter onto the stack (but it does not save the PSW) and reloads the PC with an address that depends on the source of the interrupt being serviced, as shown in the following table. Interrupt Interrupt Cleared by Vector Source Request Bits Hardware Address INT0 IE0 No (level) 0003H Yes (trans.) Timer 0 TF0 Yes 000BH INT1 IE1 No (level) 0013H Yes (trans.) Timer 1 TF1 Yes 001BH Serial Port RI, TI No 0023H Timer 2 TF2, EXF2 No 002BH System RST 0000H Reset Execution proceeds from that location until the RETI instruction is encountered. The RETI instruction informs the processor that this interrupt routine is no longer in progress, then pops the top two bytes from the stack and reloads the Program Counter. Execution of the interrupted program continues from where it left off. Note that a simple RET instruction would also have returned execution to the interrupted program, but it would have left the interrupt control system thinking an interrupt was still in progress. SFR Register and Interrupt Flag Bit Position External 0 IE0 TCON.1 External 1 IE1 TCON.3 Timer 1 TF1 TCON.7 Timer 0 TF0 TCON.5 Serial Port TI SCON.1 Serial Port RI SCON.0 Timer 2 TF2 T2CON.7 Timer 2 EXF2 T2CON.6 When an interrupt is accepted, the following action occurs: 1. The current instruction completes operation. 2. The PC is saved on the stack. 3. The current interrupt status is saved internally. 4. Interrupts are blocked at the level of the interrupts. 5. The PC is loaded with the vector address of the ISR (interrupts service routine). 6. The ISR executes. The ISR executes and takes action in response to the interrupt. The ISR finishes with RETI (return from interrupt) instruction. This retrieves the old value of the PC from the stack and restores the old interrupt status. Execution of the main program continues where it left off. External Interrupts The external sources can be programmed to be level- activated or transition-activated by setting or clearing bit IT1 or IT0 in Register TCON. If ITx= 0, external interrupt x is triggered by a detected low at the INTx pin. If ITx = 1, external interrupt x is edge-triggered. In this mode if successive samples of the INTx pin show a high in one cycle and a low in the next cycle, interrupt request flag IEx in TCON is set. Flag bit IEx then requests the interrupt. Since the external interrupt pins are sampled once each machine cycle, an input high or low should hold for at least 12 oscillator periods to ensure sampling. If the external interrupt is transition-activated, the external source has to hold the request pin high for at least one machine cycle, and then hold it low for at least one machine cycle to ensure that the transition is seen so that interrupt request flag IEx will be set. IEx will be automatically cleared by the CPU when the service routine is called. If the external interrupt is level-activated, the external source has to hold the request active until the requested interrupt is actually generated. Then the external source must deactivate the request before the interrupt service routine is completed, or else another interrupt will be generated.

32 Integrated Silicon Solution, Inc. — 1-800-379-4774 MC013-1C 11/21/98 ISSI Response Time The INT0 and INT1 levels are inverted and latched into the interrupt flags IE0 and IE1 at S5P2 of every machine cycle. Similarly, the Timer 2 flag EXF2 and the Serial Port flags RI and TI are set at S5P2. The values are not actually polled by the circuitry until the next machine cycle. The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the timers overflow. The values are then polled by the circuitry in the next cycle. However, the Timer 2 flag TF2 is set at S2P2 and is polled in the same cycle in which the timer overflows. If a request is active and conditions are right for it to be acknowledged, a hardware subroutine call to the requested service routine will be the next instruction executed. The call itself takes two cycles. Thus, a minimum of three complete machine cycles elapsed between activation of an external interrupt request and the beginning of execution of the first instruction of the service routine. Figure 19 shows response timings. A longer response time results if the request is blocked by one of the three previously listed conditions. If an interrupt of equal or higher priority level is already in progress, the additional wait time depends on the nature of the other interrupt's service routine. If the instruction in progress is not in its final cycle, the additional wait time cannot be more than three cycles, since the longest instructions (MUL and DIV) are only four cycles long. If the instruction in progress is RETI or an access to IE or IP, the additional wait time cannot be more than five cycles (a maximum of one more cycle to complete the instruction in progress, plus four cycles to complete the next instruction if the instruction is MUL or DIV). Thus, in a single-interrupt system, the response time is always more than three cycles and less than nine cycles. Single-Step Operation The IS89C52 interrupt structure allows single-step execution with very little software overhead. As previously noted, an interrupt request will not be serviced while an interrupt of equal priority level is still in progress, nor will it be serviced after RETI until at least one other instruction has been executed. Thus, once an interrupt routine has been entered, it cannot be re-entered until at least one instruction of the interrupted program is executed. One way to use this feature for single-step operation is to program one of the external interrupts (for example, INT0) to be level-activated. The service routine for the interrupt will terminate with the following code: JNB P3.2,$ ;Wait Here Till INT0 Goes High JB P3.2,$ ;Now Wait Here Till it Goes Low RETI ;Go Back and Execute One Instruction If the INT0 pin, which is also the P3.2 pin, is held normally low, the CPU will go right into the External Interrupt 0 routine and stay there until INT0 is pulsed (from low-to- high-to-low). Then it will execute RETI, go back to the task program, execute one instruction, and immediately re- enter the External Interrupt 0 routine to await the next pulsing of P3.2. One step of the task program is executed each time P3.2 is pulsed.

Table 11. Reset Values of the SFR's internal reset, with the timing shown in Figure 21. the RAM content is indeterminate. Figure 21. Reset Timing

Figure 26. Oscillator Connections for High Speed (> 24 MHz) When the frequency is higher than 24 MHz, please refer to Table 11 for recommended values of C1, C2, and R. Table 13. Recommended Value for C1, C2, R

3.5 MHz - 24 MHz 30 MHz - 40 MHz

The detailed lock-bits features are listed in Table 14. Table 14. Program Lock Bits 1 UUU No Program Lock Features enabled. latched on Reset and further programming of the Flash is disabled. 3P P U Same as 2, also verify is disabled. 4 PPP Same as 3, also external execution is disabled. memory array must be erased electrically. Table 15 and Figures 27 and 28. Table 15. Flash Programming Mode

40 Integrated Silicon Solution, Inc. — 1-800-379-4774 MC013-1C 11/21/98 ISSI Programming Algorithm Before programming the IS89C52, the control signals, the address, data should be setup according to the programming mode table and programming interface. To program the IS89C52, the following sequence should be followed: 1. Insert the desired memory location on the address bus. 2. Insert the appropriate data byte on the data bus. 3. Active the correct combination of control signals. 4. Raise EA / V PP to 12V. 5. Pulse ALE / PROG once to program a byte in the Flash array, Encryption array or the lock bits. 6. Set EA / VPP to 5 V and verify data. If the data is correct then execute step 7, otherwise execute steps 1-6. 7. Repeat steps 1 through 6, changing the address and data for the entire array or until the end of the object file is reached. Program Verify If lock bits LB1, LB2 and LB3 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of lock bits is achieved by observing that their features are enabled. To verify the data after all addresses are programmed completely, power down the IS89C52 and then reapply power. The programmed data can then be verified by applying the verify signals to the device. Erasing Chip All Flash memory cells must be programmed to '00' (include encryption array and lock bits) before the chip is erased. The entire Flash array is erased electrically by using the proper combination of control signals and by holding ALE/ PROG low for t GLGHE duration (See Table 16. Flash Programming and Verification Characteristics for tGLGHE value.) After the chip is erased, the code array and lock bits are written with all “1”s. If any Flash memory cell is not '1' (including lock bits), repeat the chip erase again. The chip erase operation must be executed successfully before the code memory can be re-programmed. Reading the Signature Bytes The signature bytes are read by the same procedure as a normal verification of locations 030H, 031H and 032H, except that P3.6 and P3.7 need to be pulled to a logic low. The values returned are: Signature Location Value (030H) D5H indicates manufactured by ISSI (031H) 51H indicates IS89C52 (032H) FFH indicates programming voltage is 12V

Table 16. Flash Programming and Verification Characteristics(1)

1. COND ENABLE and COND DISABLE are generated and depend on the control signals on pins P2.6,

as programming condition, erasing condition, and verify condition.

Figure 30. Flash Memory Erase Timing Waveform

1. The power off and power on waveform can be used in programming or erasing.

Figure 29. Flash Memory Programming and Verification Timing Waveform

1. One pulse for the main code array, 25 pulses for the encryption array and lock bits.
2. This verify condition is using at main code verification.
3. Power off waveform not shown.

25 PULSE (1)

Integrated Silicon Solution, Inc. — 1-800-379-4774 43 MC013-1C 11/21/98 ISSI OPERATING RANGE (1) Range Ambient Temperature V CC Oscillator Frequency Commercial 0 °C to +70°C 5V ± 10% 3.5 to 40 MHz Industrial –40 °C to +85°C 5V ± 10% 3.5 to 40 MHz Note: 1. Operating ranges define those limits between which the functionality of the device is guaranteed. ABSOLUTE MAXIMUM RATINGS (1) Symbol Parameter Value Unit VTERM Terminal Voltage with Respect to GND(2) –2.0 to +7.0 V TBIAS Temperature Under Bias(3) –40 to +85 °C TSTG Storage Temperature –65 to +125 °C PT Power Dissipation 1.5 W Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to – 2.0V for periods less than 20 ns. Maximum DC voltage on output pins is Vcc + 0.5V which may overshoot to Vcc + 2.0V for periods less than 20 ns. 3. Operating temperature is for commercial products only defined by this specification.

44 Integrated Silicon Solution, Inc. — 1-800-379-4774 MC013-1C 11/21/98 ISSI DC CHARACTERISTICS (Over Operating Range; GND = 0V) Symbol Parameter Test conditions Min Max Unit VIL Input low voltage (All except EA) –0.5 0.2Vcc – 0.1 V VIL1 Input low voltage ( EA) –0.5 0.2Vcc – 0.3 V VIH Input high voltage 0.2Vcc + 0.9 Vcc + 0.5 V (All except XTAL 1, RST) VIH1 Input high voltage (XTAL 1) 0.7Vcc Vcc + 0.5 V VSCH + RST positive schmitt-trigger 0.7Vcc Vcc + 0.5 V threshold voltage VSCH – RST negative schmitt-trigger 0 0.2Vcc V threshold voltage VOL (1) Output low voltage Iol = 100 µA — 0.3 V (Ports 1, 2, 3) I OL = 1.6 mA — 0.45 V IOL = 3.5 mA — 1.0 V VOL 1(1) Output low voltage I OL = 200 µA — 0.3 V (Port 0, ALE, PSEN)I OL = 3.2 mA — 0.45 V IOL = 7.0 mA — 1.0 V VOH Output high voltage I OH = –10 µA 0.9Vcc — V (Ports 1, 2, 3, ALE, PSEN) Vcc = 4.5V-5.5V IOL = –25 µA 0.75Vcc — V IOL = –60 µA 2.4 — V VOH 1 Output high voltage I OH = –80 µA 0.9Vcc — V (Port 0, ALE, PSEN) Vcc = 4.5V-5.5V IOH = –300 µA 0.75Vcc — V IOH = –800 µA 2.4 — V IIL Logical 0 input current (Ports 1, 2, 3) VIN = 0.45V — –80 µA ILI Input leakage current (Port 0) 0.45V < VIN < Vcc –10 +10 µA ITL Logical 1-to-0 transition current VIN = 2.0V — –650 µA (Ports 1, 2, 3) R RST RST pulldown resister 50 300 K Ω Note: 1. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 10 mA Maximum IOL per 8-bit port Port 0: 26 mA Ports 1, 2, 3: 15 mA Maximum total IOL for all output pins: 71 mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink greater than the listed test conditions.

16 MHz — 26 mA

20 MHz — 32 mA

24 MHz — 38 mA

32 MHz — 50 mA

40 MHz — 62 mA

16 MHz — 6 mA

24 MHz — 9 mA

32 MHz — 12 mA

40 MHz — 15 mA

1. See Figures 31, 32, 33, and 34 for Icc test conditiions.

Figure 31. Active Mode Figure 32. Idle Mode Figure 33. Power-down Mode

Figure 34. Icc Test Conditions

1. Clock signal waveform for Icc tests in active and idle mode (tCLCH = tCHCL = 5 ns)

24 MHz 40 MHz Variable Oscillator

Integrated Silicon Solution, Inc. — 1-800-379-4774 47 MC013-1C 11/21/98 ISSI SERIAL PORT TIMING: SHIFT REGISTER MODE Clock Clock (3.5-40 MHz) Symbol Parameter Min Max Min Max Min Max Unit tXLXL Serial port clock cycle time 490 510 290 310 12t CLCL –10 12t CLCL +10 ns tQVXH Output data setup to 406 — 240 — 10t CLCL –10 — ns clock rising edge tXHQX Output data hold after 73 — 40 — 2t CLCL –10 — ns clock rising edge tXHDX Input data hold after 0 — 0 — 0 — ns clock rising edge tXHDV Clock rising edge to — 417 — 250 — 10t CLCL ns input data valid EXTERNAL CLOCK DRIVE CHARACTERISTICS Symbol Parameter Min Max Unit 1/tCLCL Oscillator Frequency 3.5 40 MHz tCHCX High time 10 — ns tCLCX Low time 10 — ns tCLCH Rise time — 10 ns tCHCL Fall time — 10 ns

50 Integrated Silicon Solution, Inc. — 1-800-379-4774 MC013-1C 11/21/98 ISSI

ORDERING INFORMATION

Commercial Range: 0°C to +70°C Speed Order Part Number Package

12 MHz IS89C52-12PL PLCC – Plastic Leaded Chip Carrier

IS89C52-12W 600-mil Plastic DIP IS89C52-12PQ PQFP

24 MHz IS89C52-24PL PLCC – Plastic Leaded Chip Carrier

IS89C52-24W 600-mil Plastic DIP IS89C52-24PQ PQFP

40 MHz IS89C52-40PL PLCC – Plastic Leaded Chip Carrier

IS89C52-40W 600-mil Plastic DIP IS89C52-40PQ PQFP Integrated Silicon Solution, Inc.

2231 Lawson Lane

Santa Clara, CA 95054 Fax: (408) 588-0806 Toll Free: 1-800-379-4774 http://www.issi.com Industrial Range: –40°C to +85°C Speed Order Part Number Package

12 MHz IS89C52-12PLI PLCC – Plastic Leaded Chip Carrier

IS89C52-12WI 600-mil Plastic DIP IS89C52-12PQI PQFP

24 MHz IS89C52-24PLI PLCC – Plastic Leaded Chip Carrier

IS89C52-24WI 600-mil Plastic DIP IS89C52-24PQI PQFP

40 MHz IS89C52-40PLI PLCC – Plastic Leaded Chip Carrier

IS89C52-40WI 600-mil Plastic DIP IS89C52-40PQI PQFP ISSI