ICS873033 ICST | Alldatasheet

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www.icst.com/products/hiperclocks.html REV. A OCTOBER 19, 2005 Integrated Circuit Systems, Inc. ICS873033 HIGH SPEED, ÷4 DIFFERENTIAL-TO- 3.3V, 5V LVPECL/ECL CLOCK GENERATOR GENERAL DESCRIPTION The ICS873033 is a high speed, high perfor- mance Differential-to-3.3V, 5V LVPECL/ECL Clock Generator and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS873033 is characterized to operate from either a 3.3V or a 5V power supply.

FEATURES

  • One differential 3.3V, 5V LVPECL / ECL output
  • One differential PCLK, nPCLK input pair
  • PCLK, nPCLK pair can accept the following differential input levels: LVPECL, LVDS, CML, SSTL
  • Input frequency: 3.2GHz (maximum)
  • Translates any single ended input signal to 3.3V LVPECL levels with resistor bias on nPCLK input
  • Additive phase jitter, RMS: 0.20ps (typical)
  • LVPECL mode operating voltage supply range: VCC = 3.0V to 5.5V, VEE = 0V
  • ECL mode operating voltage supply range: VCC = 0V, VEE = -5.5V to -3.0V
  • -40°C to 85°C ambient operating temperature
  • Available in both standard and lead-free RoHS-compliant packages BLOCK DIAGRAM PIN ASSIGNMENT ICS873033 8-Lead SOIC 3.90mm x 4.90mm x 1.37mm package body M Package Top View RESET PCLK nPCLK VBB HiPerClockS™ ICS Vcc Q nQ VEE Q nQ RESET PCLK nPCLK VBB ICS873033 8-Lead TSSOP, 118 mil 3mm x 3mm x 0.95mm package body G Package Top View The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.

TABLE 1. PIN DESCRIPTIONS TABLE 2. PIN CHARACTERISTICS TABLE 3. TRUTH TABLE FIGURE 1. TIMING DIAGRAM

www.icst.com/products/hiperclocks.html REV. A OCTOBER 19, 2005 Integrated Circuit Systems, Inc. ICS873033 HIGH SPEED, ÷4 DIFFERENTIAL-TO- 3.3V, 5V LVPECL/ECL CLOCK GENERATOR TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.0V TO 5.5V; VEE = 0V ABSOLUTE MAXIMUM RATINGS TABLE 4B. LVPECL DC CHARACTERISTICS, VCC = 3.3V; VEE = 0V NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifi- cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Character- istics is not implied. Exposure to absolute maxi- mum rating conditions for extended periods may affect product reliability. Supply Voltage, VCC 6V (LVPECL mode, VEE = 0) Negative Supply Voltage, VEE -6V (ECL mode, VCC = 0) Inputs, VI (LVPECL mode) -0.5V to VCC + 0.5V Inputs, VI (ECL mode) 0.5V to VEE - 0.5V Outputs, IO Continuous Current 50mA Surge Current 100mA VBB Sink/Source, IBB ± 0.5mA Operating Temperature Range, TA -40°C to +85°C Storage Temperature, TSTG -65°C to 150°C Package Thermal Impedance, θJA 112.7°C/W (0 lfpm) (Junction-to-Ambient) for 8 Lead SOIC Package Thermal Impedance, θJA 101.7°C/W (0 m/s) (Junction-to-Ambient) for 8 Lead TSSOP l o b m y S r e t e m a r a P s n o iti d n o C t s e T m u m i n i M l a c i p y T m u m i x a M s ti n U V C C e g a tlo V ylp p u S e vitis o P V I E E t n e rr u C ylp p u S r e w o P A m l o b m y S r e t e m a r a P C C C s ti n U n i M p y T x a M n i M p y T x a M n i M p y T x a M V H O E T O N e g a tlo V h gi H t u p t u O V V L O E T O N e g a tlo V w o L t u p t u O V V H I e g a tlo V h gi H t u p n I d e d n E elg ni S V V L I e g a tlo V w o L t u p n I d e d n E elg ni S V V B B e c n e r e f e R e g a tlo V t u p t u O V V P P e g a tlo V t u p n I k a e P o k a e P mV V R M C e g a tlo V h gi H t u p n I E T O N e g n a R e d o M n o m m o C V I H I t u p n I t n e rr u C h gi H K L C P n K L C P A µ I L I t u p n I t n e rr u C w o L K L C P n K L C P A µ V h ti w y r a v s r e t e m a r a p t u p t u o d n a t u p n I C C V E E V o t V y r a v n a c h ti w d e t a ni m r e t st u p t u O E T O N Ω V o t C C V V s a d e nif e d si e g a tlo v e d o m n o m m o C E T O N H I . V si K L C P n K L C P r o f e g a tlo v t u p ni m u m ix a m e h t n oit a cilp p a d e d n e elg nis r o F E T O N C C V

www.icst.com/products/hiperclocks.html REV. A OCTOBER 19, 2005 Integrated Circuit Systems, Inc. ICS873033 HIGH SPEED, ÷4 DIFFERENTIAL-TO- 3.3V, 5V LVPECL/ECL CLOCK GENERATOR TABLE 4D. ECL DC CHARACTERISTICS, VCC = 0V; VEE = -5.5V TO -3.0V TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = 5V; VEE = 0V l o b m y S r e t e m a r a P C C C s ti n U n i M p y T x a M n i M p y T x a M n i M p y T x a M V H O E T O N e g a tlo V h gi H t u p t u O 1.1 0.1 9.0 0.1 0.1 9.0 0.1 9.0 9.0 V V L O E T O N e g a tlo V w o L t u p t u O 8.1 7.1 6.1 8.1 7.1 6.1 8.1 7.1 6.1 V V H I e g a tlo V h gi H t u p n I d e d n E elg ni S 2.1 9.0 2.1 9.0 2.1 9.0 V V L I e g a tlo V w o L t u p n I d e d n E elg ni S 8.1 5.1 8.1 5.1 8.1 5.1 V V B B e c n e r e f e R e g a tlo V t u p t u O 4.1 3.1 4.1 3.1 4.1 3.1 V V P P e g a tlo V t u p n I k a e P o k a e P mV V R M C e g a tlo V h gi H t u p n I E T O N e g n a R e d o M n o m m o C V E E V 2.1 V E E V 2.1 V E E V 2.1 V I H I t u p n I t n e rr u C h gi H K L C P n K L C P A µ I L I t u p n I t n e rr u C w o L K L C P n K L C P A µ V h ti w y r a v s r e t e m a r a p t u p t u o d n a t u p n I C C . h ti w d e t a ni m r e t st u p t u O E T O N Ω V o t C C V V s a d e nif e d si e g a tlo v e d o m n o m m o C E T O N H I . V si K L C P n K L C P r o f e g a tlo v t u p ni m u m ix a m e h t n oit a cilp p a d e d n e elg nis r o F E T O N C C V l o b m y S r e t e m a r a P C C C s ti n U n i M p y T x a M n i M p y T x a M n i M p y T x a M V H O E T O N e g a tlo V h gi H t u p t u O V V L O E T O N e g a tlo V w o L t u p t u O V V H I e g a tlo V h gi H t u p n I d e d n E elg ni S V V L I e g a tlo V w o L t u p n I d e d n E elg ni S V V B B e c n e r e f e R e g a tlo V t u p t u O V V P P e g a tlo V t u p n I k a e P o k a e P mV V R M C e g a tlo V h gi H t u p n I E T O N e g n a R e d o M n o m m o C V I H I t u p n I t n e rr u C h gi H K L C P n K L C P A µ I L I t u p n I t n e rr u C w o L K L C P n K L C P A µ V h ti w y r a v s r e t e m a r a p t u p t u o d n a t u p n I C C V E E V o t V y r a v n a c h ti w d e t a ni m r e t st u p t u O E T O N Ω V o t C C V V s a d e nif e d si e g a tlo v e d o m n o m m o C E T O N H I . V si K L C P n K L C P r o f e g a tlo v t u p ni m u m ix a m e h t n oit a cilp p a d e d n e elg nis r o F E T O N C C V

www.icst.com/products/hiperclocks.html REV. A OCTOBER 19, 2005 Integrated Circuit Systems, Inc. ICS873033 HIGH SPEED, ÷4 DIFFERENTIAL-TO- 3.3V, 5V LVPECL/ECL CLOCK GENERATOR ADDITIVE PHASE JITTER Additive Phase Jitter @ 155.52MHz (12kHz to 20MHz) = 0.20ps typical -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 10k 100k 10M The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a As with most timing specifications, phase noise measure- ments have issues. The primary issue relates to the limita- tions of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated ratio of the power in the 1Hz band to the power in the funda- mental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the fre- quency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment. OFFSET FROM CARRIER FREQUENCY (HZ) SSB PHASE NOISE dBc/HZ

www.icst.com/products/hiperclocks.html REV. A OCTOBER 19, 2005 Integrated Circuit Systems, Inc. ICS873033 HIGH SPEED, ÷4 DIFFERENTIAL-TO- 3.3V, 5V LVPECL/ECL CLOCK GENERATOR PARAMETER MEASUREMENT INFORMATION OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL PROPAGATION DELAY OUTPUT RISE/FALL TIME VCMR Cross Points VPP VEE nPCLK VCC PCLK SCOPE Qx nQx LVPECL -3.5V to -1.0V Clock Outputs 20% 80% 80% 20% tR tF VSWING tPD nPCLK Q nQ PCLK VCC VEE RMS PHASE JITTER Phase Noise Mask Offset Frequency Phase Noise Plot RMS Jitter = Area Under the Masked Phase Noise Plot Noise Power

www.icst.com/products/hiperclocks.html REV. A OCTOBER 19, 2005 Integrated Circuit Systems, Inc. ICS873033 HIGH SPEED, ÷4 DIFFERENTIAL-TO- 3.3V, 5V LVPECL/ECL CLOCK GENERATOR POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS873033. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS873033 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 5.5V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. Power (core)MAX = VCC_MAX * IEE_MAX = 5.5V * 30mA = 165mW Power (outputs)MAX = 30.94mW/Loaded Output pair Total Power_MAX (5.5V, with all outputs switching) = 165mW + 30.94mW = 195.94mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3°C/W per Table 6A below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). θθθθθJA by Velocity (Linear Feet per Minute) 200 500 Single-Layer PCB, JEDEC Standard Test Boards 153.3°C/W 128.5°C/W 115.5°C/W Multi-Layer PCB, JEDEC Standard Test Boards 112.7°C/W 103.3°C/W 97.1°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TABLE 6A. THERMAL RESISTANCE θθθθθJA FOR 8-PIN SOIC, FORCED CONVECTION TABLE 6B. THERMAL RESISTANCE θθθθθJA FOR 8-PIN TSSOP, FORCED CONVECTION θθθθθJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 101.7°C/W 90.5°C/W 89.8°C/W

  1. Calculations and Equations.

The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 7. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. FIGURE 7. LVPECL DRIVER CIRCUIT AND TERMINATION

www.icst.com/products/hiperclocks.html REV. A OCTOBER 19, 2005 Integrated Circuit Systems, Inc. ICS873033 HIGH SPEED, ÷4 DIFFERENTIAL-TO- 3.3V, 5V LVPECL/ECL CLOCK GENERATOR RELIABILITY INFORMATION TRANSISTOR COUNT The transistor count for ICS873033 is: 165 Pin compatible with MC100EP33 TABLE 7A. θJAVS. AIR FLOW TABLE FOR 8 LEAD SOIC θθθθθJA by Velocity (Linear Feet per Minute) 200 500 Single-Layer PCB, JEDEC Standard Test Boards 153.3°C/W 128.5°C/W 115.5°C/W Multi-Layer PCB, JEDEC Standard Test Boards 112.7°C/W 103.3°C/W 97.1°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TABLE 7B. θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP θθθθθJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 101.7°C/W 90.5°C/W 89.8°C/W

www.icst.com/products/hiperclocks.html REV. A OCTOBER 19, 2005 Integrated Circuit Systems, Inc. ICS873033 HIGH SPEED, ÷4 DIFFERENTIAL-TO- 3.3V, 5V LVPECL/ECL CLOCK GENERATOR PACKAGE OUTLINE - M SUFFIX FOR 8 LEAD SOIC TABLE 8A. PACKAGE DIMENSIONS Reference Document: JEDEC Publication 95, MS-012 L O B M Y S s r e t e m illi M N U M I N I M M U M I X A M N A A B C D E e C I S A B H h L α

www.icst.com/products/hiperclocks.html REV. A OCTOBER 19, 2005 Integrated Circuit Systems, Inc. ICS873033 HIGH SPEED, ÷4 DIFFERENTIAL-TO- 3.3V, 5V LVPECL/ECL CLOCK GENERATOR PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP TABLE 8B. PACKAGE DIMENSIONS Reference Document: JEDEC Publication 95, MO-187 L O B M Y S s r e t e m illi M m u m i n i M m u m i x a M N A A A b c D C I S A B E C I S A B E C I S A B e C I S A B e C I S A B L α a a a

TABLE 9. ORDERING INFORMATION for use in life support devices or critical medical instruments. The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.