855844 TRIQUINT | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 5

Technical content

Features

  • For GSM IF applications
  • Usable bandwidth of 160 kHz
  • Low loss
  • High attenuation
  • Balanced operation
  • Ceramic Surface Mount Package (SMP)
  • Small size Package Pin Configuration Surface Mount 5.00 x 5.00 x 1.32 mm Bottom View 765 321 Pin No. Description

1 Input

2 Input return

5 Output

6 Output return

3,4,7,8 Case ground 1.32 NOM. 1.52 MAX. 0.66 1.27 1.27 0.642.08 5.00 5.00 Dimensions shown are nominal in millimeters All tolerances are ±0.15mm except overall length and width +0.15/-0.10mm Body: Al2O3 ceramic Lid: Kovar, Ni plated Terminations: Au plating 0.5 - 1.0µm, over a 2 - 6µm Ni plating

225 MHz SAW Filter

Subject to change or obsolescence without notice Rev A 01-Nov-2001 Page 2 of 5 Electrical Specifications (1) Operating Temperature Range: (2) -20 to +70 oC Parameter (3) Minimum Typical Maximum Unit Center Frequency, fo - 225 - MHz Insertion Loss at 225 MHz Excluding losses due to matching Including losses in matching test circuit shown below 2.3 3.5 3.8 5.0 dB dB Amplitude Variation 224.9200 - 225.0800 MHz 224.9325 - 225.0675 MHz 0.5 0.3 3.2 2.2 dB p-p dB p-p Rejection (4) 223 - 224.4 MHz 224.4 - 224.6 MHz 224.6 - 224.8 MHz 225.2 - 225.4 MHz 225.4 - 225.6 MHz 225.6 - 227.0 MHz MHz MHz MHz MHz MHz MHz Out of Band Rejection 10 - 215 MHz 235 - 750 MHz dB dB Group Delay Ripple 224.9200 - 225.0800 MHz 224.9325 - 225.0675 MHz 224.9500 - 225.0500 MHz 0.9 0.6 0.2 1.8 1.6 1.3 µsec µsec µsec Optimal Source Impedance: (5) - 704Ω||332nH - Ω Optimal Load Impedance: (5) - 739Ω||359nH - Ω Notes: 1. All specifications are based on the test circuit shown below 2. In production, devices will be tested at room temperature to a guardbanded specification to ensure electrical compliance over temperature 3. Electrical margin has been built into the design to account for the variations due to manufacturing tolerances 4. Relative to insertion loss at 225 MHz 5. This is the complex conjugate of the unmatched filter’s impedance resulting in maximum power transfer Test Circuit: 50Ω Balanced 3,4,7,8 50Ω 7pF 82nH 7pF 7pF 7pF 82nH 50Ω

Subject to change or obsolescence without notice Rev A 01-Nov-2001 Page 3 of 5 Typical Performance (at +25oC)

Subject to change or obsolescence without notice Rev A 01-Nov-2001 Page 4 of 5 Matching Schematics Actual matching values may vary due to PCB layout and parasitics 50Ω Balanced 3,4,7,8 50Ω 7pF 82nH 7pF 7pF 7pF 82nH 50Ω Marking PCB Footprint Date code C JJJYM ID dot logo Sawtek code Marking 1.47 5.20 2.28 .84 1.47 .84 .43 .71 The date code consists of: JJJ = Julian day, Y = last digit of year, M = manufacturing site code This footprint represents a recommendation only Dimensions shown are nominal in millimeters Tape and Reel 12.0 Section A-A A A 0.3 1.8 5.25 5.25 Ø1.5 Ø1.58.0 4.0 2.0 5.5 1.75 12.8 2.7 Ø13.0 Ø20.2 Ø330 logo Sawtek ID dot 2.0 Ø102 Direction of travel Dimensions shown are nominal in millimeters Packaging quantity: 4000 units/reel

Subject to change or obsolescence without notice Rev A 01-Nov-2001 Page 5 of 5 Maximum Ratings Parameter Symbol Minimum Maximum Unit Operating Temperature Range T -20 +70 oC Storage Temperature Range T stg -40 +85 oC Warnings

  • Electrostatic Sensitive Device (ESD)
  • Avoid ultrasonic exposure Links to Additional Technical Information PCB Layout Tips Qualification Flowchart Soldering Profile S-Parameters Other Technical Information Contact Information PO Box 609501 Orlando, FL 32860-9501 USA Phone: +1 (407) 886-8860 Fax: +1 (407) 886-7061 Email: custservice@sawtek.com Web: www.sawtek.com Or contact one of our worldwide network of sales offices, representatives or distributors