ICS853054 ICST | Alldatasheet

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Systems, Inc. 853054AG www.icst.com/products/hiperclocks.html REV. A JANUARY 5, 2006 ICS853054 4:1, DIFFERENTIAL-TO-3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER PRELIMINARY GENERAL DESCRIPTION The ICS853054 is an 4:1 Differential-to-3.3V or 2.5V LVPECL/ECL Clock Multiplexer which can operate up to 2.5GHz and is a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS853054 has 4 selectable differential clock inputs. The PCLKx, nPCLKx in- put pairs can accept LVPECL, LVDS, CML or SSTL levels. The fully differential architecture and low propagation delay make it ideal for use in clock distribution circuits. The select pins have internal pulldown resistors. The SEL1 pin is the most significant bit and the binary number applied to the select pins will select the same numbered data input (i.e., 00 selects PCLK0, nPCLK0).

FEATURES

  • High speed 4:1 differential multiplexer
  • One differential 3.3V or 2.5V LVPECL output
  • Four selectable differential PCLK, nPCLK inputs
  • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL
  • Maximum output frequency: 3.2GHz
  • Translates any single ended input signal to LVPECL levels with resistor bias on nPCLKx input
  • Part-to-part skew: TBD
  • Propagation delay: 465ps (typical)
  • Additive phase jitter, RMS: 0.238ps (typical)
  • LVPECL mode operating voltage supply range: VCC = 2.375V to 3.465V, VEE = 0V
  • ECL mode operating voltage supply range: VCC = 0V, VEE = -3.465V to -2.375V
  • -40°C to 85°C ambient operating temperature
  • Available in both standard and lead-free RoHS-compliant packages BLOCK DIAGRAM PIN ASSIGNMENT HiPerClockS™ ICS PCLK0 nPCLK0 PCLK1 nPCLK1 VCC SEL0 SEL1 VEE VCC Q nQ VEE nPCLK3 PCLK3 nPCLK2 PCLK2 ICS853054 16-Lead TSSOP 4.4mm x 5.0mm x 0.92mm package body G Package Top View PCLK0 nPCLK0 PCLK1 nPCLK1 PCLK2 nPCLK2 PCLK3 nPCLK3 SEL1 SEL0 Q nQ The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.

TABLE 1. PIN DESCRIPTIONS TABLE 2. PIN CHARACTERISTICS TABLE 3. CLOCK INPUT FUNCTION TABLE

Systems, Inc. 853054AG www.icst.com/products/hiperclocks.html REV. A JANUARY 5, 2006 ICS853054 4:1, DIFFERENTIAL-TO-3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER PRELIMINARY TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375 TO 3.465V; VEE = 0V l o b m y S r e t e m a r a P s n o iti d n o C t s e T m u m i n i M l a c i p y T m u m i x a M s ti n U V C C e g a tlo V ylp p u S e vitis o P V I C C t n e rr u C ylp p u S r e w o P A m TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = 2.375 TO 3.465V; VEE = 0V l o b m y S r e t e m a r a P s n o iti d n o C t s e T m u m i n i M l a c i p y T m u m i x a M s ti n U I H I t n e rr u C h gi H t u p n I K L C P K L C P K L C P n K L C P n V C C V N I V A µ I L I t n e rr u C w o L t u p n I K L C P K L C P V C C V V N I V A µ K L C P n K L C P n V C C V V N I V A µ V P P e g a tlo V t u p n I k a e P o k a e P V V R M C e g a tlo V t u p n I e d o M n o m m o C E T O N V V H O E T O N e g a tlo V e g a tlo V h gi H t u p t u O V C C V V L O E T O N e g a tlo V w o L t u p t u O V C C V V G N I W S g ni w S e g a tlo V t u p t u O k a e P o k a e P V V s a d e nif e d si e g a tlo v e d o m n o m m o C E T O N H I . V si x K L C P n K L C P r o f e g a tlo v t u p ni m u m ix a m e h t n oit a cilp p a d e d n e elg nis r o F E T O N C C V h ti w d e t a ni m r e t st u p t u O E T O N Ω V o t C C V TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = 2.375 TO 3.465V; VEE = 0V Supply Voltage, VCC 4.6V (LVPECL mode, VEE = 0) Negative Supply Voltage, VEE -4.6V (ECL mode, VCC = 0) Inputs, VI (LVPECL mode) -0.5V to VCC + 0.5V Inputs, VI (ECL mode) 0.5V to VEE - 0.5V Outputs, IO Continuous Current 50mA Surge Current 100mA Operating Temperature Range, TA -40°C to +85°C Storage Temperature, TSTG -65°C to 150°C Package Thermal Impedance, θJA 89°C/W (0 lfpm) (Junction-to-Ambient) NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifi- cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Character- istics is not implied. Exposure to absolute maxi- mum rating conditions for extended periods may affect product reliability. ABSOLUTE MAXIMUM RATINGS l o b m y S r e t e m a r a P s n o iti d n o C t s e T m u m i n i M l a c i p y T m u m i x a M s ti n U V H I e g a tlo V h gi H t u p n I V C C V V C C V V C C V V C C V V L I e g a tlo V w o L t u p n I V C C V V V C C V V I H I t n e rr u C h gi H t u p n I L E S L E S V C C V N I V V C C V N I V A µ I L I t n e rr u C w o L t u p n I L E S L E S V C C V V N I V V C C V V N I V A µ

Systems, Inc. 853054AG www.icst.com/products/hiperclocks.html REV. A JANUARY 5, 2006 ICS853054 4:1, DIFFERENTIAL-TO-3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER PRELIMINARY ADDITIVE PHASE JITTER Additive Phase Jitter, RMS @ 155.52MHz = <0.238ps typical -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 10k 100k 10M 100M The spectral purity in a band at a specific offset from the funda- mental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fun- damental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The de- the 1Hz band to the power in the fundamental. When the re- quired offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the funda- mental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. vice meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment. OFFSET FROM CARRIER FREQUENCY (HZ) SSB PHASE NOISE dBc/HZ

Systems, Inc. 853054AG www.icst.com/products/hiperclocks.html REV. A JANUARY 5, 2006 ICS853054 4:1, DIFFERENTIAL-TO-3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER PRELIMINARY PARAMETER MEASUREMENT INFORMATION PROPAGATION DELAY DIFFERENTIAL INPUT LEVEL OUTPUT LOAD AC TEST CIRCUIT PART-TO-PART SKEW OUTPUT RISE/FALL TIME nQx Qx nQy Qy PART 1 PART 2 tsk(pp) VCMR Cross Points VPP VEE VCC Clock Outputs 20% 80% 80% 20% tR tF VOD tPD nPCLK0:3 PCLK0:3 nQ Q SCOPE Qx nQx LVPECL VCC VEE nPCLK0:3 PCLK0:3 -1.465V to -0.375V

This section provides information on power dissipation and junction temperature for the ICS853054. Equations and example calculations are also provided. The total power dissipation for the ICS853054 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V ± 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. moderate air flow of 200 meters per second and a multi-layer board, the appropriate value is 81.8°C/W per Table 6 below. and the type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE θθθθθJA FOR 16-PIN TSSOP FORCED CONVECTION NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

  1. Calculations and Equations.

The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 5. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. FIGURE 5. LVPECL DRIVER CIRCUIT AND TERMINATION

TABLE 7. θJAVS. AIR FLOW TABLE FOR 16 LEAD TSSOP NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

TABLE 8. PACKAGE DIMENSIONS

TABLE 9. ORDERING INFORMATION for use in life support devices or critical medical instruments. The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.