ICS8305I ICST | Alldatasheet

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Systems, Inc. 8305AGI www.icst.com/products/hiperclocks.html REV. B MAY 19, 2005 ICS8305I LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER GENERAL DESCRIPTION The ICS8305I is a low skew, 1-to-4, Differential/ LVCMOS-to-LVCMOS/LVTTL Fanout Buffer and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS8305I has selectable clock inputs that accept either differential or single ended input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Outputs are forced LOW when the clock is disabled. A sepa- rate output enable pin controls whether the outputs are in the active or high impedance state. Guaranteed output and part-to-part skew characteristics make the ICS8305I ideal for those applications demanding well de- fined performance and repeatability. HiPerClockS™ ICS BLOCK DIAGRAM PIN ASSIGNMENT GND OE VDD CLK_EN CLK nCLK CLK_SEL LVCMOS_CLK VDDO GND VDDO GND ICS8305I 16-Lead TSSOP 4.4mm x 3.0mm x 0.92mm package body G Package Top View

FEATURES

  • 4 LVCMOS/LVTTL outputs
  • Selectable differential or LVCMOS/LVTTL clock inputs
  • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
  • LVCMOS_CLK supports the following input types: LVCMOS, LVTTL
  • Maximum output frequency: 350MHz
  • Output skew: 40ps (maximum)
  • Part-to-part skew: 700ps (maximum)
  • Additive phase jitter, RMS: 0.04ps (typical)
  • 3.3V core, 3.3V, 2.5V or 1.8V output operating supply
  • -40°C to 85°C ambient operating temperature
  • Lead-Free package fully RoHS compliant LVCMOS_CLK CLK nCLK CLK_SEL CLK_EN OE D Q LE

TABLE 1. PIN DESCRIPTIONS TABLE 2. PIN CHARACTERISTICS

FIGURE 1. CLK_EN TIMING DIAGRAM

Systems, Inc. 8305AGI www.icst.com/products/hiperclocks.html REV. B MAY 19, 2005 ICS8305I LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C l o b m y S r e t e m a r a P s n o iti d n o C t s e T m u m i n i M l a c i p y T m u m i x a M s ti n U V D D e g a tlo V ylp p u S e r o C V V O D D e g a tlo V ylp p u S t u p t u O V V V I D D t n e rr u C ylp p u S r e w o P A m I O D D t n e rr u C ylp p u S t u p t u O A m l o b m y S r e t e m a r a P s n o iti d n o C t s e T m u m i n i M l a c i p y T m u m i x a M s ti n U V H I t u p n I e g a tlo V h gi H E O L E S K L C N E K L C V D D V K L C S O M C V L V D D V V L I t u p n I e g a tlo V w o L E O L E S K L C N E K L C V K L C S O M C V L V I H I t u p n I t n e rr u C h gi H E O L E S K L C N E K L C V D D V N I V A µ K L C S O M C V L V D D V N I V A µ I L I t u p n I t n e rr u C w o L E O L E S K L C N E K L C V D D V V N I V A µ K L C S O M C V L V D D V V N I V A µ V H O E T O N e g a tlo V h gi H t u p t u O V O D D V V V O D D V V V O D D V V V O D D V V L O E T O N e g a tlo V w o L t u p t u O V O D D V V V O D D V V V O D D V V V I L Z O w o L t n e rr u C e t a tsir T t u p t u O A µ I H Z O h gi H t n e rr u C e t a tsir T t u p t u O A µ h ti w d e t a ni m r e t st u p t u O E T O N Ω V o t O D D .tiu c ri C ts e T d a o L t u p t u O n oit a m r o f n I t n e m e r u s a e M r e t e m a r a P e e S TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, θJA 89°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions be- yond those listed in the DC Characteristics or AC Character- istics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.

Systems, Inc. 8305AGI www.icst.com/products/hiperclocks.html REV. B MAY 19, 2005 ICS8305I LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C l o b m y S r e t e m a r a P s n o iti d n o C t s e T m u m i n i M l a c i p y T m u m i x a M s ti n U I H I t n e rr u C h gi H t u p n I K L C n V N I V D D V A µ K L C V N I V D D V A µ I L I t n e rr u C w o L t u p n I K L C n V N I V V D D V A µ K L C V N I V V D D V A µ V P P e g a tlo V t u p n I k a e P o k a e P V V R M C e g a tlo V t u p n I e d o M n o m m o C E T O N D N G V D D V s n oit a cilp p a d e d n e elg nis r o F E T O N V si K L C n K L C r o f e g a tlo v t u p ni m u m ix a m e h t D D V V s a d e nif e d si e g a tlo v e d o m n o m m o C E T O N H I . TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V ± 5%, TA = -40°C TO 85°C l o b m y S r e t e m a r a P s n o iti d n o C t s e T m u m i n i M l a c i p y T m u m i x a M s ti n U f X A M y c n e u q e r F t u p t u O K L C n K L C f e R z H M K L C S O M C V L f e R z H M p t H L ale D n oit a g a p o r P h gi H o t w o L K L C S O M C V L A E T O N K L C n K L C B E T O N s n t o k s E T O N w e k S t u p t u O e g d E g nisi R e h t n o d e r u s a e M s p t p p k s E T O N w e k S tr a P o t-tr a P s p t tij S M R e ttiJ e s a h P e vitid d A r e ff u B n oitc e s r e ttiJ e s a h P e vitid d A o t r e f e r E T O N s p tR t F e m i T lla F e si R t u p t u O o t s p c d o elc y C yt u D t u p t u O z H M z H M ƒ t N E E T O N e m i T elb a n E t u p t u O s n t S I D E T O N e m i T elb a si D t u p t u O s n V e h t m o rf d e r u s a e M A E T O N D D V o t t u p ni e h t f o O D D u p t u o e h t f o V o t t nio p g nis s o r c t u p nilait n e r e ffid e h t m o rf d e r u s a e M B E T O N O D D u p t u o e h t f o n oitid n o c d a olla u q e h ti w d n a e g a tlo v ylp p u s e m a s e h t t a st u p t u o n e e w t e b w e k s s a d e nif e D E T O N V t a d e r u s a e M O D D d n a s e g a tlo v ylp p u s e m a s e h t a g nit a r e p o s e civ e d t n e r e ffid n o st u p t u o n e e w t e b w e k s s a d e nif e D E T O N V t a d e r u s a e m sit u p t u o e h t e civ e d h c a e n o t u p nif o e p yt e m a s e h t g nis U n oitid n o c d a olla u q e h ti w O D D n oitc u d o r p ni d e ts e t t o N n oit a zir e tc a r a h c y b d e e t n a r a u g e r a s r e t e m a r a p e s e h T E T O N c olc t u p ni e n o yln o g nivir D E T O N d r a d n a t S C E D E J h ti w e c n a d r o c c a ni d e nif e d si r e t e m a r a p sih T E T O N

Systems, Inc. 8305AGI www.icst.com/products/hiperclocks.html REV. B MAY 19, 2005 ICS8305I LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER TABLE 5C. AC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 1.8V ± -0.15V, TA = -40°C TO 85°C TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = -40°C TO 85°C l o b m y S r e t e m a r a P s n o iti d n o C t s e T m u m i n i M l a c i p y T m u m i x a M s ti n U f X A M y c n e u q e r F t u p t u O K L C n K L C f e R z H M K L C S O M C V L f e R z H M p t H L ale D n oit a g a p o r P h gi H o t w o L K L C S O M C V L A E T O N K L C n K L C B E T O N s n t o k s E T O N w e k S t u p t u O e g d E g nisi R e h t n o d e r u s a e M s p t p p k s E T O N w e k S tr a P o t-tr a P s p t tij S M R e ttiJ e s a h P e vitid d A r e ff u B n oitc e s r e ttiJ e s a h P e vitid d A o t r e f e r E T O N s p tR t F e m i T lla F e si R t u p t u O o t s p c d o elc y C yt u D t u p t u O z H M z H M f t N E E T O N e m i T elb a n E t u p t u O s n t S I D E T O N e m i T elb a si D t u p t u O s n V e h t m o rf d e r u s a e M A E T O N D D V o t t u p ni e h t f o O D D u p t u o e h t f o V o t t nio p g nis s o r c t u p nilait n e r e ffid e h t m o rf d e r u s a e M B E T O N O D D u p t u o e h t f o V t a d e r u s a e M n oitid n o c d a olla u q e h ti w d n a e g a tlo v ylp p u s e m a s e h t t a st u p t u o n e e w t e b w e k s s a d e nif e D E T O N O D D d n a s e g a tlo v ylp p u s e m a s e h t a g nit a r e p o s e civ e d t n e r e ffid n o st u p t u o n e e w t e b w e k s s a d e nif e D E T O N V t a d e r u s a e m sit u p t u o e h t e civ e d h c a e n o t u p nif o e p yt e m a s e h t g nis U n oitid n o c d a olla u q e h ti w O D D n oitc u d o r p ni d e ts e t t o N n oit a zir e tc a r a h c y b d e e t n a r a u g e r a s r e t e m a r a p e s e h T E T O N c olc t u p ni e n o yln o g nivir D E T O N d r a d n a t S C E D E J h ti w e c n a d r o c c a ni d e nif e d si r e t e m a r a p sih T E T O N l o b m y S r e t e m a r a P s n o iti d n o C t s e T m u m i n i M l a c i p y T m u m i x a M s ti n U f X A M y c n e u q e r F t u p t u O K L C n K L C f e R z H M K L C S O M C V L f e R z H M p t H L ale D n oit a g a p o r P h gi H o t w o L K L C S O M C V L A E T O N K L C n K L C B E T O N s n t o k s E T O N w e k S t u p t u O e g d E g nisi R e h t n o d e r u s a e M s p t p p k s E T O N w e k S tr a P o t-tr a P s p tj ti S M R e ttiJ e s a h P e vitid d A r e ff u B n oitc e s r e ttiJ e s a h P e vitid d A o t r e f e r E T O N s p tR t F e m i T lla F e si R t u p t u O o t s p c d o elc y C yt u D t u p t u O z H M z H M f t N E E T O N e m i T elb a n E t u p t u O s n t S I D E T O N e m i T elb a si D t u p t u O s n B elb a T e e s e t o n r o F

Systems, Inc. 8305AGI www.icst.com/products/hiperclocks.html REV. B MAY 19, 2005 ICS8305I LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER ADDITIVE PHASE JITTER Input/Output Additive Phase Jitter at 155.52MHz = 0.04ps typical -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 10k 100k 10M 100M The spectral purity in a band at a specific offset from the funda- mental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fun- damental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The de- the 1Hz band to the power in the fundamental. When the re- quired offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the funda- mental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. vice meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment. OFFSET FROM CARRIER FREQUENCY (HZ) SSB PHASE NOISE dBc/HZ

Systems, Inc. 8305AGI www.icst.com/products/hiperclocks.html REV. B MAY 19, 2005 ICS8305I LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION PART-TO-PART SKEW tsk(o) VDDO VDDO Qx Qy DIFFERENTIAL INPUT LEVEL OUTPUT SKEW 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT SCOPE Qx LVCMOS VCMR Cross Points VPP GND CLK nCLK VDD tsk(pp) VDDO VDDO Qx Qy PART 1 PART 2 -1.65V±5% 1.65V±5% 3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT 3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT -1.25V±5% 1.25V±5% SCOPE Qx LVCMOS -0.9V±0.075V 0.9V±0.075V VDD VDDO 2.4V±0.09V SCOPE Qx LVCMOS VDD VDDO 2.05V±5% VDD, VDDO GND GND GND

Systems, Inc. 8305AGI www.icst.com/products/hiperclocks.html REV. B MAY 19, 2005 ICS8305I LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER PROPAGATION DELAY OUTPUT RISE/FALL TIME Clock Outputs 20% 80% 80% 20% tR tF nCLK CLK Q0:Q3 tPD VDDO VDD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD tPERIOD tPW tPERIOD odc = VDDO x 100% tPW Q0:Q3 LVCMOS_CLK

TABLE 6. θJAVS. AIR FLOW TABLE FOR 16 LEAD TSSOP NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. FIGURE 4. EXAMPLE ICS8305I LVCMOS CLOCK OUTPUT BUFFER SCHEMATIC

TABLE 7. PACKAGE DIMENSIONS

TABLE 8. ORDERING INFORMATION for use in life support devices or critical medical instruments. The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.

Systems, Inc. 8305AGI www.icst.com/products/hiperclocks.html REV. B MAY 19, 2005 ICS8305I LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER T E E H S Y R O T S I H N O I S I V E R v e R e l b a T e g a P e g n a h C f o n o it p ir c s e D e t a D A T m o rf o p yt r e b m u N r e d r O /tr a P d e tc e rr o c elb a t n oit a m r o f n I g nir e d r O I G A S C I o t T I G A S C I B C T A T .la cip yt s p o t la cip yt s p m o rf tijt d e g n a h c s elb a T s citsir e tc a r a h C C A olp r e ttiJ e s a h P e vitid d A d e t a d p U B T n oit pir c s e d N E K L C d e tc e rr o c elb a T n oit pir c s e D ni P B T r e b m u n tr a p e e r F d a e L d e d d a elb a T n oit a m r o f n I g nir e d r O