82P33724

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82P33724 REVISION 1 09/23/14 1 ©2014 Integrated Device Technology, Inc. Port Synchronizer for IEEE 1588 and Synchronous Ethernet 82P33724 HIGHLIGHTS

• DPLL1 and DPLL2 can be used on line cards to manage the genera- tion of synchronous port clocks and IEEE 1588 synchronization sig- nals based on multiple system backplane references
• DPLL3 can be used on line cards to select incoming line clocks for use on system backplanes; it can also be used for general purpose timing applications
• APLL1 and APLL2 generate clocks with jitter < 1 ps RMS (12 kHz to

20 MHz) for: 1000BASE-T and 1000BASE-X ports and to generate

IEEE 1588 time stamp clocks and 1 pulse per second (PPS) signals

• Fractional-N input dividers suppor t a wide range of reference fre- quencies
• The device can be configured from an external EEPROM after reset

FEATURES

• Differential reference inputs (IN1 to IN4) accept clock frequencies between 2 kHz and 650 MHz
• Single ended inputs (IN5 to IN6) accept reference clock frequencies between 2 kHz and 162.5 MHz
• Loss of Signal (LOS) pins (LOS0 to LOS3) can be assigned to any clock reference input
• Reference monitors qualify/disqua lify references depending on activ- ity, frequency and LOS pins
• Automatic reference selection state machines select the active refer- ence for each DPLL based on the reference monitors, priority tables, revertive and non-revertive settings and other programmable settings
• Fractional-N input dividers enable the DPLLs to lock to a wide range of reference clock frequencies including: 10/100/1000 Ethernet, 10G Ethernet, OTN, SONET/SDH, PDH, TDM, GSM and GNSS frequen- cies
• Any reference inputs (IN1 to IN6) can be designated as external sync pulse inputs (1 PPS, 2 kHz, 4 kHz or 8 kHz) associated with a select- able reference clock input
• FRSYNC_8K_1PPS and MFRSYNC_2K_1PPS output sync pulses that are aligned with the selected ex ternal input sync pulse input and frequency locked to the associated reference clock input
• DPLL1 and DPLL2 can be configured with bandwidths between 18 Hz and 567 Hz
• DPLL1 and DPLL2 lock to input references with frequencies between 2 kHz and 650 MHz
• DPLL3 locks to input references with frequencies between 8 kHz and

650 MHz

• DPLL1 and DPLL2 generate clocks with PDH, TDM, GSM, CPRI/ OBSAI, 10/100/1000 Ethernet and GN SS frequencies; these clocks are directly available on OUT1 and OUT8
• DPLL3 generates N x 8 kHz clocks up to 100 MHz that are output on OUT9 and OUT10
• APLL1 and APLL2 can be connected to DPLL1 and DPLL2
• APLL1 and APLL2 generate 10/100/1000 Ethernet, 10G Ethernet, or SONET/SDH frequencies
• Any of eight common TCXO/OCXO frequencies can be used for the System Clock: 10 MHz, 12.8 MHz, 13 MHz, 19.44 MHz, 20 MHz, 24.576 MHz, 25 MHz or 30.72 MHz
• The I2C slave, SPI or the UART interface can be used by a host pro- cessor to access the control and status registers
• The I2C master interface can aut omatically load a device configura- tion from an external EEPROM after reset
• Differential outputs OUT3 to OUT6 output clocks with frequencies between 1 PPS and 650 MHz
• Single ended outputs OUT1, OUT2, OUT7, and OUT8 output clocks with frequencies between 1 PPS and 125 MHz
• Single ended outputs OUT9 and OUT10 output clocks N*8 kHz multi- ples up to 100 MHz
• DPLL1 and DPLL2 support independent programmable delays for each of IN1 to IN16; the delay for each input is programmable in steps of 0.61 ns with a range of ~±78 ns
• The input to output phase delay of DPLL1 and DPLL2 is programma- ble in steps of 0.0745 ps with a total range of ±20 μs
• The clock phase of each of the output dividers for OUT1 to OUT8 is individually programmable in steps of ~200 ps with a total range of +/ -180°
• 1149.1 JTAG Boundary Scan
• 72-pin QFN green package

APPLICATIONS

• Synchronous clock generation for 10/40G and lower rate, Ethernet, PON OLT and SONET/SDH line card
• Access routers, edge routers, core routers
• Carrier Ethernet switches
• Multiservice access platforms
• P O N O L T
• LTE eNodeB

82P33724 SHORT FORM DATA SHEET PORT SYNCHRONIZER FOR IEEE 1588 AND SYNCHRONOUS ETHERNET

2 REVISION 1 09/23/14

DESCRIPTION

The 82P33724 Port Synchronizer for IEEE 1588 and Synchronous Ethernet provides tools to manage timing references, clock conversion and tim- ing paths for IEEE 1588 and Synchronous Ethernet (SyncE). The device supports up to three independent timing paths for: IEEE 1588 clock genera- tion; SyncE clock generation; and general pur pose frequency translation. The device outputs low-jitter clocks that can directly synchronize Ethernet interfaces; as well as SONET/SDH and PDH interfaces and IEEE 1588 Time Stamp Units (TSUs). The 82P33724 accepts four differential reference inputs and tw o single ended reference inputs that can operate at common Ethern et, SONET/ SDH and PDH frequencies that range from 2 kHz to 650 MHz. The references are continually monitored for loss of signal and for frequency offset per user programmed thresholds. All of the refe rences are available to all three Digital PLLs (DPLLs). The active reference for eac h DPLL is determined by forced selection or by automatic selection based on user programmed priorities, locking allowances, reference monitors, and LOS inputs. The 82P33724 can accept a clock reference and an associated phase locked sync signal as a pair. DPLL1/DPLL2 can lock to the clock reference and align the frame sync and multi-frame sync outputs with the pair ed sync input. The device allows any of the differential or single ended reference inputs to be configured as sync inputs that can be associated with any of the other differential or single ended reference inputs. The input sync signals can have a frequency of 1 PPS, 2 kHz, 4kHz or 8 kHz. This feature enables DPLL1/DPLL2 to phase align its frame sync and multi-frame sync outputs with a sync input without the need use a low bandwidth setting to lock directly to the sync input. The DPLLs support three primary operating m odes: Free-Run, Locked and Holdover. In Free- Run mode the DPLLs synthesize clocks ba sed on the system clock alone. In Locked mode the DPLLs filter reference clock jitter with the selected bandwidth. In Locked mode, the long-term output fre- quency accuracy is the same as the long term frequency accuracy of the selected input reference. In Holdover mode, the DPLL use s frequency data acquired while in Locked mode to generate accurate frequencies when input references are not available. The 82P33724 requires a system clock for it s reference monitors and other digital ci rcuitry. The frequency accuracy of the syst em clock deter- mines the frequency accuracy of the DPLLs in Free-Run mode. The frequency stability of the system clock determines the frequenc y stability of the DPLLs in Free-Run mode and in Holdover mode; and it affects the wander generation of the DPLLs in Locked mode. DPLL1 and DPLL2 can be configured with a range of selectable filtering bandwidths from 18 Hz to 567 Hz. DPLL3 is a wideband (BW > 25Hz) fre- quency translator that can be used, for example, to convert a recovered SyncE clock to a 25MHz backplane clock. Clocks generated by DPLL1 and DPLL2 can be passed through APLL1 or APLL2 which are LC based jitter attenuating Analog PLLs (APLLs). The output clocks generated by APLL1 and APLL2 are suitable for serial GbE and lower rate interfaces, and for IEEE 1588 time stamps clocks and 1 PPS signals. All 82P33724 control and status registers are accessed through an I2C slave, SPI or the UART micr oprocessor interface. For conf iguring the DPLLs, APLL1 and APLL2, the I2C master interface can automatically load a configuration from an external EEPROM after reset.

Figure 1. Functional Block Diagram

4 REVISION 1 09/23/14

1 PIN ASSIGNMENT

Figure 2. Pin Assignment (Top View)

REVISION 1 09/23/14 5 PORT SYN CHRONIZER FOR IEEE 1588 AND SYNCHRONOUS ETHERNET 82P33724 SHORT FORM DATA SHEET

2 PIN DESCRIPTION

Table 1: Pin Description Pin No. Name I/O Type Description Global Control Signal 6O S C I I C M O S OSCI: Crystal Oscillator System Clock A clock provided by a crystal oscillator is input on this pin. It is the system clock for the device. The oscillator frequency is selected via pins XO_FREQ0 ~ XO_FREQ2

59 SONET/SDH/

I pull-down CMOS SONET/SDH: SONET / SDH Frequency Selection During reset, this pin determines the default value of the IN_SONET_SDH bit: High: The default value of the IN_SONET_SDH bit is ‘1’ (SONET); Low: The default value of the IN_SONET_SDH bit is ‘0’ (SDH). After reset, the value on this pin takes no effect. LOS3- This pin is used to disqualify input clocks. See input clocks section for more details.

52 RSTB I

RSTB: Reset A low pulse of at least 50 µs on this pin resets the device. If loading from an EEPROM, the maximum time from RSTB de-as sert to have stable clocks is 100ms. If not loading from EEPROM the maximum time from RSTB de-assert to have sta- ble clocks is 5ms. XO_FREQ0/ LOS0 XO_FREQ1/ LOS1 XO_FREQ2/ LOS2 I pull-down CMOS XO_FREQ0 ~ XO_FREQ2: These pins set the oscillator frequency. XO_FREQ[2:0] Oscillator Frequency (MHz) 000 10.000 001 12.800 010 13.000 011 19.440 100 20.000 101 24.576 110 25.000 111 30.720 LOS0 ~ LOS2 - These pins are used to disqualify input clocks. See input clocks section for more details. After reset, this pin takes on the operation of LOS0-LOS2 Input Clock and Frame Synchronization Input Signal IN1_POS IN1_NEG I PECL/LVDS IN1_POS / IN1_NEG: Positive / Negative Input Clock 1 A reference clock is input on this pin.This pin can also be used as a sync input, and in this case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin. IN2_POS IN2_NEG I PECL/LVDS IN2_POS / IN2_NEG: Positive / Negative Input Clock 1 A reference clock is input on this pin.This pin can also be used as a sync input, and in this case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin. IN3_POS IN3_NEG I PECL/LVDS IN3_POS / IN3_NEG: Positive / Negative Input Clock 3 A reference clock is input on this pin.This pin can also be used as a sync input, and in this case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin. IN4_POS IN4_NEG I PECL/LVDS IN4_POS / IN4_NEG: Positive / Negative Input Clock 4 A reference clock is input on this pin.This pin can also be used as a sync input, and in this case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin.

37 IN5 I

IN5: Input Clock 5 A reference clock is input on this pin.This pin can also be used as a sync input, and in this case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin.

41 IN6

I pull-down CMOS IN6: Input Clock 6 A reference clock is input on this pin.This pin can also be used as a sync input, and in this case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin. Output Frame Synchronization Signal

43 FRSYNC

_8K_1PPS OC M O S FRSYNC_8K_1PPS: 8 kHz Frame Sync Output An 8 kHz signal or a 1PPS sync signal is output on this pin.

44 MFRSYNC

_2K_1PPS OC M O S MFRSYNC_2K_1PPS: 2 kHz Multiframe Sync Output A 2 kHz signal or a 1PPS sync signal is output on this pin.

82P33724 SHORT FORM DATA SHEET PORT SYNCHRONIZER FOR IEEE 1588 AND SYNCHRONOUS ETHERNET

6 REVISION 1 09/23/14

OUT2 OC M O S OUT1 ~ OUT2: Output Clock 1 ~ 2 OUT3_POS OUT3_NEG O PECL/LVDS OUT3_POS / OUT3_NEG: Positive / Negative Output Clock 3 This output is set to LVDS by default.The LVDS output has internal 100 ohm termination. OUT4_POS OUT4_NEG O PECL/LVDS OUT4_POS / OUT4_NEG: Positive / Negative Output Clock 4 This output is set to LVDS by default.The LVDS output has internal 100 ohm termination. OUT5_POS OUT5_NEG O PECL/LVDS OUT5_POS / OUT5_NEG: Positive / Negative Output Clock 5 This output is set to LVDS by default.The LVDS output has internal 100 ohm termination. OUT6_POS OUT6_NEG O PECL/LVDS OUT6_POS / OUT6_NEG: Positive / Negative Output Clock 6 This output is set to LVDS by default.The LVDS output has internal 100 ohm termination. OUT7 OUT8 OC M O S OUT7 ~ OUT8: Output Clock 7 ~ 8 OUT9 OUT10 OC M O S OUT9 ~ OUT10: Output Clock 9 ~ 10 Miscellaneous

13 VC1 O Analog

VC1: APLL1 VC Output An external RC filter (a resistor in series with a capacitor to ground, and another capacitor in parallel) should be connected to this pin. 1V C 2 O A n a l o g VC2: APLL2 VC Output An external RC filter (a resistor in series with a capacitor to ground, and another capacitor in parallel) should be connected to this pin. Lock Signal

54 DPLL3_LOCK OC M O S DPLL3_LOCK

This pin goes high when DPLL3 is locked

56 DPLL2_LOCK OC M O S DPLL2_LOCK

This pin goes high when DPLL2 is locked

55 DPLL1_LOCK OC M O S DPLL1_LOCK

This pin goes high when DPLL1 is locked Microprocessor Interface

57 INT_REQ O

Tri-state CMOS INT_REQ: Interrupt Request This pin is used as an interrupt request. MPU_MODE1/ I2CM_SCL MPU_MODE0/ I2CM_SDA I/O pull-up CMOS/ Open Drain MPU_MODE[1:0]: Microprocessor Interface Mode Selection During reset, these pins determine the default value of the MPU_SEL_CNFG[1:0] bits as fol- lows: 00: I2C mode 01: SPI mode 10: UART mode 11: I2C master (EEPROM) mode I2CM_SCL: Serial Clock Line In I2C master mode, the serial clock is output on this pin. I2CM_SDA: Serial Data Input for I2C Master Mode In I2C master mode, this pin is used as the for the serial data. Table 1: Pin Description (Continued) Pin No. Name I/O Type Description

REVISION 1 09/23/14 7 PORT SYN CHRONIZER FOR IEEE 1588 AND SYNCHRONOUS ETHERNET 82P33724 SHORT FORM DATA SHEET

47 SDI/I2C_AD2/

UART_RX I pull-down CMOS SDI: Serial Data Input In Serial mode, this pin is used as the serial data input. Address and data on this pin are seri- ally clocked into the device on the rising edge of SCLK. I2C_AD2: Device Address Bit 2 In I2C mode, I2C_AD[2:0] pins are the address bus of the microprocessor interface. UART_RX In UART mode, this pin is used as the receive data (UART Receive)

48 CLKE/I2C_AD1 I

CLKE: SCLK Active Edge Selection In Serial mode, this pin is an input, it selects the active edge of SCLK to update the SDO: High - The falling edge; Low - The rising edge. I2C_AD1: Device Address Bit 1 In I2C mode, I2C_AD[2:0] pins are the address bus of the microprocessor interface.

49 CS/I2C_AD0 I

CS: Chip Selection In Serial modes, this pin is an input.A transition from high to low must occur on this pin for each read or write operation and this pin should remain low until the operation is over. I2C_AD0: Device Address Bit 0 In I2C mode, I2C_AD[2:0] pins are the address bus of the microprocessor interface.

50 SCLK/I2C_SCL I

SCLK: Shift Clock In Serial mode, a shift clock is input on this pin. Data on SDI is sampled by the device on the rising edge of SCLK. Data on SDO is updated on the active edge of SCLK. The active edge is determined by the CLKE. I2C_SCL: Serial Clock Line In I2C mode, the serial clock is input on this pin. SDO/I2C_SDA/ UART_TX I2C_SDA I/O pull-up CMOS/ Open Drain SDO: Serial Data Output In Serial mode, this pin is used as the serial data output. Data on this pin is serially clocked out of the device on the active edge of SCLK. I2C_SDA: Serial Data Input/Output In I2C mode, this pin is used as the input/output for the serial data. UART_TX: In UART mode, this pin is used as the transmit data (UART Transmit) JTAG (per IEEE 1149.1)

14 TMS I

TMS: JTAG Test Mode Select The signal on this pin controls the JTAG test performance and is sampled on the rising edge of TCK.

15 TRSTB I

TRSTB: JTAG Test Reset (Active Low) A low signal on this pin resets the JTAG test port. This pin should be connected to ground when JTAG is not used.

16 TCK I

TCK: JTAG Test Clock The clock for the JTAG test is input on this pin. TDI and TMS are sampled on the rising edge of TCK and TDO is updated on the falling edge of TCK. If TCK is idle at a low level, all stored-state devices contained in the test logic will indefinitely retain their state.

17 TDI I

TDI: JTAG Test Data Input The test data are input on this pin. They are clocked into the device on the rising edge of TCK. Table 1: Pin Description (Continued) Pin No. Name I/O Type Description

82P33724 SHORT FORM DATA SHEET PORT SYNCHRONIZER FOR IEEE 1588 AND SYNCHRONOUS ETHERNET

8 REVISION 1 09/23/14

2.1 RECOMMENDATIONS FOR UNUSED INPUT

2.1.1 INPUTS

All control pins have internal pul l-ups or pull-downs; additional resis- tance is not required but can be added for additional protection. A 1k Ω resistor can be used. Single-Ended Clock Inputs For protection, unused single- ended clock inputs should be tied to ground. Differential Clock Inputs For applications not requiring the use of a differential input, both *_POS and *_NEG can be left floating. Though not required, but for additional protection, a 1k Ω resistor can be tied from _POS to ground.

2.1.2 OUTPUTS

For applications not requiring the use of a status pin, we recommend bringing out to a test point for debugging purposes. Single-Ended Clock Outputs All unused single-ended clock outputs can be left floating, or can be brought out to a test point for debugging purposes. Differential Clock Outputs All unused differential outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated.

18 TDO O

TDO: JTAG Test Data Output The test data are output on this pin. They are clocked out of the device on the falling edge of TCK. TDO pin outputs a high impedance signal except during the process of data scanning. Power & Ground 2, 3, 4, 5, 10 11, 12 VDDA Power - VDDA: Analog Core Power - +3.3V DC nominal 20, 24, 69, 72 VDDAO Power VDDAO: Analog Output Power - +3.3V DC nominal 27, 29, 64, 66 VDDDO Power VDDDO: Digital Output Power - +3.3V DC nominal 40, 62 VDDD Power VDDD: Digital Core Power - +3.3V DC nominal 42, 53 VDDD_1_8 Power VDDD_1_8: Digital Core Power - +1.8V DC nominal 19,23 VSSAO Ground VSSAO: Ground 73 (e_PAD) VSS Ground - VSS: Ground Other

58 IC - - IC: Internal Connection

Internal Use. This pin must be left open for normal operation. Table 1: Pin Description (Continued) Pin No. Name I/O Type Description

Figure 3. 72-Pin QFN Package Outline Page 1 (SAWN Option)

10 REVISION 1 09/23/14

Figure 4. 72-Pin QFN Package Outline Page 2 (SAWN Option)

Figure 5. 72-Pin QFN Package Recommended Land Pattern

82P33724 SHORT FORM DATA SHEET PORT SYNCHRONIZER FOR IEEE 1588 AND SYNCHRONOUS ETHERNET

12 REVISION 1 09/23/14

ORDERING INFORMATION

"G" after the two-letter package code denotes Pb-Free configuration, RoHS compliant.

REVISION HISTORY

Table 2: Ordering Information Part/Order Number Package Temperature 82P33724NLG 72-Pin QFN -40o to +85oC Rev. Date Description of Change

DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Product specification subject to change without notice. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright ©2014 Integrated Device Technology, Inc.. All rights reserved. Corporate Headquarters

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