75V16F64GS16 ISSI | Alldatasheet

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Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00A 08/01/02 75V16F64GS16 ISSI Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. FlexBankTM is a trademark of Fujitsu Limited, Japan. Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc

64 Mbit FLASH MEMORY AND 16 Mbit PSEUDO SRAM

STACKED MULTI-CHIP PACKAGE (MCP) PRELIMINARY INFORMATION AUGUST 2002 MCP FEATURES

  • Power supply voltage of 2.7 to 3.1 volt
  • High performance: - Flash access time as fast as 70 ns - PSRAM access time as fast as 80 ns
  • Package: 65-Ball FBGA
  • Operating Temperature: –30°C to +85°C FLASH MEMORY FEATURES
  • 0.16 µm Process Technology
  • Simultaneous Read/Write Operations (Dual Bank)
  • FlexBankTM architecture - Bank A : 8 Mbit ( 8 KB x 8 and 64 KB x 15) - Bank B : 24 Mbit (64 KB x 48) - Bank C : 24 Mbit (64 KB x 48) - Bank D : 8 Mbit ( 8 KB x 8 and 64 KB x 15) - Two virtual Banks are chosen from the combination of four physical banks (Refer to "Example of Virtual Banks Combination Table" and Simultaneous Operation Table" in FLEXIBLE SECTOR-ERASE ARCHITECTURE on FLASH MEMORY) - Host system can program or erase in one bank, and then read immediately and simultaneously from the other bank with zero latency between read and write operations. - Read-while-erase - Read-while-program
  • Single 3.0 V Read, Program, and Erase - Minimized system level power requirements
  • Minimum 100,000 Program/Erase Cycles
  • Sector Erase Architecture - Sixteen 4 Kword and one hundred twenty-six 32 Kword sectors in word - Any combination of sectors can be concurrently erased - Supports full chip erase
  • Hidden ROM (Hi-ROM) Region - 256 byte of Hi-ROM, accessible through a new "HI- ROM Enable" command sequence - Factory serialized and protected to provide a secure electronic serial number (ESN)
  • WP/ACC Input Pin - At VIL, allows protection of “outermost” 2 × 8 Kbytes on both ends of boot sectors, regardless of sector protection/unprotection status - At VIH, allows removal of boot sector protection - At VACC, program time will be reduced by 40 %
  • Embedded EraseTM Algorithms - Automatically preprograms and erases the chip or any sector
  • Embedded ProgramTM Algorithms - Automatically writes and verifies data at specified address
  • Data Polling and Toggle Bit Feature for Detection of Program or Erase Cycle Completion
  • Ready/Busy Output (RY/BY) - Hardware method for detection of program or erase cycle completion
  • Automatic Sleep Mode - When addresses remain stable, the device automatically switches itself to low power mode.
  • Low VCCf Write Inhibit ≤ 2.5 V
  • Program Suspend/Resume - Suspends the program operation to allow a read in another byte
  • Erase Suspend/Resume - Suspends the erase operation to allow a read data and/or program in another sector within the same device PSRAM FEATURES
  • Power Dissipation: - Operating : 20 mA Max - Standby : 70 µA Max - Power Down : 10 µA Max
  • Power down Control by CE2r
  • Byte Write Control : LB (DQ7-DQ0), UB (DQ15-DQ8)
  • 4 words Address Access Capability

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00A 08/01/02 75V16F64GS16 ISSI PIN DESCRIPTIONS A0-A19 Address Inputs, Common A20-A21 Address Inputs, Flash DQ0-DQ15 Data Inputs/Outputs, Common RESET Hardware Reset Pin/Acceleration, Flash CE1r,CE2r Chip Enable, PSRAM RY/BY Ready/Busy Output, Flash Open Drain Output CEf Chip Enable, Flash OE Output Enable, Common WE Write Enable, Common LB Lower-byte Control, PSRAM UB Upper-byte Control, PSRAM WP/ACC Write Protect/Acceleration, Flash RY/BY Ready/Busy Output NC No Internal Connection Vccf Device Power Supply, Flash GND Device Ground, Common Vccr Device Power, PSRAM PIN CONFIGURATION (64 Mb Flash and 16 Mb PSRAM) PACKAGE CODE: D 65 BALL FBGA (Top View) (9.00 mm x 9.00 mm Body, 0.8 mm Ball Pitch) A B C D E F G H J K NC NC NC NC A11 WE WP/ACC LB NC A15 A12 A19 CE2r RESET UB A21 A13 A20 RY/BY A18 NC A14 A10 A17 A16 NC DQ6 DQ1 GND Vccf DQ15 DQ13 DQ4 DQ3 DQ9 OE CEf GND DQ7 DQ12 Vccr Vccf DQ10 DQ0 CE1r DQ14 DQ5 NC DQ11 DQ2 DQ8 NC NC NC NC Common Flash Only PSRAM Only

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00A 08/01/02 75V16F64GS16 ISSI LOGIC SYMBOL MCP BLOCK DIAGRAM GND GND Vccf RY/BY 16-MBIT Static PSRAM 64-MBIT Flash Memory DQ15-DQ0 A21-A0 WP/ACC RESET CEf LB UB WE OE CE1r CE2r DQ15-DQ0 A19-A0 VCCr A21-A0 DQ15-DQ0 A21-A0 CEf CE1r CE2r OE WE WP/ACC RESET UB LB DQ15-DQ0 x16 RY/BY

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00A 08/01/02 75V16F64GS16 ISSI FLASH MEMORY BLOCK DIAGRAM STATE CONTROL COMMAND REGISTER RESET WE CE WP/ACC DQ15-DQ0 A21-A0 A21-A0 A21-A0 A21-A0 A21-A0 Lower Bank Address Upper Bank Address Y-Decoder Latches and Control Logic Lower Bank Upper Bank X-Decoder Y-Decoder Latches and Control Logic X-Decoder Status Control DQ15-DQ0 DQ15-DQ0 DQ15-DQ0 OE OE VCC GND

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00A 08/01/02 75V16F64GS16 ISSI Full Standby H H H X X X X High-Z High-Z H X Output Disable(3) H L X H H X X High-Z High-Z H X L H X H H X X High-Z High-Z H X Read from Flash(4) L H X L H X X DOUT DOUT H X Write to Flash L H X H L X X DIN DIN H X Read from PSRAM(5) H L H L H X X DOUT DOUT H X Write to PSRAM L L DIN DIN H L H H L H L High-Z DIN H X L H DIN High-Z Temporary Sector X X X X X X X X X VID X Group Unprotection(6) Flash Hardware X H H X X X X High-Z High-Z L X Reset Boot Block Sector Write X X X X X X X X X X L Protection PSRAM Power Down(8) X X L X X X X X X X X Legend : L = VIL, H = VIH, X = VIL or VIH. See “DC CHARACTERISTICS” for voltage levels. Notes: 1. Other operations not indicated in this table are prohibited. 2. Do not apply CEf = VIL, CE1r = VIL and CE2r = VIH all at once. 3. PSRAM Output Disable condition should not be kept longer than 1 ms. 4. WE can be VIL if OE is VIL, OE at VIH initiates the write operations. 5. PSRAM Byte control at Read operation is not supported. 6. Also used for the extended sector group protections. 7. Protects “outermost” 2 ´ 8 Kbytes (4 words) on both ends of the boot block sectors. 8. Power Down mode can be entered from Standby state and all DQ pins are in High-Z state. DEVICE BUS OPERATIONS OPERATION(1,2) CE CE CE CE CEf CE1 CE1 CE1 CE1 CE1r CE2r OE OE OE OE OE WE WE WE WE WE LB LB LB LB LBs UB UB UB UB UBs DQ7-DQ0 DQ15-DQ8 RESET RESET RESET RESET RESET WP WP WP WP WP/ACC(7)

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00A 08/01/02 75V16F64GS16 ISSI FLEXIBLE SECTOR-ERASE ARCHITECTURE ON FLASH MEMORY Bank Sector Bank Sector Type Address K-Word Address Type Address K-Word Address BankA SA0 000000h BankB SA36 0E8000h BankA SA1 001000h BankB SA37 0F0000h BankA SA2 002000h BankB SA38 0F8000h BankA SA3 003000h BankB SA39 100000h BankA SA4 004000h BankB SA40 108000h BankA SA5 005000h BankB SA41 110000h BankA SA6 006000h BankB SA42 118000h BankA SA7 007000h BankB SA43 120000h BankA SA8 008000h BankB SA44 128000h BankA SA9 010000h BankB SA45 130000h BankA SA10 018000h BankB SA46 138000h BankA SA11 020000h BankB SA47 140000h BankA SA12 028000h BankB SA48 148000h BankA SA13 030000h BankB SA49 150000h BankA SA14 038000h BankB SA50 158000h BankA SA15 040000h BankB SA51 160000h BankA SA16 048000h BankB SA52 168000h BankA SA17 050000h BankB SA53 170000h BankA SA18 058000h BankB SA54 178000h BankA SA19 060000h BankB SA55 180000h BankA SA20 068000h BankB SA56 188000h BankA SA21 070000h BankB SA57 190000h BankA SA22 078000h BankB SA58 198000h BankB SA23 080000h BankB SA59 1A0000h BankB SA24 088000h BankB SA60 1A8000h BankB SA25 090000h BankB SA61 1B0000h BankB SA26 098000h BankB SA62 1B8000h BankB SA27 0A0000h BankB SA63 1C0000h BankB SA28 0A8000h BankB SA64 1C8000h BankB SA29 0B0000h BankB SA65 1D0000h BankB SA30 0B8000h BankB SA66 1D8000h BankB SA31 0C0000h BankB SA67 1E0000h BankB SA32 0C8000h BankB SA68 1E8000h BankB SA33 0D0000h BankB SA69 1F0000h BankB SA34 0D8000h BankB SA70 1F8000h BankB SA35 0E0000h BankC SA71 200000h

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00A 08/01/02 75V16F64GS16 ISSI FLEXIBLE SECTOR-ERASE ARCHITECTURE ON FLASH MEMORY (Continued) Bank Sector Bank Sector Type Address K-Word Address Type Address K-Word Address BankC SA72 208000h BankC SA107 320000h BankC SA73 210000h BankC SA108 328000h BankC SA74 218000h BankC SA109 330000h BankC SA75 220000h BankC SA110 338000h BankC SA76 228000h BankC SA111 340000h BankC SA77 230000h BankC SA112 348000h BankC SA78 238000h BankC SA113 350000h BankC SA79 240000h BankC SA114 358000h BankC SA80 248000h BankC SA115 360000h BankC SA81 250000h BankC SA116 368000h BankC SA82 258000h BankC SA117 370000h BankC SA83 260000h BankC SA118 378000h BankC SA84 268000h BankD SA119 380000h BankC SA85 270000h BankD SA120 388000h BankC SA86 278000h BankD SA121 390000h BankC SA87 280000h BankD SA122 398000h BankC SA88 288000h BankD SA123 3A0000h BankC SA89 290000h BankD SA124 3A8000h BankC SA90 298000h BankD SA125 3B0000h BankC SA91 2A0000h BankD SA126 3B8000h BankC SA92 2A8000h BankD SA127 3C0000h BankC SA93 2B0000h BankD SA128 3C8000h BankC SA94 2B8000h BankD SA129 3D0000h BankC SA95 2C0000h BankD SA130 3D8000h BankC SA96 2C8000h BankD SA131 3E0000h BankC SA97 2D0000h BankD SA132 3E8000h BankC SA98 2D8000h BankD SA133 3F0000h BankC SA99 2E0000h BankD SA134 3F8000h BankC SA100 2E8000h BankD SA135 3F9000h BankC SA101 2F0000h BankD SA136 3FA000h BankC SA102 2F8000h BankD SA137 3FB000h BankC SA103 300000h BankD SA138 3FC000h BankC SA104 308000h BankD SA139 3FD000h BankC SA105 310000h BankD SA140 3FE000h BankC SA106 318000h BankD SA141 3FF000h

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00A 08/01/02 75V16F64GS16 ISSI FLEXBANK TM ARCHITECTURE TABLE Bank 1 Bank 2 Bank Split Volume Combination Volume Combination

8 Mbit

56 Mbit

Bank B, C, D

24 Mbit

40 Mbit

Bank A, C, D Bank A, B, D Bank A, B, C EXAMPLE OF VIRTUAL BANKS COMBINATION TABLE Bank 1 Bank 2 Bank Split Volume Combination Sector Size Volume Combination Sector Size Bank B, C, D 8x4 Kword 15x32 Kword 111x32 Kword

16 Mbit

Bank A,D 16x4 Kword

48 Mbit

Bank B,C 96x32 Kword 30x32 Kword Bank A, C, D 16x4 Kword 78x32 Kword

32 Mbit

Bank A,B 8x4 Kword Bank C,D 8x4 Kword 63x32 Kword 63x32 Kword Notes: 1) When multiple sector erase over several banks is operated, the system cannot read out of the bank to which a sector being erased belongs. For example, if erasing is taking place at both Bank A and Bank B, neither Bank A nor Bank B is read out. They would output the sequence flag once they were selected. Meanwhile the system would get to read from either Bank C or Bank D.

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00A 08/01/02 75V16F64GS16 ISSI SIMULTANEOUS OPERATION TABLE Case Bank 1 Status Bank 2 Status Read Mode Read Mode Read Mode Autoselect Mode Read Mode Program Mode Read Mode Erase Mode (1) Autoselect Mode Read Mode Program Mode Read Mode Erase Mode (1) Read Mode Note: 1) By writing erase suspend command on the bank address of sector being erased, the erase operation gets suspended so that it enables reading from or programming the remaining sectors. 2) Bank 1 and Bank 2 are divided for the sake of convenience at Simultaneous Operation. Actually, the Bank consists of 4 banks, Bank A, Bank B, Bank C and Bank D. Bank Address (BA) means to specify each of the Banks.

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00A 08/01/02 75V16F64GS16 ISSI SECTOR ADDRESS TABLE Bank Address Sector Address Address Range Bank Sector A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 Word Mode Bank A SA0 000000h to 000FFFh Bank A SA1 001000h to 001FFFh Bank A SA2 002000h to 002FFFh Bank A SA3 003000h to 003FFFh Bank A SA4 004000h to 004FFFh Bank A SA5 005000h to 005FFFh Bank A SA6 006000h to 006FFFh Bank A SA7 007000h to 007FFFh Bank A SA8 X X X 008000h to 00FFFFh Bank A SA9 X X X 010000h to 017FFFh Bank A SA10 X X X 018000h to 01FFFFh Bank A SA11 X X X 020000h to 027FFFh Bank A SA12 X X X 028000h to 02FFFFh Bank A SA13 X X X 030000h to 037FFFh Bank A SA14 X X X 038000h to 03FFFFh Bank A SA15 X X X 040000h to 047FFFh Bank A SA16 X X X 048000h to 04FFFFh Bank A SA17 X X X 050000h to 057FFFh Bank A SA18 X X X 058000h to 05FFFFh Bank A SA19 X X X 060000h to 067FFFh Bank A SA20 X X X 068000h to 06FFFFh Bank A SA21 X X X 070000h to 077FFFh Bank A SA22 X X X 078000h to 07FFFFh Bank B SA23 X X X 080000h to 087FFFh Bank B SA24 X X X 088000h to 08FFFFh Bank B SA25 X X X 090000h to 097FFFh Bank B SA26 X X X 098000h to 09FFFFh Bank B SA27 X X X 0A0000h to 0A7FFFh Bank B SA28 X X X 0A8000h to 0AFFFFh Bank B SA29 X X X 0B0000h to 0B7FFFh Bank B SA30 X X X 0B8000h to 0BFFFFh Bank B SA31 X X X 0C0000h to 0C7FFFh Bank B SA32 X X X 0C8000h to 0CFFFFh

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00A 08/01/02 75V16F64GS16 ISSI SECTOR ADDRESS TABLE (Continued) Bank Address Sector Address Address Range Bank Sector A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 Word Mode Bank B SA33 X X X 0D0000h to 0D7FFFh Bank B SA34 X X X 0D8000h to 0DFFFFh Bank B SA35 X X X 0E0000h to 0E7FFFh Bank B SA36 X X X 0E8000h to 0EFFFFh Bank B SA37 X X X 0F0000h to 0F7FFFh Bank B SA38 X X X 0F8000h to 0FFFFFh Bank B SA39 X X X 100000h to 107FFFh Bank B SA40 X X X 108000h to 10FFFFh Bank B SA41 X X X 110000h to 117FFFh Bank B SA42 X X X 118000h to 11FFFFh Bank B SA43 X X X 120000h to 127FFFh Bank B SA44 X X X 128000h to 12FFFFh Bank B SA45 X X X 130000h to 137FFFh Bank B SA46 X X X 138000h to 13FFFFh Bank B SA47 X X X 140000h to 147FFFh Bank B SA48 X X X 148000h to 14FFFFh Bank B SA49 X X X 150000h to 157FFFh Bank B SA50 X X X 158000h to 15FFFFh Bank B SA51 X X X 160000h to 167FFFh Bank B SA52 X X X 168000h to 16FFFFh Bank B SA53 X X X 170000h to 177FFFh Bank B SA54 X X X 178000h to 17FFFFh Bank B SA55 X X X 180000h to 187FFFh Bank B SA56 X X X 188000h to 18FFFFh Bank B SA57 X X X 190000h to 197FFFh Bank B SA58 X X X 198000h to 19FFFFh Bank B SA59 X X X 1A0000h to 1A7FFFh Bank B SA60 X X X 1A8000h to 1AFFFFh Bank B SA61 X X X 1B0000h to 1B7FFFh Bank B SA62 X X X 1B8000h to 1BFFFFh Bank B SA63 X X X 1C0000h to 1C7FFFh Bank B SA64 X X X 1C8000h to 1CFFFFh Bank B SA65 X X X 1D0000h to 1D7FFFh

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00A 08/01/02 75V16F64GS16 ISSI SECTOR ADDRESS TABLE (Continued) Bank Address Sector Address Address Range Bank Sector A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 Word Mode Bank B SA66 X X X 1D8000h to 1DFFFFh Bank B SA67 X X X 1E0000h to 1E7FFFh Bank B SA68 X X X 1E8000h to 1EFFFFh Bank B SA69 X X X 1F0000h to 1F7FFFh Bank B SA70 X X X 1F8000h to 1FFFFFh Bank C SA71 X X X 200000h to 207FFFh Bank C SA72 X X X 208000h to 20FFFFh Bank C SA73 X X X 210000h to 217FFFh Bank C SA74 X X X 218000h to 21FFFFh Bank C SA75 X X X 220000h to 227FFFh Bank C SA76 X X X 228000h to 22FFFFh Bank C SA77 X X X 230000h to 237FFFh Bank C SA78 X X X 238000h to 23FFFFh Bank C SA79 X X X 240000h to 247FFFh Bank C SA80 X X X 248000h to 24FFFFh Bank C SA81 X X X 250000h to 257FFFh Bank C SA82 X X X 258000h to 25FFFFh Bank C SA83 X X X 260000h to 267FFFh Bank C SA84 X X X 268000h to 26FFFFh Bank C SA85 X X X 270000h to 277FFFh Bank C SA86 X X X 278000h to 27FFFFh Bank C SA87 X X X 280000h to 287FFFh Bank C SA88 X X X 288000h to 28FFFFh Bank C SA89 X X X 290000h to 297FFFh Bank C SA90 X X X 298000h to 29FFFFh Bank C SA91 X X X 2A0000h to 2A7FFFh Bank C SA92 X X X 2A8000h to 2AFFFFh Bank C SA93 X X X 2B0000h to 2B7FFFh Bank C SA94 X X X 2B8000h to 2BFFFFh Bank C SA95 X X X 2C0000h to 2C7FFFh Bank C SA96 X X X 2C8000h to 2CFFFFh Bank C SA97 X X X 2D0000h to 2D7FFFh Bank C SA98 X X X 2D8000h to 2DFFFFh Bank C SA99 X X X 2E0000h to 2E7FFFh

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00A 08/01/02 75V16F64GS16 ISSI SECTOR ADDRESS TABLE (Continued) Bank Address Sector Address Address Range Bank Sector A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 Word Mode Bank C SA100 X X X 2E8000h to 2EFFFFh Bank C SA101 X X X 2F0000h to 2F7FFFh Bank C SA102 X X X 2F8000h to 2FFFFFh Bank C SA103 X X X 300000h to 307FFFh Bank C SA104 X X X 308000h to 30FFFFh Bank C SA105 X X X 310000h to 317FFFh Bank C SA106 X X X 318000h to 31FFFFh Bank C SA107 X X X 320000h to 327FFFh Bank C SA108 X X X 328000h to 32FFFFh Bank C SA109 X X X 330000h to 337FFFh Bank C SA110 X X X 338000h to 33FFFFh Bank C SA111 X X X 340000h to 347FFFh Bank C SA112 X X X 348000h to 34FFFFh Bank C SA113 X X X 350000h to 357FFFh Bank C SA114 X X X 358000h to 35FFFFh Bank C SA115 X X X 360000h to 367FFFh Bank C SA116 X X X 368000h to 36FFFFh Bank C SA117 X X X 370000h to 377FFFh Bank C SA118 X X X 378000h to 37FFFFh Bank D SA119 X X X 380000h to 387FFFh Bank D SA120 X X X 388000h to 38FFFFh Bank D SA121 X X X 390000h to 397FFFh Bank D SA122 X X X 398000h to 39FFFFh Bank D SA123 X X X 3A0000h to 3A7FFFh Bank D SA124 X X X 3A8000h to 3AFFFFh Bank D SA125 X X X 3B0000h to 3B7FFFh Bank D SA126 X X X 3B8000h to 3BFFFFh Bank D SA127 X X X 3C0000h to 3C7FFFh Bank D SA128 X X X 3C8000h to 3CFFFFh Bank D SA129 X X X 3D0000h to 3D7FFFh Bank D SA130 X X X 3D8000h to 3DFFFFh Bank D SA131 X X X 3E0000h to 3E7FFFh Bank D SA132 X X X 3E8000h to 3EFFFFh Bank D SA133 X X X 3F0000h to 3F7FFFh Bank D SA134 3F8000h to 3F8FFFh Bank D SA135 3F9000h to 3F9FFFh Bank D SA136 3FA000h to 3FAFFFh Bank D SA137 3FB000h to 3FBFFFh Bank D SA138 3FC000h to 3FCFFFh Bank D SA139 3FD000h to 3FDFFFh Bank D SA140 3FE000h to 3FEFFFh Bank D SA141 3FF000h to 3FFFFFh

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00A 08/01/02 75V16F64GS16 ISSI SECTOR ADDRESS GROUP TABLE Sector A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 Sectors SGA0 SA0 SGA1 SA1 SGA2 SA2 SGA3 SA3 SGA4 SA4 SGA5 SA5 SGA6 SA6 SGA7 SA7 SGA8 X X X SA8 to SA10 SGA9 X X X X X SA11 to SA14 SGA10 X X X X X SA15 to SA18 SGA11 X X X X X SA19 to SA22 SGA12 X X X X X SA23 to SA26 SGA13 X X X X X SA27 to SA30 SGA14 X X X X X SA31 to SA34 SGA15 X X X X X SA35 to SA38 SGA16 X X X X X SA39 to SA42 SGA17 X X X X X SA43 to SA46 SGA18 X X X X X SA47 to SA50 SGA19 X X X X X SA51 to SA54 SGA20 X X X X X SA55 to SA58 SGA21 X X X X X SA59 to SA62 SGA22 X X X X X SA63 to SA66 SGA23 X X X X X SA67 to SA70 SGA24 X X X X X SA71 to SA74 SGA25 X X X X X SA75 to SA78 SGA26 X X X X X SA79 to SA82 SGA27 X X X X X SA83 to SA86 SGA28 X X X X X SA87 to SA90 SGA29 X X X X X SA91 to SA94 SGA30 X X X X X SA95 to SA98 SGA31 X X X X X SA99 to SA102 SGA32 X X X X X SA103 to SA106

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00A 08/01/02 75V16F64GS16 ISSI FLASH MEMORY AUTOSELECT CODES TABLE Type A21 to A12 Code (HEX) Manufacture's Code BA L L L L L 04h Device Code BA L L L L H 227Eh Extended Device BA L H H H L 2202h Code(2) BA L H H H H 2201h Sector Group Sector Group L L L H L 01h(1) Protection Address Legend: L = VIL, H = VIH. See “n DC CHARACTERISTICS” for voltage levels. Notes: 1. Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. 2. A read cycle at address (BA) 01h outputs device code. When 227Eh was output, this indicates that there will require two additional codes, called Extended Device Codes. Therefore the system may continue reading out these Extended Device Codes at the address of (BA) 0Eh, as well as at (BA) 0Fh. SECTOR ADDRESS GROUP TABLE (Continued) Sector A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 Sectors SGA33 X X X X X SA107 to SA110 SGA34 X X X X X SA111 to SA114 SGA35 X X X X X SA115 to SA118 SGA36 X X X X X SA119 to SA122 SGA37 X X X X X SA123 to SA126 SGA38 X X X X X SA127 to SA130 SGA39 X X X SA131 to SA133 SGA40 SA134 SGA41 SA135 SGA42 SA136 SGA43 SA137 SGA44 SA138 SGA45 SA139 SGA46 SA140 SGA47 SA141

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00A 08/01/02 75V16F64GS16 ISSI FLASH MEMORY COMMAND DEFINITIONS Notes: 1. Both Read/Reset commands are functionally equivalent, resetting the device to the read mode. 2. This command is valid during Fast Mode. 3. This command is valid while RESET = VID 4. The valid address is A6 to A0. 5. This command is valid during Hi-ROM mode. 6. The data “00h” is also acceptable. Command Sequence Bus Write Cycle Req'd First Bus Second Bus Third Bus Fourth Bus Fifth Bus Sixth Bus Cycle Write Cycle Write Cycle Read/Write Cycle Cycle Data Read / Reset (1) Flash Program (2) Erase Resume Data Data Addr. Addr. Addr. Addr. Data Addr. Data Addr. Data Read / Reset (1) SPA 60h SPA SPA 55h F0h AAh 30h RA 55h AAh F0h RD SD 40h 88h BA XXXh 30h A0h 90h 98h 55h Set to Fast Mode (2) Autoselect Program Program Suspend Program Resume Sector Erase Erase Suspend Query (4) Hi-ROM Entry 90h PA 55h B0h PD A0h Extended Sector Group Protection (3) Reset from Flash Mode (2) Hi-ROM Exit (5) 555h AAh 2AAh 55h 555h A0h 00h Hi-ROM Program (5) Chip Erase XXXh 555h 555h 555h BA BA 555h 555h 555h 555h (BA) 55h AAh AAh 2AAh 555h 2AAh (BA) 555h 2AAh 555h AAh AAh B0h 2AAh 2AAh 55h 55h 555h 555h 80h 80h 555h 555h AAh AAh 2AAh 2AAh 55h 55h 55h 555h SA 10h 30h BA B0h 60h 555h AAh 2AAh 55h 555h 20h XXXh PA PD BA XXXh (6) F0H 2AAh 2AAh 55h 555h 555h (HRBA) 90h XXXh PD (HRA) PA

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00A 08/01/02 75V16F64GS16 ISSI FLASH MEMORY COMMAND DEFINITIONS (Continued) PD = Data to be programmed at location PA. Data is latched on the rising edge of write pulse. SPA = Sector group address to be protected. Set sector group address and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0). SD = Sector group protection verify data. Output 01h at protected sector group addresses and output 00h at unprotected sector group addresses. HRA = Address of the Hi-ROM area : 000000h to 00007Fh HRBA = Bank Address of the Hi-ROM area (A21 = A20 = A19 = VIL) The system should generate the following address patterns : 555h or 2AAh to addresses A10 to A0 Both Read/Reset commands are functionally equivalent, resetting the device to the read mode. Command combinations not described in “Flash Memory Command Definitions” are illegal. Notes: Address bits A21 to A11 = X = “H” or “L” for all address commands except or Program Address (PA), Sector Address (SA) , and Bank Address (BA) , and Sector Group Address (SPA) . Bus operations are defined in "DEVICE BUS OPERATIONS”. RA = Address of the memory location to be read PA = Address of the memory location to be programmed Addresses are latched on the falling edge of the write pulse. SA = Address of the sector to be erased. The combination of A21, A20, A19, A18, A17, A16, A15, A14, A13, and A12 will uniquely select any sector. BA = Bank Address (A21, A20, A19) RD = Data read from location RA during read operation.

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00A 08/01/02 75V16F64GS16 ISSI ABSOLUTE MAXIMUM RATINGS Rating Symbol Parameter Min. Max. Unit Tstg Storage Temperature –55 +125 TA Ambient Temperature with Power Applied –30 +85 VIN Voltage with Respect to Ground All Pins(1,2) –0.3 VCCf + 0.3 V VOUT Voltage with Respect to Ground All Pins(1,2) –0.3 VCCr + 0.3 V VCCf VCCf Supply(1) –0.2 +3.6 V VCCr VCCr Supply(1,3) -0.2 +3.6 V VIN RESET(1,3) -0.5 +13.0 V VACC WP/ACC(1,4) –0.5 +10.5 V Notes: 1. Voltage is defined on the basis of GND = GND = 0 V. 2. Minimum DC voltage on input or I/O pins is -0.3 V. During voltage transitions, input or I/O pins may undershoot During voltage transitions, input or I/O pins may overshoot to VCCf + 1.0 V or VCCr + 1.0 V for periods of up to 5 ns. 3. Minimum DC input voltage on RESET pin is -0.5 V. During voltage transitions, RESET pin may undershoot GND to -2.0 V for periods of up to 20 ns. Voltage difference between input and supply voltage (VIN-VCCf or VCCr) does not exceed 9.0 V. Maximum DC input voltage on RESET pin is +13.0 V that may overshoot to +14.0 V for periods of up to 20 ns. 4. Minimum DC input voltage on WP/ACC pin is -0.5 V. During voltage transitions, WP/ACC pin may undershoot GND to -2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is +10.5 V which may overshoot to +10.5 V for periods of up to 20 ns, when VCCf is applied. 5. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED OPERATING CONDITIONS Rating Symbol Parameter Min. Max. Unit TA Ambient Temperature –30 +85 VCCf VCCf Supply Voltages –2.7 +3.1 V VCCr VCCr Supply Voltages –2.7 +3.1 V Note: Voltage is defined on the basis of GND = GND = 0 V.

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00A 08/01/02 75V16F64GS16 ISSI DC CHARACTERISTICS Symbol Parameter Test Conditions Min. Typ. Max. Unit ILI Input Leakage VIN=GND to VCCf, VCCr -1.0 +1.0 µA ILO Output Leakage VOUT=GND to VCCf, VCCr -1.0 +1.0 µA ILIT RESET Inputs VCCf=VCCf max., µA Leakage Current RESET = 12.5V ICC1f FLASH Vcc (1) CEf=VIL, OE=VIH tCycle = 5Mhz mA Active Current (Read) tCycle = 1Mhz mA ICC2f FLASH Vcc Active(2) CEf=VIL, mA Current(Program/Erase) OE=VIH ICC3f FLASH Vcc Active(5) CEf=VIL, mA Current OE=VIH (Read-While-Program) ICC4f FLASH Vcc Active(5) CEf=VIL, mA Current OE=VIH (Read-While-Erase) ICC5f FLASH Vcc Active CEf=VIL, mA Current OE=VIH (Erase-Suspend-Program) IACC WP/ACC Acceleration VCCf = Vcc max, mA Program Current WP/ACC = VACC max ICC1r PSRAM Vcc Active VCCr = Vccr max, trc / twc = min mA Current CE1r=VIL, CE2r=VIH, VIN=VIH or VIL, trc / twc = 1 µs 2.5 3.0 mA IOUT=0 mA ISB1f FLASH Vcc VCCf = Vccf max, CEf= VCCf + 0.3V, µA Standby Current RESET = VCCf + 0.3V, WP/ACC = VCCf + 0.3V ISB2f FLASH Vcc VCCf = Vccf max, RESET= GND + 0.3V, µA Standby Current WP/ACC = VCCf + 0.3V (RESET) ISB3f FLASH Vcc(3) VCCf = Vcc max., CEf, = GND + 0.3V, µA Current RESET = VCCf + 0.3V, (Automatic Sleep Mode) WP/ACC = VCCf + 0.3V, VIN = VCCf + 0.3V OR GND + 0.3V ISBr PSRAM Vcc Standby VCCr = Vccr max, CE1r = CE2R = VIN, 0.5 mA Current VIN=VIH or VIL, IOUT=0 mA ISB1r PSRAM Vcc Standby VCCr = Vccr max, CE1r ≥ VCCr -0.2V, µA Current CE2r ≥ VCCr -0.2V, VIN ≤ 0.2 V or VIN ≥ VCCr -0.2V IOUT=0 mA ISB2r PSRAM Vcc Standby VCCr = Vccr max, CE1r ≥ VCCr -0.2V, mA Current(6) CE2r ≥ VCCr -0.2V, VIN Cycle time = tRC min, IOUT = 0 mA

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00A 08/01/02 75V16F64GS16 ISSI DC CHARACTERISTICS (Continued) Symbol Parameter Test Conditions Min. Max. Unit IPDr PSRAM VCC Power VCCr = VCCr max., µA Down Current VIN ≥ VCCf - 0.2 V OR VIN ≤ 0.2 V CE2r ≤ 0.2 V, IOUT = 0 mA VIL Input Low Level -0.3 0.5 V VIH Input High Level (Flash) 2.0 VCCf + 0.3 V VIH Input High Level (PSRAM) 2.2 VCCr + 0.3 V VID Voltage for Autoselect 11.5 12.5 V and Sector Protection (RESET)(4) VACC Voltage for WP/ACC 8.5 9.5 V Sector Protection/Unprotection and Program Acceleration (4) VOL Output Low Level VCCr = VCCr min., VCCS=VCCS min. 0.4 V (PSRAM) IOL = 1.0 mA VOH Output High Level VCCr = VCCr min., VCCS=VCCS min. 2.2 V (PSRAM) IOH = -0.5 mA VOL Output Low Level VCCf = VCCf min., VCCS=VCCS min. 0.45 V (Flash) IOL = 4.0 mA VOH Output High Level VCCf = VCCf min., VCCS=VCCS min. VCCf - 0.4 V (Flash) IOH = -0.1 mA VLKO Flash Low Vccf 2.3 2.5 V Lock-Out Voltage Notes: 1. ICC current listed includes both the DC operating current and the frequency dependent component. 2. ICC active while Embedded Algorithm (program or erase) is in progress. 3. Automatic sleep mode enables the low power mode when address remains stable for 150 ns. 4. Applicable for only VCCf applying. 5. Embedded Algorithm (program or erase) is in progress. (@5 MHz) 6. ISB2 r depends on VIN cycle time. Please refer to “APPENDIX A”.

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00A 08/01/02 75V16F64GS16 ISSI TIMING DIAGRAM FOR ALTERNATING PSRAM TO FLASH AC CHARACTERISTICS - CE CE CE CE CE TIMING Parameter Symbol Condition Min Max Unit CEf Recover Time tCCR ns CEf Hold Time tCHOLD ns CE1r High to WE Invalid time for tCHWX ns Standby Entry CEf CE1r CE2r tCCR tCCR tCCR tCCR tCHWX tCHOLD WE

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00A 08/01/02 75V16F64GS16 ISSI JEDEC Standard Parameter Symbol Symbol Condition Min Max Unit Read Cycle Time tAVAV tRC ns Address to Output Delay tAVQV tACC CEf = VIL, OE = VIL ns Chip Enable to Output Delay tELQV tCE OE = VIL ns Output Enable to Output Delay tGLQV tOE ns Chip Enable to Output High-Z tEHQZ tDF ns Output Enable to Output High-Z tGHQZ tDF ns Output Hold Time From Addresses, tAXQX tOH ns CEf or OE, Whichever Occures First RESET Pin Low to Read Mode tREADY µs FLASH READ ONLY OPERATIONS CHARACTERISTICS Test Conditions: Output Load : 1 TTL gate and 30 pF Input rise and fall times : 5 ns Input pulse levels : 0.0 V or VCCf Timing measurement reference level Input : VCCf/2 Output : VCCf/2

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00A 08/01/02 75V16F64GS16 ISSI FLASH READ CYCLE Address DQ CEf OE WE Address Stable Output valid High-Z High-Z tOEH tRC tOE tDF tCE tACC

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00A 08/01/02 75V16F64GS16 ISSI FLASH HARDWARE RESET RESET RESET RESET RESET / READ OPERATION TIMING DIAGRAM Address DQ CEf RESET Address Stable Output valid High-Z tRC tACC tRH tCE tRH tRP tOH

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00A 08/01/02 75V16F64GS16 ISSI WRITE/ERASE/PROGRAM OPERATIONS JEDEC Standard Parameter Symbol Symbol Min Typ Max Unit Write Cycle Time tAVAV tWC ns Address Setup Time tAVWL tAS ns Address Setup Time to OE Low tASO ns During Toggle Bit Polling Address Hold Time tWLAX tAH ns Address Hold Time from CE or tAHT ns OE High During Toggle Bit Polling Data Setup Time tDVWH tDS ns Data Hold Time tWHDX tDH ns Output Enable Hold Time Read tOEH ns Output Enable Hold Time tOEH ns Toggle and Data Polling CE High During Toggle Bit Polling tCEPH ns OE High During Toggle Bit Polling tOEPH ns Read Recover Time Before Write (OE to CE) tGHWL tGHWL ns Read Recover Time Before Write (OE to WE) tGHEL tGHEL ns WE Setup Time (CEf to WE) tELWL tWS ns CE Setup Time (WE to CE) tWLEL tCS ns WE Hold Time (CE to WE) tWHEH tWH ns CE Hold Time (WE to CE) tEHWH tCH ns Write Pulse Width tWLWH tWPH ns CEf Pulse Width tELEH tCP ns Write Pulse Width High tWHWL tWPH ns CE Pulse Width High tEHEL tCPH ns Programming Operation tWHWH1 tWHWH1 µs Sector Erase Operation (1) tWHWH2 tWHWH2 0.2 s VCC Setup Time tVCS µs Rise Time to VID (2) tVIDR 500 ns Rise Time to VID (3) tVACCR 500 ns Voltage Transition Time (2) tVLHT µs Write Pulse width (2) tWPP 100 µs

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00A 08/01/02 75V16F64GS16 ISSI WRITE/ERASE/PROGRAM OPERATIONS (Continued) JEDEC Standard Parameter Symbol Symbol Min Typ Max Unit OE Setup Time to WE Active (2) tOESP µs CE Setup Time to WE Active (2) tCSP µs Recover Time from RY/BY tRB ns RESET Pulse Width tRP 500 ns RESET High Level Period Before Read tRH 200 ns Program/Erase Valid to RY/BY Delay tBUSY ns Delay Time from Embedded Output Enable tEOE ns Erase Time-Out Time tTOW µs Erase Suspend Transition Time tSPD µs Notes: 1. Does not include preprogramming time. 2. For Sector Group Protection operation. 3. For Accelerated Program operation.

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00A 08/01/02 75V16F64GS16 ISSI FLASH WRITE CYCLE (WE CONTROL) Notes: 1. PA is address of the memory location to be programmed. 2. PD is data to be programmed at byte address. 3. DQ7 is the output of the complement of the data written to the device. 4. DOUT is the output of the data written to the device. 5. Figure indicates last two bus cycles out of four bus cycle sequence. Address DQ CEf OE WE A0h DQ7 Dout PA 555h PA Data Polling PD Dout tAS 3rd Bus Cycle tAH tRC tOE tCE tOH tDF tDS tDH tWHWH1 tCS tCH tGHWL tWP tWPH tWC

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00A 08/01/02 75V16F64GS16 ISSI FLASH WRITE CYCLE (CEf CONTROL) Notes: 1. PA is address of the memory location to be programmed. 2. PD is data to be programmed at byte address. 3. DQ7 is the output of the complement of the data written to the device. 4. DOUT is the output of the data written to the device. 5. Figure indicates last two bus cycles out of four bus cycle sequence. Address DQ CEf OE WE AOh DQ7 Dout PA 555h PA Data Polling PD tAS 3rd Bus Cycle tAH tWC tDS tDH tWHWH1 tWS tWH tGHEL tCP tCPH

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00A 08/01/02 75V16F64GS16 ISSI FLASH AC WAVEFORMS CHIP/SECTOR ERASE OPERATIONS Notes: 1. SA is the sector address for Sector Erase. Address = 555h for Chip Erase. Address DQ CEf OE WE 55h 10h/ 30h Vccf 55h AAh 80h AAh 555h 2AAh 555h 555h 2AAh SA(1) 30h for Sector Erase tWC tAS tAH tSC tCH tWP tWPH tVCS tGHWL tDS tDH

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00A 08/01/02 75V16F64GS16 ISSI FLASH AC WAVEFORMS FOR DATA DATA DATA DATA DATA POLLING DURING EMBEDDED ALGORITHM OPERATIONS Notes: 1. DQ7 = Valid Data (the device has completed the Embedded operation.) Data In DQ0/DQ6 CEf OE WE RY/BY DQ Data In DQ7 DQ0 to DQ6 = Output Flag DQ0 to DQ6 Valid Data DQ7 = Valid Data tDF tBUSY tWHWH1 or 2 tOE tEOE tOEH tCE tCH High - Z High - Z (1)

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00A 08/01/02 75V16F64GS16 ISSI FLASH AC WAVEFORMS FOR TOGGLE BIT DURING EMBEDDED ALGORITHM OPERATIONS Notes: 1. DQ6 stops toggling (the device has completed the Embedded operation). Toggle Toggle Toggle Toggle Output Data Data Data Data Valid Data ADDRESS DQ6/DQ2 CEf OE WE tDH tBUSY tOEH tOE RY/BY tCE tOEH tOEPH tCEPH tAHT tASO tAHT tAS (1)

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00A 08/01/02 75V16F64GS16 ISSI FLASH BACK-to-BACK READ/WRITE TIMING DIAGRAM Note: 1. This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2. BA1: Address of Bank 1; BA2: Address of Bank 2. ADDRESS DQ CEf OE WE BA1 BA1 BA1 tRC tAS tAH tACC tCE BA2 (555h) BA2 (PA) BA2 (PA) Read Command Read Command Read Read Valid Valid Valid Valid Valid Output Input Output Input Output Status tWC tRC tWC tRC tRC tDS tDH tDF tDF tOEH (PD) tGHWL tWP (A0h) tOE tCEPH tAHT tAS

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00A 08/01/02 75V16F64GS16 ISSI FLASH RY/BY BY BY BY BY TIMING DIAGRAM DURING WRITE/ERASE OPERATIONS FLASH RESET, RESET, RESET, RESET, RESET, RY/BY BY BY BY BY TIMING DIAGRAM WE CEf RY/BY The rising edge of the last write pulse Entire programming or erase operations tBUSY WE RESET RY/BY tREADY tRP tRB

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00A 08/01/02 75V16F64GS16 ISSI FLASH EXTENDED SECTOR GROUP PROTECTION Notes: 1. SPAX : Sector Group Address to be protected, SPAY : Next Group Sector Address to be protected, TIME-OUT: Time-Out window = 250 µs (Min) RESET Address A6, A3 A2, A0 CEf OE WE Data Vccf 60h 60h 40h 01h 60h SPAX SPAY SPAX TIME-OUT tVCS tVIDR tVLHT tWC tWP tOE tWC

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00A 08/01/02 75V16F64GS16 ISSI PSRAM READ OPERATIONS Value Parameter Symbol Min. Max. Unit Read Cycle Time tRC ns Chip Enable Access Time(1,3) tCE ns Output Enable Access Time(1) tOE ns Chip Enable Access Time(1,4) tAA ns Output Data Hold Time(1) tOH ns CE1r Low to Output Low-Z(2) tCLZ ns OE Low to Output Low-Z(2) tOLZ ns CE1r High to Output High-Z(2) tCHZ ns OE High to Output High-Z(2) tOHZ ns Address Setup Time to CE1r Low(5) tASC ns Address Setup Time to OE(3,6) tASO ns Address Setup Time to OE(7) tASO(ABS) ns Address Invalid Time(4) tAX ns CE1r Low to Address Hold Time(4) tCLAH ns OE Low to Address Hold Time(4,8) tOLAH ns CE1r High to Address Hold Time tCHAH ns OE High to Address Hold Time tOHAH ns CE1r Low to OE Low DelayTime(4,6,8,9) tCLOL 1000 ns OE Low to CE1r High DelayTime(8) tOLCH ns CE1r High Pulse Width tCP ns OE High Pulse Width(6,8,9) tOP 1000 ns OE High Pulse Width(7) tOP(ABS) ns Notes: 1. The output load is 30 pF. 2. The output load is 5 pF. 3. The tCE is applicable if OE is brought to Low before CE1r goes Low and is also applicable if actual value of both or either tASO or tCLOL is shorter than specified value. 4. Applicable only to A0 and A1 when both CE1r and OE are kept at Low for the address access. 5. Applicable if OE is brought to Low before CE1r goes Low. 6. The tASO, tCLOL (Min) and top (Min) are reference values when the access time is determined by tOE. If actual value of each parameter is shorter than specified minimum value, tOE becomes longer by the amount of subtracting actual value from specified minimum value. For example, if actual tASO, tASO (actual) , is shorter than specified minimum value, tASO (Min) , during OE control access (i.e., CE1r stays Low) , the tOE becomes tOE (Max) + tASO (Min) - tASO (actual) . 7. The tASO[ABS] and tOP[ABS] are the absolute minimum values during OE control access. 8. If actual value of either tCLOL or tOP is shorter than specified minimum value, both tOLAH and tOLCH become tRC (Min) - tCLOL (actual) or tRC (Min) - tOP (actual) . 9. Maximum value is applicable if CE1r is kept at Low.

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00A 08/01/02 75V16F64GS16 ISSI PSRAM WRTE OPERATIONS Value Parameter Symbol Min. Max. Unit Write Cycle Time(1) tWC ns Address Setup Time(2) tAS ns Address Setup Timev tAH ns CE1r Write Setup Time tCS 1000 ns CE1r Write Hold Time tCH 1000 ns WE Setup Time tWS ns WE Hold Time tWH ns LB adnd UB Setup Time tBS ns LB adnd UB Hold Time tBH ns OE Setup Time(3) tOES 1000 ns OE Hold Time(3,4) tOEH 1000 ns OE Hold Time(5) tOEH(ABS) ns OE High to CE1r Low Setup Time(6) tOHCL ns OE High to Address Hold Time(7) tOHAH ns CE1r Write Pulse Width(1,8) tCW ns WE Write Pulse Width(1,8) tWP ns CE1r Write Recovery Time(1,9) tWRC ns WE Write Recovery Time(1,3,9) tWR 1000 ns Data Setup Time tDS ns Data Hold Time tDH ns CE1r High Pulse Width(9) tCD ns Notes: 1. Minimum value must be equal or greater than the sum of actual tCW (or tWP) and tWRC (or tWR) . 2. New write address is valid from either CE1r or WE that is brought to High. 3. Maximum value is applicable if CE1r is kept at Low and both WE and OE are kept at High. 4. The tOEH is specified from end of tWC (Min) , and is a reference value when access time is determined by tOE. If actual value is shorter than specified minimum value, tOE becomes longer by the amount of subtracting actual value from specified minimum value. 5. The tOEH[ABS] is the absolute minimum value if write cycle is terminated by WE and CE1r stay Low. 6. tOHCL (Min) must be satisfied if read operation is not performed prior to write operation. In case OE is disabled after tOHCL (Min) , WE Low must be asserted after tRC (Min) from CE1r Low. In other words, read operation is initiated if tOHCL (Min) is not satisfied. 7. Applicable if CE1r stays Low after read operation. 8. tCW and tWP are applicable if write operation is initiated by CE1r and WE, respectively. 9. tWRC and tWR are applicable if write operation is terminated by CE1r and WE, respectively. The tWR (Min) can be ignored if CE1r is brought to High together or after WE is brought to High. In such a case, the tCP (Min) must be satisfied.

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00A 08/01/02 75V16F64GS16 ISSI PSRAM POWER DOWN PARAMETER Value Parameter Symbol Min. Max. Unit CE2r Low Setup Time for Power down Entry tCSP ns CE2r Low Setup Time after Power down Entry tC2LP 100 ns CE1r High Hold Time Following CE2r High after Power down Exit tCHH 350 µs CE1r High Setup Time Following CE2r High after Power down Exit tCHS ns PSRAM OTHER TIMING PARAMETERS Value Parameter Symbol Min. Max. Unit CE1r High to OE Invalid for Standby Entry tCHOX ns CE1r High to WE Invalid for Standby Entry(1) tCHWX ns CE2r Low Hold Time after Power-up(2) tC2LH µs CE2r High Hold Time after Power-up(3) tC2HL µs CE1r High Hold Time Following CE2r High after Power-up(2) tCHH 350 µs Input Transition Time(4) tT ns Notes: 1. Unintended data may be written into any address location if tCHWX is not satisfied. 2. Must satisfy tCHH (Min) after tC2LH (Min) . 3. Requires Power Down mode entry and exit after tC2HL. 4. Input Transition Time (tT) at AC testing is 5 ns as shown below. If actual tT is longer than 5 ns, it may violate some timing parameters of AC specification. PSRAM AC TEST CONDITIONS Parameter Symbol Conditon Value Unit Input HIgh Level VIH VCCr = 2.7V to 3.1V 2.3 V Input Low Level VIL VCCr = 2.7V to 3.1V 0.4 V Input Timing Measurement Level VREF VCCr = 2.7V to 3.1V 1.3 V Input Transition Time tT Between VIL and VIH ns

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00A 08/01/02 75V16F64GS16 ISSI PSRAM READ TIMING (OE Control Access) PSRAM READ TIMING (CE1r Control Access) Address Valid Data Input CE1r OE DQ (Input) Address Valid tRC tCLOL tCE tRC tOHAH tOE Valid Data Input tOE tOP tOLCH tOH tOHZ tOLZ tOHZ tOH tOLZ tASO tOHAH tASO Address Valid Address Valid Data Input CE1r OE DQ (Input) Address Valid tRC tCE tRC tcHAH Valid Data Input tOH tCHZ tCLZ tCHZ tOH tCLZ tOHAH tASC Address Valid tCE tASC tCP Note: CE2r and WE must be High during read cycle. Note: CE2r and WE must be High during read cycle.

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00A 08/01/02 75V16F64GS16 ISSI PSRAM READ TIMING (Address Access after OE Control Access) PSRAM READ TIMING (Address Access after CE1r Control Access) Address (A19-A2) CE1r OE DQ (Input) Address Valid tRC tAA tRC tOHAH tOHZ Valid Data Input Valid Data Input tOH tOLAH tOH tASO Address Valid (No change) tAX Address Valid Address Valid tOLZ tOE Address (A1, A0) Address (A19-A2) CE1r DQ (Input) Address Valid tRC tAA tRC tCHAH OE tCHZ Valid Data Input Valid Data Input tOH tCLAH tOH tASC Address Valid (No change) tAX Address Valid Address Valid tCLZ tCE Address (A1, A0) Note: CE2r and WE must be High during read cycle. Note: CE2r and WE must be High during read cycle.

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00A 08/01/02 75V16F64GS16 ISSI PSRAM WRITE TIMING (CE1r Control) PSRAM WRITE TIMING (WE Control, Single Write Operation) Address Valid Data Input CE1r OE DQ (Input) Address Valid WE UB, LB tDS tDH tAS tAS tAH tWC tBS tOHCL tCW tWRC tWH tWS tBH tBS tWS Address CE1r DQ (Input) tWC OE Valid Data Input tOHz tOHCL tOES tBS Address Valid tCS tDS tDH tWP tWR tCP tCH tAS tBH WE UB, LB tOHAH tAS tAH Note: CE2r must be High during write cycle. Note: CE2r must be High during write cycle.

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00A 08/01/02 75V16F64GS16 ISSI PSRAM WRITE TIMING (WE Control, Continuous Write Operation) PSRAM READ / WRITE TIMING (CE1r Control) Address CE1r DQ (Input) tWC OE Valid Data Input tOHz tOHCL tOES tBS Address Valid tCS tDS tDH tWP tWR tAS tBH WE UB, LB tOHAH tAS tAH tBS Address CE1r DQ (Input) tWC OE Valid Data Input tCHZ tWH tOHCL tBS Write Address tWS tDS tDH tCW tWRC tASC tBH WE UB, LB tCHAH tAS tAH Read Address tOLz tOLz tOH tCLOL Read Data Output tCP tWH tWS Note: CE2r must be High during write cycle. Note: Write address is valid from either CE1r or WE of last falling edge.

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00A 08/01/02 75V16F64GS16 ISSI PSRAM READ / WRITE TIMING (CE1r Control) PSRAM READ / WRITE TIMING (READ = OE Control, WRITE = WE Control) Address CE1r DQ OE Write Data Input tOEH tWH tCHZ tWRC (Min) Write Address tWS tCE tWRC tCP tASC WE UB, LB tBH tAS tRC Read Address tCLz tOHCL tOH Read Data Output tOH tWH tWS tCHAH tBS Note: CE2r must be High during write cycle. Address CE1r DQ tWC OE Write Data Input tOHZ tOES tBS Write Address tDS tDH tWP tWR tASO tBH WE UB, LB tOHAH tAS tAH Read Address tOEH tOLz tOH Read Data Output Low Note: CE1r can be tied to Low for WE and OE controlled operation. When CE1r is tied to Low, output is exclusively controlled by OE.

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00A 08/01/02 75V16F64GS16 ISSI PSRAM READ / WRITE TIMING (READ = OE Control, WRITE = WE Control) Address CE1r DQ OE Write Data Input tOEH tOHZ Write Address tWR tOE tASO WE UB, LB tAS tRC Read Address tOES tDH Read Data Output tOH tBH tOLZ tOHAH tBS Low Note: CE1r can be tied to Low for WE and OE controlled operation. When CE1r is tied to Low, output is exclusively controlled OE.

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00A 08/01/02 75V16F64GS16 ISSI PSRAM POWER DOWN TIMING PSRAM STANDBY ENTRY TIMING AFTER READ WRITE CE1r DQ tCHH tCHS tC2LP tCSP CE2r High - Z Power Down Entry Power Down Mode Power Down Exit CE1r WE tCHOX tCHWX OE Active (Read) Standby Active (Write) Standby Note: Both tCHOX and tCHWX define the earliest entry timing for Standby mode. If either of timing is not satis- fied, it takes tRC (min) period from either last address transition of A0 and A1, or CE1r Low to High transition.

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00A 08/01/02 75V16F64GS16 ISSI PSRAM POWER UP TIMING 2 PSRAM POWER UP TIMING 1 CE1r Vccr tC2LH CE2r tCHS tCHH Vccr Min CE1r Vccr tC2HL CE2r tCHS tCHH 0 V Vccr Min tC2LP tCSP tC2HL Note: The tC2LH specifies from CE2r Low to High transition after Vccr reaches specified minimum level. CE1r must be brought to High prior to or together with CE2r Low to High transition. Note: It is recommended CE2r to be kept at Low during Vccr power-up. The tC2LH specifies after Vccr reaches specified minimum level.

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00A 08/01/02 75V16F64GS16 ISSI FLASH ERASE AND PROGRAMMING PERFORMANCE Parameter Min. Max. Typ.(1) Unit Remarks Sector Erase Time 0.2 1.0 s Excludes programming time prior to erasure Word Programming Time 6.0 µs Excludes system-level overhead Chip Programming Time 200 s Excludes system-level overhead Erase/Program Cycle 100,00 cycle Note: 1. Test conditions TA = +25 °C, VCC = 2.9V, Data = Checker

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00A 08/01/02 75V16F64GS16 ISSI PSRAM DATA RETENTION SWITCHING CHARACTERISTICS Symbol Parameter Conditions Min. Max. Unit VDR Vccr Data Retention Supply Voltage CE1r = CE2r ≥ VCCr -0.2V OR, 2.1 3.1 V CE1r = CE2r = VIH IDR Vccr Data Retention Supply Current 2.3 V ≤ VCCr ≤ 2.7 V,≥ mA VIN = VIH (1) or VIL CE1r = CE2r = VIH (1), IOUT = 0 MA IDR1 Vccr Data Retention Supply Current 2.3 V ≤VCCr ≤ 2.7 V,≥ µA VIN ≤ 0.2 V or VIN ≥ VCCr -2.0 V, CE1r = CE2r ≥ VCCr -0.2 V IOUT = 0 MA tDRS Data Retention SetupTime 2.7 V ≤ VCCr ≤ 3.1 V,≥ ns At Data Retention Entry tDRR Data Retention RecoveryTime 2.7 V ≤ VCCr ≤ 3.1 V,≥ ns After Data Retention ∆V/∆t VCCR Voltage Transition Time 0.5 V/µs Note: 1. 2.0 V ≤ VIN ≤ VCCr + 0.3 PSRAM DATA RETENTION TIMING Note: 1. 2.0 V ≤ VIH ≤ VCCr + 0.3 V 3.1V 2.7V 2.3V 4.0V GND tDRS tDRR Vccr CE2r CE1r CE1r = CE2r >Vccr - 0.2V or VIH(1) Min Data Retention Mode Data bus must be in High-Z at data retention entry ∆V/∆t ∆V/∆t

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00A 08/01/02 75V16F64GS16 ISSI PSRAM DATA RETENTION SWITCHING CHARACTERISTICS Symbol Parameter Conditions Min. Max. Unit CIN Input Capacitance VIN = 0 V pF COUT Output Capacitance VOUT = 0 V pF CIN2 Control Pin Capacitance VIN = 0 V pF CIN3 WP/ACC Pin Capacitance VIN = 0 V 21.5 pF Notes: 1. Test conditions TA = +25 °C, f = 1.0 MHz ISB2r VS VIN Cycle Time HANDLING OF PACKAGE: Please handle this package carefully since the sides of package created with acute angles. CAUTION: 1) The high voltage (VID) cannot be applied to address pins and control pins except RESET. Exception is when autoselect and sector group protection function are used. Then the high voltage (VID) can be applied to RESET. 2) Without the high voltage (VID) , sector group protection can be achieved by using “Extended Sector Group Protection” command. 2.5 2.0 1.5 1.0 0.5 0.0 200 400 600 800 1000 VIN Cycle Time (ns) ISB2r vs. VIN Cycle Time (VCCr = 3.0 V) ISB2r (mA) : RT = 25 °C : LT = -30 °C : HT = 85 °C

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00A 08/01/02 75V16F64GS16 ISSI K J H G F E D C B A SEATING PLANE A B C D E F G H J K A e E e D BALL GRID ARRAY – 65-Ball FBGA PACKAGE CODE: D - 9.0 mm x 9.0 mm Body, 0.8 mm Ball Pitch Symbol Min. Typ. Max. Units A 1.09 1.19 1.34 mm 0.29 0.39 0.49 mm D 8.90 9.00 9.10 mm 7.20 mm E 8.90 9.00 9.10 mm 7.20 mm e 0.80 mm

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00A 08/01/02 75V16F64GS16 ISSI

ORDERING INFORMATION

Industrial Range: -30ºC to +85ºC SRAM Data Boot Flash Bank Flash PSRAM Order Part No. Bus Section Organization Speed(ns) Speed(ns) Package IS75V16F64GS16-7080DI PC PC 65-ball FBGA