74LS181

DM54LS181 NSC | Alldatasheet

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Y Provides 16 arithmetic operations: add, subtract, com- pare, double, plus twelve other arithmetic operations Y Provides all 16 logic operations of two variables: exclu- sive-OR, compare, AND, NAND, OR, NOR, plus ten other logic operations Y Full lookahead for high speed arithmetic operation on long words Connection Diagram Dual-In-Line Package TL/F/9821–1 Order Number DM54LS181J, DM54LS181W or DM74LS181N See NS Package Number J24A, N24A or W24C Pin Names Description A0–A 3 Operand Inputs (Active LOW) B0–B 3 Operand Inputs (Active LOW) S0–S3 Function Select Inputs M Mode Control Input C n Carry Input F0–F 3 Function Outputs (Active LOW) A e B Comparator Output G Carry Generate Output (Active LOW) P Carry Propagate Output (Active LOW) Cna4 Carry Output C1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.

Absolute Maximum Ratings (Note) Supply Voltage 7V Input Voltage 7V Operating Free Air Temperature Range DM74LS 0 §Ct o a70§C Storage Temperature Range b65§Ct o a150§C Note: The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaran- teed. The device should not be operated at these limits. The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings. The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual device operation. Recommended Operating Conditions Symbol Parameter DM54LS181 DM74LS181 Units Min Max Min Nom Max VCC Supply Voltage 4.5 5.5 4.75 5 5.25 V VIH High Level Input Voltage 2 2 V VIL Low Level Input Voltage 0.7 0.8 V IOH High Level Output Current b0.4 b0.4 mA IOL Low Level Output Current 4 8 mA TA Free Air Operating Temperature b55 125 0 70 §C Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units(Note 1) VI Input Clamp Voltage V CC e Min, I I eb 18 mA b1.5 V VOH High Level Output V CC e Min, I OH e Max, DM54 2.5 V Voltage V IL e Max DM74 2.7 VOL Low Level Output V CC e Min, I OL e Max, DM54 0.4 VVoltage V IH e Min DM74 0.35 0.5 IOL e 4 mA, V CC e Min DM74 0.25 0.4 II Input Current @ Max V CC e Max, V I e 7V M input 0.1 Input Voltage V I e 10V (DM54) A n,B n 0.3 mASn 0.4 Cn 0.5 IIH High Level Input Current V CC e Max, V I e 2.7V M input 20 An,B n 60 mASn 80 Cn 100 IIL Low Level Input Current V CC e Max, V I e 0.4V M input b0.4 An,B n b1.2 mASn b1.6 Cn b2.0 IOS Short Circuit V CC e Max b20 b100 mAOutput Current (Note 2) ICC Supply Current V CC e Max, B n,C n e GND DM54 35 mA Sn,M ,A n e 4.5V DM74 37 Note 1: All typicals are at V CC e 5V, T A e 25§C. Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.

Switching Characteristics: DM54/DM74LS Symbol Parameter Conditions C L e 15 pF Units Min Max tPLH Propagation Delay M e GND 27 nstPHL Cn to C na4 20 tPLH Propagation Delay M e GND 26 nstPHL Cn to F 20 tPLH Propagation Delay M, S 1,S 2 e GND; 29 nstPHL A or B to G (Sum) S 1,S 3 e 4.5V 23 tPLH Propagation Delay M, S 0,S 3 e GND; 32 nstPHL A or B to G (Diff) S 1,S 2 e 4.5V 26 tPLH Propagation Delay M, S 1,S 2 e GND; 30 nstPHL A or B to P (Sum) S 0,S 3 e 4.5V 30 tPLH Propagation Delay M, S 0,S 3 e GND; 30 nstPHL A or B to P (Diff) S 1,S 2 e 4.5V 33 tPLH Propagation Delay M, S 1,S 2 e GND; 32 nstPHL Ai or B i to F i (Sum) S 0,S 3 e 4.5V 25 tPLH Propagation Delay M, S 0,S 3 e GND; 32 nstPHL Ai or B i to F i (Diff) S 1,S 2 e 4.5V 33 tPLH Propagation Delay M e 4.5V 33 nstPHL A or B to F (Logic) 29 tPLH Propagation Delay M, S 1,S 2 e GND; 38 nstPHL A or B to C na4 (Sum) S 0,S 3 e 4.5V 38 tPLH Propagation Delay M, S 0,S 3 e GND; 41 nstPHL A or B to C na4 (Diff) S 1,S 2 e 4.5V 41 tPLH Propagation Delay M, S 0,S 3 e GND; 50 nstPHL A or B to A e BS 1,S 2 e 4.5V; 62 RL e 2k X to 5.0V

Sum Mode Test Table I Function Inputs S0 e S3 e 4.5V, S1 e S2 e M e 0V Input Other Input Other Data Inputs Output Symbol Under Same Bit Under Test Apply Apply Apply Apply Test 4.5V GND 4.5V GND tPLH Ai Bi None Remaining Cn FitPHL A and B tPLH Bi Ai None Remaining Cn FitPHL A and B tPLH A B None None Remaining PtPHL A and B ,C n tPLH B A None None Remaining PtPHL A and B ,C n tPLH A None B Remaining Remaining GtPHL B A,C n tPLH B None A Remaining Remaining GtPHL B A,C n tPLH A None B Remaining Remaining Cna4tPHL B A,C n tPLH B None A Remaining Remaining Cna4tPHL B A,C n tPLH Cn None None All All Any F tPHL A B or C na4 Diff Mode Test Table II Function Inputs S1 e S2 e 4.5V, S0 e S3 e M e 0V Input Other Input Other Data Inputs Output Symbol Under Same Bit Under Test Apply Apply Apply Apply Test 4.5V GND 4.5V GND tPLH A None B Remaining Remaining FitPHL A B,C n tPLH B A None Remaining Remaining FitPHL A B,C n tPLH A None B None Remaining PtPHL A and B ,C n tPLH B A None None Remaining PtPHL A and B ,C n tPLH A B None None Remaining GtPHL A and B ,C n tPLH B None A None Remaining GtPHL A and B ,C n tPLH A None B Remaining Remaining A e BtPHL A B,C n tPLH B A None Remaining Remaining A e BtPHL A B,C n tPLH A B None None Remaining Cna4tPHL A and B ,C n tPLH B None A None Remaining Cna4tPHL A and B ,C n tPLH Cn None None All None C na4tPHL A and B

Logic Mode Test Table III Function Inputs S1 e S2 e M e 4.5V, S0 e S3 e 0V Input Other Input Other Data Inputs Output Symbol Under Same Bit Under Test Apply Apply Apply Apply Test 4.5V GND 4.5V GND tPLH A B None None Remaining Any FtPHL A and B ,C n tPLH B A None None Remaining Any FtPHL A and B ,C n Functional Description The ’LS181 is a 4-bit high speed parallel Arithmetic Logic Unit (ALU). Controlled by the four Function Select inputs (S0–S3) and the Mode Control input (M), it can perform all the 16 possible logic operations or 16 different arithmetic operations on active HIGH or active LOW operands. The Function Table lists these operations When the Mode Control input (M) is HIGH, all internal car- ries are inhibited and the device performs logic operations on the individual bits as listed. When the Mode Control input is LOW, the carries are enabled and the device performs arithmetic operations on the two 4-bit words. The device incorporates full internal carry lookahead and provides for either ripple carry between devices using the C na4 output, or for carry lookahead between packages using the signals P (Carry Propagate) and G (Carry Generate). In the ADD mode, P indicates that F is 15 or more, while G indicates that F is 16 or more. In the SUBTRACT mode, P indicates that F is zero or less, while G indicates that F is less than zero. P and G are not affected by carry in. When speed requirements are not stringent, it can be used in a simple ripple carry mode by connecting the Carry output (C na4) signal to the Carry input (C n) of the next unit. For high speed operation the device is used in conjunction with the 9342 or 93S42 carry lookahead circuit. One carry lookahead pack- age is required for each group of four ’LS181 devices. Carry lookahead can be provided at various levels and offers high speed capability over extremely long word lengths. The A e B output from the device goes HIGH when all four F outputs are HIGH and can be used to indicate logic equiv- alence over four bits when the unit is in the subtract mode. The A e B output is open-collector and can be wired-AND with other A e B outputs to give a comparison for more than four bits. The A e B signal can also be used with the Cna4 signal to indicate A l B and A k B. The Function Table lists the arithmetic operations that are performed without a carry in. An incoming carry adds a one to each operation. Thus, select code LHHL generates A minus B minus 1 (2s complement notation) without a carry in and generates A minus B when a carry is applied. Be- cause subtraction is actually performed by complementary addition (1s complement), a carry out means borrow; thus a carry is generated when there is no underflow and no carry is generated when there is underflow. As indicated, this de- vice can be used with either active LOW inputs producing active LOW outputs or with active HIGH inputs producing active HIGH outputs. For either case the table lists the oper- ations that are performed to the operands labeled inside the logic symbol. Function Table Mode Select Active LOW Operands Active HIGH Operands Inputs & F n Outputs & F n Outputs Logic Arithmetic Logic Arithmetic S3 S2 S1 S0 (M e H) (M e L) (C n e L) (M e H) (M e L) (C n e H) LLLL A A minus 1 A A LLLH A B AB minus 1 A a B A a B LLHL A a B AB minus 1 A BA a B L L H H Logic 1 minus 1 Logic 0 minus 1 LHLL A a B A plus (A a B)A B A plus AB LHLH B AB plus (A a B)B (A a B) plus AB LHHL A Z B A minus B minus 1 A Z B A minus B minus 1 LHHH A a B A a B AB AB minus 1 HLLL A B A plus (A a B) A a B A plus AB HLLH A Z B A plus B A Z B A plus B HLHL B A B plus (A a B) B (A a B) plus AB HLHH A a BA a B AB AB minus 1 H H L L Logic 0 A plus A * Logic 1 A plus A * HHLH A B AB plus A A a B (A a B) plus A HHHL A B A B minus A A a B( A a B) plus A HHHH A A A A minus 1 *Each bit is shifted to the next most significant position. **Arithmetic operations expressed in 2s complement notation.

TL/F/9821–3 Active Low Operands TL/F/9821–4 VCC e Pin 24 GND e Pin 12

TL/F/9821–5

Physical Dimensions inches (millimeters) Package (J) Order Number DM54LS181J 24-Lead Molded Dual-In-Line Package (N) Order Number DM74LS181N

DM54LS181/DM74LS181 4-Bit Arithmetic Logic Unit Physical Dimensions inches (millimeters) (Continued) Package (W) Order Number DM54LS181W LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd.

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