65WV2568DALL ISSI | Alldatasheet

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Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 1 Rev. A 02/09/2012 IS62/65WV2568DALL IS62/65WV2568DBLL Copyright © 2012 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason- ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances 256K x 8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM

FEATURES

  • High-speed access time: 35ns, 45ns, 55ns
  • CMOS low power operation – 36 mW (typical) operating – 9 µW (typical) CMOS standby
  • TTL compatible interface levels
  • Single power supply – 1.8V ± 10% Vcc (IS62/65WV2568DALL) – 2.5V–3.6V Vcc (IS62/65WV2568DBLL)
  • Fully static operation: no clock or refresh required
  • Three state outputs
  • Industrial temperature available
  • Lead-free available

DESCRIPTION

The ISSI IS62/65WV2568DALL and IS62/65WV2568DBLL are high-speed, 2M bit static RAMs organized as 256K words by 8 bits. It is fabricated using ISSI's high- performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. When CS1 is HIGH (deselected) or when CS2 is LOW (deselected) , the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS62/65WV2568DALL and IS62/65WV2568DBLL are packaged in the JEDEC standard 32-pin TSOP (TYPE I), sTSOP (TYPE I), and 36-pin mini BGA. FUNCTIONAL BLOCK DIAGRAM FEBRUARY 2012 A0-A17 CS1 OE WE 256K x 8 MEMORY ARRAYDECODER COLUMN I/O CONTROL CIRCUIT GND VCC I/O DATA CIRCUIT I/O0-I/O7 CS2

IS62/65WV2568DALL, IS62/65WV2568DBLL 2 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 02/09/2012 PIN DESCRIPTIONS A0-A17 Address Inputs CS1 Chip Enable 1 Input CS2 Chip Enable 2 Input OE Output Enable Input WE Write Enable Input I/O0-I/O7 Input/Output NC No Connection Vcc Power GND Ground 36-pin mini BGA (B) (6mm x 8mm) 32-pin TSOP (TYPE I), sTSOP (TYPE I) PIN CONFIGURATION 1 2 3 4 5 6 A B C D E F G H I/O4 I/O5 GND Vcc I/O6 I/O7 OE A10 CS2 WE NC NC CS1 A11 A17 A16 A12 A15 A13 I/O0 I/O1 Vcc GND I/O2 I/O3 A14 A11 A13 WE CS2 A15 VCC A17 A16 A14 A12 OE A10 CS1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0

IS62/65WV2568DALL, IS62/65WV2568DBLL Integrated Silicon Solution, Inc. — www.issi.com 3 Rev. A 02/09/2012 DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter Test Conditions Vcc Min. Max. Unit Voh Output HIGH Voltage Ioh = -0.1 mA 1.8V ± 10% 1.4 — V Ioh = -1 mA 2.5-3.6V 2.2 — V VoL Output LOW Voltage IoL = 0.1 mA 1.8V ± 10% — 0.2 V IoL = 2.1 mA 2.5-3.6V — 0.4 V VIh Input HIGH Voltage 1.8V ± 10% 1.4 Vcc + 0.2 V 2.5-3.6V 2.2 Vcc + 0.3 V VIL(1) Input LOW Voltage 1.8V ± 10% –0.2 0.4 V ILI Input Leakage GND ≤ VIn ≤ Vcc –1 1 µA ILo Output Leakage GND ≤ Vout ≤ Vcc, Outputs Disabled –1 1 µA Notes: For IS62/65WV2568DALL: VIL (min.) = -1.0V Ac (pluse width < 10ns). Not 100% tested. VIh (max.) = Vcc + 1.0V Ac; (pluse width < 10ns). Not 100% tested. For IS62/65WV2568DBLL: VIL (min.) = -2.0V Ac (pluse width < 10ns). Not 100% tested. VIh (max.) = Vcc + 2.0V Ac; (pluse width < 10ns). Not 100% tested. ABSOLUTE MAXIMUM RATINGS(1) Symbol Parameter Value Unit Vterm Terminal Voltage with Respect to GND –0.2 to Vcc+0.3 V tStg Storage Temperature –65 to +150 °C Pt Power Dissipation 1.0 W Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reli- ability. OPERATING RANGE (Vcc) Range Ambient Temperature IS62/65WV2568DALL IS62/65WV2568DBLL Commercial 0°C to +70°C 1.8V ± 10% 2.5V - 3.6V Industrial –40°C to +85°C 1.8V ± 10% 2.5V - 3.6V Automotive (A3) –40°C to +125°C 1.8V ± 10% 2.5V - 3.6V

IS62/65WV2568DALL, IS62/65WV2568DBLL 4 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 02/09/2012 AC TEST LOADS Figure 1 Figure 2 CAPACITANCE(1) Symbol Parameter Conditions Max. Unit cIn Input Capacitance VIn = 0V 8 pF cout Input/Output Capacitance Vout = 0V 10 pF Note: 1. Tested initially and after any design or process changes that may affect these parameters. AC TEST CONDITIONS Parameter 62WV2568DALL 62WV2568DBLL (Unit) (Unit) Input Pulse Level 0.4V to Vcc-0.2V 0.4V to Vcc-0.3V Input Rise and Fall Times 5 ns 5ns Input and Output Timing Vref Vref and Reference Level Output Load See Figures 1 and 2 See Figures 1 and 2 r1(Ω) 3070 3070 R2(Ω) 3150 3150 Vref 0.9V 1.5V Vtm 1.8V 2.8V 30 pF Including jig and scope OUTPUT VTM 5 pF Including jig and scope OUTPUT VTM

IS62/65WV2568DALL, IS62/65WV2568DBLL Integrated Silicon Solution, Inc. — www.issi.com 5 Rev. A 02/09/2012 POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Test Conditions Max. Max. Max. Unit 35ns 45ns 55ns Icc Vcc Dynamic Operating Vcc = Max., Com. 15 12 10 mA Supply Current Iout = 0 mA, f = fmAx Ind. 20 15 12 Auto. 25 20 15 typ.(2) 10 8 6 (TTL Inputs) VIn = VIh or VIL Ind. 0.1 0.1 0.1 CS1 = VIh , CS2 = VIL, Auto. 0.2 0.2 0.2 f = 1 MHz ISB2 CMOS Standby Vcc = Max., Com. 7 7 7 µA Current (CMOS Inputs) CS1 ≥ Vcc – 0.2V, Ind. 10 10 10 CS2 ≤ 0.2V, Auto. – 18 18 VIn ≥ Vcc – 0.2V, or typ. (2) 3 VIn ≤ 0.2V, f = 0 Note: 1. At f = fmAx, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at Vcc = 3.0V, Ta = 25oC and not 100% tested.

IS62/65WV2568DALL, IS62/65WV2568DBLL 6 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 02/09/2012 AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CS1 = OE = VIL, cS2 = WE = VIh) DATA VALIDPREVIOUS DATA VALID tAA tOHA tOHA tRC DOUT ADDRESS READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter 35ns 45ns 55ns trc Read Cycle Time 35 — 45 — 55 — ns tAA Address Access Time — 35 — 45 — 55 ns tohA Output Hold Time 10 — 10 — 10 — ns tAcS1/tAcS2 CS1/CS2 Access Time — 35 — 45 — 55 ns tDoe OE Access Time — 15 — 20 — 25 ns thzoe(2) OE to High-Z Output — 10 — 15 — 20 ns tLzoe(2) OE to Low-Z Output 5 — 5 — 5 — ns thzcS1/thzcS2(2) CS1/CS2 to High-Z Output 0 10 0 15 0 20 ns tLzcS1/tLzcS2(2) CS1/CS2 to Low-Z Output 10 — 10 — 10 — ns Notes: 1. Test conditions and output loading conditions are specified in the AC Test Conditions and AC Test Loads (Figure 1). 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

IS62/65WV2568DALL, IS62/65WV2568DBLL Integrated Silicon Solution, Inc. — www.issi.com 7 Rev. A 02/09/2012 AC WAVEFORMS READ CYCLE NO. 2(1,3) (CS1, CS2, OE Controlled) Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CS1= VIL. cS2=WE=VIh. 3. Address is valid prior to or coincident with CS1 LOW and cS2 hIgh transition. tRC tOHAtAA tDOE tLZOE tACS1/tACS2 tLZCS1/ tLZCS2 tHZOE HIGH-Z DATA VALID tHZCS ADDRESS OE CS1 CS2 DOUT

IS62/65WV2568DALL, IS62/65WV2568DBLL 8 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 02/09/2012 WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range) Symbol Parameter 35ns 45ns 55ns tWc Write Cycle Time 35 — 45 — 55 — ns tScS1/tscs2 CS1/CS2 to Write End 25 — 35 — 45 — ns tAW Address Setup Time to Write End 25 — 35 — 45 — ns thA Address Hold from Write End 0 — 0 — 0 — ns tSA Addrress Setup Time 0 — 0 — 0 — ns tPWe WE Pulse Width 30 — 35 — 40 — ns tSD Data Setup to Write End 15 — 20 — 25 — ns thD Data Hold from Write End 0 — 0 — 0 — ns thzWe WE LOW to High-Z Output — 20 — 20 — 20 ns tLzWe WE HIGH to Low-Z Output 5 — 5 — 5 — ns Notes: 1. Test conditions and output loading conditions are specified in the AC Test Conditions and AC Test Loads (Figure 1). 2. The internal write time is defined by the overlap of CS1 LOW, CS2 HIGH and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. AC WAVEFORMS WRITE CYCLE NO. 1 (CS1/CS2 Controlled, OE = HIGH or LOW) DATA-IN VALID DATA UNDEFINED tWC tSCS1 tSCS2 tAW tHA tPWE tHZWE HIGH-Z tLZWEtSA tSD tHD ADDRESS CS1 CS2 WE DOUT DIN

IS62/65WV2568DALL, IS62/65WV2568DBLL Integrated Silicon Solution, Inc. — www.issi.com 9 Rev. A 02/09/2012 AC WAVEFORMS WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle) WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle) DATA-IN VALID DATA UNDEFINED tWC tSCS1 tSCS2 tAW tHA tPWE tHZWE HIGH-Z tLZWEtSA tSD tHD ADDRESS OE CS1 CS2 WE DOUT DIN DATA-IN VALID DATA UNDEFINED tWC tSCS1 tSCS2 tAW tHA tPWE tHZWE HIGH-Z tLZWEtSA tSD tHD ADDRESS OE CS1 CS2 WE DOUT DIN

IS62/65WV2568DALL, IS62/65WV2568DBLL 10 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 02/09/2012 DATA RETENTION SWITCHING CHARACTERISTICS Symbol Parameter Test Condition Min. Max. Unit V Dr Vcc for Data Retention See Data Retention Waveform 1.5 3.6 V IDr Data Retention Current Vcc = 1.5V, CS1 ≥ Vcc – 0.2V, Com. — 7 µA CS2 ≤ 0.2V Ind. — 10 Auto. — 15 typ.(1) — 2 t SDr Data Retention Setup Time See Data Retention Waveform 0 — ns t rDr Recovery Time See Data Retention Waveform t rc — ns DATA RETENTION WAVEFORM (CS1 Controlled) DATA RETENTION WAVEFORM (CS2 Controlled) VCC CS1 ≥ VCC - 0.2V tSDR tRDR VDR CS1 GND 3.0V 2.2V Data Retention Mode VCC CS2 ≤ 0.2V tSDR tRDR VDR 0.4V CS2 GND 3.0 2.2V Data Retention Mode Note: 1. Typical values are measured at Vcc = VDr(min), TA = 25oC and not 100% tested.

IS62/65WV2568DALL, IS62/65WV2568DBLL Integrated Silicon Solution, Inc. — www.issi.com 11 Rev. A 02/09/2012

ORDERING INFORMATION

IS62WV2568DALL (1.8 ± 10%) Industrial Range: –40°C to +85°C Speed (ns) Order Part No. Package

55 IS62WV2568DALL-55TI TSOP , TYPE I

55 IS62WV2568DALL-55TLI TSOP , TYPE I, Lead-free

55 IS62WV2568DALL-55BI mini BGA (6mm x 8mm)

55 IS62WV2568DALL-55BLI mini BGA (6mm x 8mm), Lead-free

55 IS62WV2568DALL-55HI sTSOP , TYPE I

55 IS62WV2568DALL-55HLI sTSOP , TYPE I, Lead-free

IS62WV2568DBLL (2.5V - 3.6V) Industrial Range: –40°C to +85°C Speed (ns) Order Part No. Package

35 IS62WV2568DBLL-35HLI sTSOP , TYPE I

35 IS62WV2568DBLL-35TLI TSOP , TYPE I, Lead-free

45 IS62WV2568DBLL-45TI TSOP , TYPE I

45 IS62WV2568DBLL-45TLI TSOP , TYPE I, Lead-free

45 IS62WV2568DBLL-45BI mini BGA (6mm x 8mm)

45 IS62WV2568DBLL-45BLI mini BGA (6mm x 8mm), Lead-free

45 IS62WV2568DBLL-45HI sTSOP , TYPE I

45 IS62WV2568DBLL-45HLI sTSOP , TYPE I, Lead-free

IS65WV2568DBLL (2.5V - 3.6V) Automotive Range (A3): –40°C to +125°C Speed (ns) Order Part No. Package

45 IS65WV2568DBLL-45TLA3 TSOP , TYPE I, Lead-free

45 IS65WV2568DBLL-45HLA3 sTSOP , TYPE I, Lead-free

IS62/65WV2568DALL, IS62/65WV2568DBLL 12 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 02/09/2012

IS62/65WV2568DALL, IS62/65WV2568DBLL Integrated Silicon Solution, Inc. — www.issi.com 13 Rev. A 02/09/2012

IS62/65WV2568DALL, IS62/65WV2568DBLL 14 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 02/09/2012 NOTE : 1. CONTROLLING DIMENSION : MM . 2. Reference document : JEDEC MO-207 08/12/2008Package Outline